CN104899158A - Memory access optimization method and memory access optimization device - Google Patents

Abstract

Embodiments of the present invention provide a memory access optimization method and device. The memory access optimization method of the present invention includes: determining whether the cache access of the processor core misses the cache block, and in the case of the cache access misses the cache block, assigning a cache block to the access address through a block storage instruction in the cache, and The address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block. In the embodiment of the present invention, the CPU When the write instruction is executed and the cache misses, the number of accesses to the main memory is reduced, and the program execution efficiency is improved.

Description

Memory access optimization method and device

technical field

Embodiments of the present invention relate to the field of communication technologies, and in particular, to a memory access optimization method and device.

Background technique

The buffer memory is the most important part of the storage system. It was first conceived by Wilkes in 1951. It was proposed in order to make up for the speed difference between the central processing unit (Central Processing Unit, referred to as CPU) and the memory. The delay caused by the speed difference between memory, multi-level memory system is usually used in CPU. For example, using a storage structure of three levels: first-level cache, second-level cache, and Random Access Memory (RAM for short), the access speeds decrease sequentially, and the capacity increases sequentially. If the CPU executes a write command, the last level If the access of the cache (secondary cache) misses, it needs to access the RAM, resulting in long access delay, high power consumption, and poor performance.

In order to solve the above problems, in the prior art, when the CPU executes a write instruction and the cache misses, it does not access the RAM, but first uses the Data Cache Block Zero (DCBZ for short) instruction to directly write to the cache Allocate a cache block for the access address, and write all 0 data to the entire cache block. Since only all 0 data can be written to the entire cache block, that is, the cache block can only be initialized to all 0 data, so the follow-up still needs Use a write instruction (such as a store instruction) to write valid data into the cache, increasing memory access operations.

Contents of the invention

The embodiment of the present invention provides a memory access optimization method and device, which solves the problem that in the prior art, when the CPU executes a write instruction and the cache misses, only all 0 data can be written to the entire cache block, and the real When the data is valid, the write operation needs to be performed again, which increases the memory access operation and causes the problem of waste of power consumption.

In a first aspect, an embodiment of the present invention provides a memory access optimization method, including:

determining whether a cache access by a processor core misses a cache block;

If the cache access misses the cache block, a cache block is allocated for the access address through the block storage instruction in the cache, and the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block , writing the data indicated by the block storage instruction to the first data location of the allocated cache block, where the first data location of the allocated cache block is the allocated cache indicated by the block storage instruction The data location of the block.

In the first possible implementation manner of the first aspect, it also includes:

If the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block, then keep the data in the second data location of the allocated cache block or change the second data location of the allocated cache block to Write all "0" data values or "1" data values or write "0" data values and "1" data values to the second data position of the allocated cache block, the allocated cache block The second data location is a data location of the allocated cache block other than the first data location of the allocated cache block.

According to the first aspect or the first possible implementation of the first aspect, in the second possible implementation, it further includes:

If the cache access hits the cache block, then write the data indicated by the block storage instruction to the first data position of the hit cache block, and the first data position of the hit cache block is indicated by the block storage instruction The data location of the hit cache block.

According to the second possible implementation of the first aspect, the third possible implementation also includes:

If the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block, then keep the data at the second data position of the hit cache block or store all the data at the second data position of the hit cache block Write a "0" data value or a "1" data value or write a "0" data value and a "1" data value into the second data position of the hit cache block, and the hit cache block's second The data location is the data location of the hit cache block except the first data location of the hit cache block.

In a second aspect, an embodiment of the present invention provides a device for optimizing memory access, including:

A determining module, configured to determine whether the cache access of the processor core misses the cache block;

A processing module, configured to allocate a cache block for the access address through a block storage instruction in the cache if the cache access misses the cache block, and write the address unit of the address identification field indicated by the block storage instruction into the allocated cache The address identification field of the block, the data indicated by the block storage instruction is written to the first data position of the allocated cache block, and the first data position of the allocated cache block is indicated by the block storage instruction The data location of the allocated cache block.

In a first possible implementation manner of the second aspect, the processing module is further configured to keep the allocated cache block if the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block The data on the second data position of the allocated cache block or write all the "0" data value or "1" data value into the second data position of the allocated cache block or write the second data position of the allocated cache block writing a "0" data value and a "1" data value, the second data location of the allocated cache block being a data location of the allocated cache block other than the first data location of the allocated cache block .

According to the second aspect or the first possible implementation of the second aspect, in the second possible implementation, the processing module is further configured to, if the cache access hits a cache block, store the block indicated by the instruction The data is written to the first data position of the hit cache block, and the first data position of the hit cache block is the data position of the hit cache block indicated by the block store instruction.

According to the second possible implementation of the second aspect, in the third possible implementation, the processing module is further configured to: if the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block, then Keep the data on the second data position of the hit cache block or write all "0" data values or "1" data values into the second data position of the hit cache block or write the hit cache A "0" data value and a "1" data value are written in the second data position of the block, and the second data position of the hit cache block is the first data position of the hit cache block. The data location of the hit cache block.

The memory access optimization method and device of the embodiment of the present invention, by determining whether the cache access of the processor core misses the cache block, in the case that the cache access misses the cache block, assign a cache block to the access address in the cache through a block storage instruction , and the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block, so that the CPU When the write instruction is executed and the cache misses, the number of accesses to the main memory is reduced, and the program execution efficiency is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a flow chart of a memory access optimization method provided in Embodiment 1 of the present invention;

FIG. 2 is a flow chart of a memory access optimization method provided in Embodiment 2 of the present invention;

FIG. 3 is a schematic structural diagram of a memory access optimization device 300 provided in Embodiment 3 of the present invention;

FIG. 4 is a schematic structural diagram of a memory access optimization device 400 provided by Embodiment 4 of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

FIG. 1 is a flowchart of a memory access optimization method provided by Embodiment 1 of the present invention. The method of this embodiment is applicable to the case of writing data into the cache block by reducing memory access operations when the CPU executes the write instruction and the cache misses. The method is executed by a device for optimizing memory access, and the device is usually implemented in hardware and/or software. The method of the present embodiment comprises the steps:

S110. Determine whether the cache access of the processor core misses the cache block.

S120. If the cache access misses the cache block, allocate a cache block for the access address through the block storage instruction in the cache, and write the address unit of the address identification field indicated by the block storage instruction into the address identification field of the allocated cache block Writing the data indicated by the block storage instruction into the first data position of the allocated cache block, where the first data position of the allocated cache block is the data position of the allocated cache block indicated by the block storage instruction.

When the processor core accesses the memory, it needs to check the address sent by the CPU to determine whether the address unit to be accessed by the CPU is in the cache. If it is there, it is called a hit (Cache hit) cache block (Cache block), and the CPU can read/write it at an extremely fast speed; access. Accessing main memory when a cache block is missed reduces the efficiency of the system. In the prior art, instead of accessing the RAM when a Cache block is missed, the dcbz instruction is first used to directly allocate a cache block in the cache for the access address, and write all 0 data to the entire cache block. You can only write all 0 data to the entire cache block, that is, you can only initialize the cache block to all 0 data, so you still need to use a store command to write valid data into the cache, which increases the memory access operation. However, in the present embodiment, in the case of a Cache block miss, a cache block is allocated for the access address by a block storage instruction in the cache, and the address unit of the address identification field indicated by the block storage instruction is written to the allocated cache block. The address identification field writes the data indicated by the block storage instruction into the first data position of the allocated cache block, so that the data can be written into the first data position of the allocated cache block only by one block storage instruction , that is, it only needs to execute the block storage instruction once to complete the operation completed by executing two instructions in the prior art. In the prior art, the writing of valid data to the allocated cache is completed by a dcbz instruction and a store instruction block. Therefore, in this embodiment, when the CPU executes the write instruction and the cache misses, the times of accessing the main memory are reduced, and the program execution efficiency is improved.

Specifically, by determining whether the cache access of the processor core misses the cache block, if the cache access misses the cache block, a cache block is allocated to the access address through a block store instruction in the cache, and the cache block indicated by the block store instruction is The address unit of the address identification field is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block.

In the memory access optimization method provided in this embodiment, by determining whether the cache access of the processor core misses the cache block, in the case that the cache access misses the cache block, a cache block is assigned to the access address through a block storage instruction in the cache, And the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block, so that the CPU executes When the instruction is written and the cache misses, the number of accesses to the main memory is reduced, and the program execution efficiency is improved.

FIG. 2 is a flow chart of a memory access optimization method provided by Embodiment 2 of the present invention. Referring to Figure 2, the method of this embodiment may include:

S210. Determine whether the cache access of the processor core misses the cache block, if yes, execute S220, otherwise execute S240.

S220. In the cache, allocate a cache block for the access address through a block storage instruction, and write the address unit of the address identification field indicated by the block storage instruction into the address identification field of the allocated cache block, and write the data indicated by the block storage instruction The first data location of the allocated cache block is the data location of the allocated cache block indicated by the block storage instruction. If the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block, execute S230.

S230. Keep the data on the second data position of the allocated cache block or write all the data values "0" or "1" into the second data position of the allocated cache block or the second data position of the allocated cache block A data value of "0" and a data value of "1" are written in the data position, and the second data position of the allocated cache block is the data position of the allocated cache block except the first data position of the allocated cache block.

Wherein, a "0" data value and a "1" data value are written in the second data position of the allocated cache block, that is, a "0" data value and a "1" data value can be written in the second data position of the allocated cache block Any combination of "data values, for example, if the second data position of the allocated cache block is 10 bits, 1010101010 or 0101010101 can be written.

It should be noted that after the data indicated by the block storage instruction is written to the first data position of the allocated Cache block, if the allocated Cache block is not replaced, subsequent accesses will not cause Cache misses to the Cache block , that is, the next ordinary store operation will be an operation that hits the Cache block, so the data indicated by the ordinary store instruction can be written to the data position in the hit Cache block corresponding to the address indicated by the ordinary store instruction , thereby improving the hit rate of the Cache block.

S240. Write the data indicated by the block store instruction to the first data position of the hit cache block, where the first data position of the hit cache block is the data position of the hit cache block indicated by the block store instruction. If the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block, go to step 250 .

S250. Keep the data on the second data position of the hit cache block or write all data values of "0" or "1" into the second data position of the hit cache block or the second data position of the hit cache block. A data value of "0" and a data value of "1" are written in the data position, and the second data position of the hit cache block is the data position of the hit cache block except the first data position of the hit cache block.

Wherein, a "0" data value and a "1" data value are written into the second data position of the hit cache block, that is, a "0" data value and a "1" data value can be written into the second data position of the hit cache block. Any combination of "data values, for example, if the second data position of the allocated cache block is 10 bits, 1010101010 or 0101010101 can be written.

In the memory access optimization method provided in this embodiment, by determining whether the cache access of the processor core misses the cache block, in the case that the cache access misses the cache block, a cache block is assigned to the access address through a block storage instruction in the cache, And the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block, so that the CPU executes When the instruction is written and the cache misses, the number of accesses to the main memory is reduced, and the program execution efficiency is improved.

FIG. 3 is a schematic structural diagram of a memory access optimization device 300 provided by Embodiment 3 of the present invention. Referring to FIG. 3 , the device for optimizing memory access includes the following modules: a determination module 310 and a processing module 320 .

The determination module 310 is used to determine whether the cache access of the processor core misses the cache block; the processing module 320 is used to allocate a cache block for the access address in the cache through a block storage instruction if the cache access misses the cache block, and store the block The address unit of the address identification field indicated by the storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block, and the first data position of the allocated cache block is The data location is the data location of the allocated cache block indicated by the block storage instruction.

Further, the processing module 320 is further configured to keep the data at the second data position of the allocated cache block or the second data of the allocated cache block if the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block Write all "0" data values or "1" data values into the position or write "0" data values and "1" data values into the second data position of the allocated cache block, and the allocated cache block's first The second data location is the data location of the allocated cache block other than the first data location of the allocated cache block.

Further, the processing module 320 is also configured to write the data indicated by the block storage instruction to the first data position of the hit cache block if the cache access hits the cache block, and the first data position of the hit cache block is the block storage The data location of the hit cache block indicated by the instruction.

Further, the processing module 320 is further configured to keep the data at the second data position of the hit cache block or the second data of the hit cache block if the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block All write "0" data value or "1" data value in the position or write "0" data value and "1" data value in the second data position of the cache block of the hit, the first cache block of the hit The second data location is the data location of the hit cache block except the first data location of the hit cache block.

The memory access optimization device provided in this embodiment, by determining whether the cache access of the processor core misses the cache block, in the case of the cache access misses the cache block, assigns a cache block to the access address through a block storage instruction in the cache, And the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block, so that the CPU executes When the instruction is written and the cache misses, the number of accesses to the main memory is reduced, and the program execution efficiency is improved.

Correspondingly, referring to accompanying drawing 4, Fig. 4 is a schematic structural diagram of a memory access optimization device 400 provided in Embodiment 4 of the present invention, the memory access optimization device includes at least one processor 401, such as a CPU, and at least one network interface 404 , such as a physical network card, or other user interface 403 , as well as memory 405 and at least one communication bus 402 .

Wherein, the communication bus 402 is used to realize connection and communication between these components.

The network interface 404 is used to realize connection and communication between the physical host and the network, for example, the network interface 404 may be used to connect devices such as a physical network card and/or a physical switch.

Optionally, the user interface 403 may include a display, a keyboard, or other pointing devices, such as a mouse, a trackball (trackball), a touch panel, or a touch display screen.

The memory 405 may include a high-speed random access memory (RAM, Random Access Memory), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory 405 may also include at least one storage device located away from the aforementioned processor 401 .

In some implementations, the memory 405 stores the following elements, executable modules or data structures, or their subsets, or their extensions:

Operating system 4051, including various system programs, used to realize various basic services and handle hardware-based tasks;

The application module 4052 includes various application programs for realizing various application services.

The application module 4052 includes, but is not limited to, various units related to data exchange of virtual machines, such as a receiving unit, a configuration unit, an acquisition unit, and a synthesis unit.

Specifically, the processor 401 is configured to determine whether the cache access of the processor core misses the cache block; if the cache access misses the cache block, a cache block is allocated for the access address through a block storage instruction in the cache, and the block is stored The address unit of the address identification field indicated by the instruction is written into the address identification field of the allocated cache block, the data indicated by the block storage instruction is written into the first data position of the allocated cache block, and the first data of the allocated cache block The location is the data location of the allocated cache block indicated by the block store instruction.

Further, the processor 401 is further configured to keep the data at the second data position of the allocated cache block or the second data of the allocated cache block if the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block Write all "0" data values or "1" data values into the position or write "0" data values and "1" data values into the second data position of the allocated cache block, and the allocated cache block's first The second data location is the data location of the allocated cache block other than the first data location of the allocated cache block.

Further, the processor 401 is further configured to write the data indicated by the block storage instruction into the first data position of the hit cache block if the cache access hits the cache block, and the first data position of the hit cache block is the block storage The data location of the hit cache block indicated by the instruction.

Further, the processor 401 is further configured to keep the data at the second data position of the hit cache block or the second data of the hit cache block if the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block Write all "0" data values or "1" data values into the position or write "0" data values and "1" data values into the second data position of the allocated cache block, and the hit cache block's first The second data location is the data location of the hit cache block except the first data location of the hit cache block.

The memory access optimization device provided in this embodiment, by determining whether the cache access of the processor core misses the cache block, in the case of the cache access misses the cache block, assigns a cache block to the access address through a block storage instruction in the cache, And the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block, and the data indicated by the block storage instruction is written into the first data position of the allocated cache block, so that the CPU executes When the instruction is written and the cache misses, the number of accesses to the main memory is reduced, and the program execution efficiency is improved.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by program instructions and related hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (8)

1. A memory access optimization method, characterized in that, comprising: determining whether a cache access by a processor core misses a cache block; If the cache access misses the cache block, a cache block is allocated for the access address through the block storage instruction in the cache, and the address unit of the address identification field indicated by the block storage instruction is written into the address identification field of the allocated cache block , writing the data indicated by the block storage instruction to the first data location of the allocated cache block, where the first data location of the allocated cache block is the allocated cache indicated by the block storage instruction The data location of the block. 2. The method according to claim 1, further comprising: If the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block, then keep the data on the second data location of the allocated cache block or change the second data location of the allocated cache block to Write all "0" data values or "1" data values or write "0" data values and "1" data values to the second data position of the allocated cache block, the allocated cache block The second data location is a data location of the allocated cache block other than the first data location of the allocated cache block. 3. The method according to claim 1 or 2, further comprising: If the cache access hits the cache block, then write the data indicated by the block storage instruction to the first data position of the hit cache block, and the first data position of the hit cache block is indicated by the block storage instruction The data location of the hit cache block. 4. The method according to claim 3, further comprising: If the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block, then keep the data at the second data position of the hit cache block or store all the data at the second data position of the hit cache block Write a "0" data value or a "1" data value or write a "0" data value and a "1" data value into the second data position of the hit cache block, and the hit cache block's second The data location is the data location of the hit cache block except the first data location of the hit cache block. 5. A memory access optimization device, characterized in that, comprising: A determining module, configured to determine whether the cache access of the processor core misses the cache block; A processing module, configured to allocate a cache block for the access address through a block storage instruction in the cache if the cache access misses the cache block, and write the address unit of the address identification field indicated by the block storage instruction into the allocated cache The address identification field of the block, the data indicated by the block storage instruction is written to the first data position of the allocated cache block, and the first data position of the allocated cache block is indicated by the block storage instruction The data location of the allocated cache block. 6. The device according to claim 5, wherein the processing module is further configured to keep the allocated cache memory if the width of the data indicated by the block storage instruction is smaller than the width of the allocated cache block Data on the second data location of the block or write all "0" data values or "1" data values on the second data location of the allocated cache block or write the second data location of the allocated cache block Write a "0" data value and a "1" data value, the second data location of the allocated cache block is the data of the allocated cache block except the first data location of the allocated cache block Location. 7. The device according to claim 5 or 6, wherein the processing module is further configured to write the data indicated by the block storage instruction into the hit cache block if the cache access hits the cache block. In a data location, the first data location of the hit cache block is the data location of the hit cache block indicated by the block store instruction. 8. The device according to claim 7, wherein the processing module is further configured to keep the width of the hit cache block if the width of the data indicated by the block storage instruction is smaller than the width of the hit cache block Data on the second data position or write "0" data value or "1" data value in the second data position of the cache block of the hit or write the second data position of the cache block of the hit Entering a "0" data value and a "1" data value, the second data position of the hit cache block is the data position of the hit cache block except the first data position of the hit cache block.