CN104898135B - Satellite navigation signals analogy method and simulation system based on FPGA - Google Patents

Abstract

The invention discloses an FPGA-based satellite navigation signal simulation method and simulation system. The simulation method includes: receiving and storing the input system parameters and channel parameters, and sending interrupt signals at intervals to control the update of external input data; controlling the phase to generate text, pseudocode, subcode, carrier and subcarrier and modulating the output digital intermediate frequency signal. The present invention has the following advantages: based on FPGA construction, real-time, high-precision, and high-dynamic satellite navigation signals can be simulated; each functional module is independent of each other, easy to maintain and system upgrade; frequency point information and parameters come from external input, modulation engineering basis Frequency point and parameter information configure the modulation project to realize signal modulation at a specific frequency point; the modulation project is compatible with each frequency point of BDS, GPS, GLONASS and GALILEO satellite navigation systems, and meets the new requirements of the new signal system for the simulator.

Description

FPGA-based satellite navigation signal simulation method and simulation system

technical field

The invention relates to an FPGA-based satellite navigation signal simulation method and simulation system, belonging to the field of wireless communication.

Background technique

As a main positioning means, the global satellite navigation system has become the focus of the development of all countries in the world. At present, the GPS system is in the process of modernization, Glonass, Galileo and BDS and other systems are in the construction and improvement stage. During the development of each system, improving the performance of the satellite navigation system has become the focus of the development and construction of each system, so the new signal system has been demonstrated and applied. For example, Galileo and GPS systems have adopted new signal modulation methods such as TMBOC, CBOC, AltBOC and TDDM-BPSK. The bandwidth of the new signal system is wider, and most of them include two signals of pilot frequency and data, and the square wave subcarrier and subcode are added to the modulation method. The characteristics of the new signal system and its impact on the performance of the satellite navigation system need to be verified in theory and practice. At the same time, the change of the signal system poses challenges to the development of the receiver. It is an inevitable development process to develop the receiver according to the characteristics of the new signal system. The development of these works is inseparable from the development of the satellite navigation system simulator.

At present, the main structure of the satellite navigation system simulator system includes three types, which are software, hardware and combination of software and hardware. The software architecture simulator generates digital IF signal data files, which can be played back and up-converted to generate RF signals, but limited by computer hardware, it cannot simulate long-term, high-sampling-rate IF signals. The emulator functions of the hardware architecture are relatively fixed, and it is difficult to upgrade the system. For a simulator with a combination of software and hardware architecture, the software part is responsible for calculating signal parameters and writing navigation messages, and the hardware part is responsible for the modulation and up-conversion of intermediate frequency signals.

The hardware development platform of the hardware part in the prior art can be mainly divided into three categories: DSP, ASIC, and PLD.

DSP relies on instructions to realize data processing operations, which can only be processed serially, and cannot meet the design requirements when dealing with high-speed, large data streams, and parallel operations.

AISC refers to integrated circuits designed for special purposes. The disadvantages are that the internal logic structure cannot be changed, the reconfiguration is low, the development cycle is long, and the cost is high.

Among them, PLD is mainly divided into two categories: FPGA and CPLD. CPLD has less logic resources, and is mainly used in occasions with relatively simple logic and low power consumption. FPGA has rich logic resources and is suitable for large-scale digital signal processing.

In the prior art, the simulator is generally implemented for a specific function, such as the simulation of high-precision or high-dynamic signals. Moreover, the existing simulator architecture is mostly used to realize signal simulation of a single frequency point, and the simulation of multi-mode and multi-channel signals is not perfect enough, which is not convenient for user equipment testing.

Contents of the invention

The present invention aims to solve at least one of the above-mentioned technical problems.

For this reason, the first object of the present invention is to propose a kind of FPGA-based satellite navigation signal simulation method. This method is suitable for simulating high precision or high dynamic satellite navigation signals. At the same time, it is compatible with each frequency point of BDS, GPS, GLONASS and GALILEO systems. The hardware part can be controlled through the software part of the simulator, and the digital intermediate frequency satellite navigation signal of the corresponding frequency point can be selected and simulated to facilitate testing and effectively shorten the development of user equipment. Time, and meet the new requirements of the new signal system for the simulator.

The second object of the present invention is to propose a FPGA-based satellite navigation signal simulation system. The system is suitable for simulating high precision or high dynamic satellite navigation signals. At the same time, it is compatible with each frequency point of BDS, GPS, GLONASS and GALILEO systems. The hardware part can be controlled through the software part of the simulator, and the digital intermediate frequency satellite navigation signal of the corresponding frequency point can be selected and simulated to facilitate testing and effectively shorten the development of user equipment. Time, and meet the new requirements of the new signal system for the simulator.

In order to achieve the above object, the embodiment of the first aspect of the present invention discloses a satellite navigation signal simulation method based on FPGA, including the following steps 1) receiving and storing the input system parameters and channel parameters, and sending interrupt signals at intervals Control the update of the external input data; 2) Control the phase to generate message, pseudocode, subcode, carrier and subcarrier and modulate the output digital intermediate frequency signal; in step 2), further include: receiving message rate parameter, pseudocode NCO parameter, carrier NCO parameters, subcode length parameters, subcode rate parameters and pseudocode periodic pulses, output text bit by bit under the control of the pseudocode periodic pulses and the text rate parameters, and pass pseudocode DDS according to the pseudocode NCO parameters Control generates pseudo-code phase, read described pseudo-code by described pseudo-code phase control; Count described pseudo-code periodic pulse, output sub-code phase under the control of sub-code rate and sub-code length parameter, according to described sub-code phase The code phase control reads the subcode; generates the carrier phase through the carrier DDS control according to the carrier NCO parameter, and reads the sampling amplitude of the carrier by the carrier phase control to obtain the carrier; receives the pseudo code DDS The output phase control word of the control word, and according to the modulation factor, control the subcarrier phase hopping to output the subcarrier bit by bit.

According to the FPGA-based satellite navigation signal simulation method of the embodiment of the present invention, the software is used to simulate slowly changing errors, and can complete the calculation of these simulation models; the hardware completes the modulation of the signal to ensure that the signal can be generated in real time. The simulator can perform long-term signal testing; using the parameters delivered by the software to configure each module of the FPGA can flexibly change the functions of the FPGA without frequently modifying the FPGA program; based on the FPGA, the frequency point information and parameters come from external input , The modulation project configures the modulation project through frequency point information and parameters, which can realize signal modulation at a specific frequency point, and is compatible with each frequency point of BDS, GPS, GLONASS and GALILEO satellite navigation systems, which is convenient for testing and shortens the development time of user equipment; Each functional module is relatively independent, has good compatibility and scalability, is easy to maintain and is conducive to system upgrades.

In addition, the FPGA-based satellite navigation signal simulation method according to the above-mentioned embodiments of the present invention can also have the following additional technical features:

Further, in step 1), the input external parameters are also included, the high bits of the external parameters are the first valid data input, and the low bits are used to determine the type of the first valid data, and the first valid data includes Channel status parameters, system initialization parameters, initialization data delivery completion flag, NCO parameter update flag and new visible star flag.

Further, in step 1), according to the input external parameter, the high bit of the external parameter is the input second valid data, and the low bit is used for the type determination of the second valid data, and the second valid data includes channel Initialization parameters, NCO parameters and telegrams.

Further, in step 1), the update process of the external input data controlled by the interrupt signal is as follows: when the simulator is initialized and the signal starts to modulate, the interrupt starts counting; if the update period condition is met, an interrupt is sent to the external device and reset Counting and interrupt are used to control the external device to input the latest NCO parameters and the latest message for the simulator; if the update period condition is not met, continue timing.

Further, in step 2), the modulation process of the intermediate frequency signal is: receiving the message, the pseudocode, the subcode, the carrier and the subcarrier, and selecting the corresponding modulation according to the frequency point code Mode, the intermediate frequency modulation is performed on the pilot channel signal and the data channel signal, wherein, when the input pseudo code is updated and jumped, the delay is set by the register to realize the message, subcode, and subcarrier jumping with the pseudo code to meet the needs Under the condition of jumping at the same time.

Further, in step 2), it also includes: the data channel signal after intermediate frequency modulation passes through the first multiplier to control the power of the data channel relative to the pilot channel to obtain the data channel signal; the pilot channel signal after intermediate frequency modulation The channel signal passes through the second multiplier to control the power of the pilot channel relative to the data channel to obtain the pilot channel signal.

Further, in step 2), it also includes: receiving the amplitude control word and the output signal amplitude of the adder, using the third multiplier to control the amplitude of the satellite signal modulated by the channel relative to other satellite signals and outputting it, so as to simulate the receiver Each satellite navigation signal received with inconsistent power.

Further, in step 2), it also includes combining all channel signals to obtain the final digital intermediate frequency satellite navigation signal.

In order to achieve the above object, the embodiment of the second aspect of the present invention discloses a satellite navigation signal simulation system based on FPGA, including: a parameter receiving module, which is used to receive and store the input system parameters and channel parameters, and store the data Passed to the signal modulation module; the signal modulation module, according to the parameters received from the parameter receiving module, controls the generation of text, pseudocode, subcode, carrier and subcarrier, and modulates and outputs the digital intermediate frequency signal.

According to the satellite navigation signal simulation system based on FPGA of the embodiment of the present invention, the software is used to simulate slowly changing errors, and can complete the calculation of these simulation models; the hardware completes the modulation of the signal to ensure that the signal can be generated in real time. The simulator can perform long-term signal testing; using the parameters delivered by the software to configure each module of the FPGA can flexibly change the functions of the FPGA without frequently modifying the FPGA program; based on the FPGA, the frequency point information and parameters come from external input , The modulation project configures the modulation project through frequency point information and parameters, which can realize signal modulation at a specific frequency point, and is compatible with each frequency point of BDS, GPS, GLONASS and GALILEO satellite navigation systems, which is convenient for testing and shortens the development time of user equipment. Each functional module is relatively independent, has good compatibility and scalability, is easy to maintain and is conducive to system upgrades.

In addition, the FPGA-based satellite navigation signal simulation system according to the foregoing embodiments of the present invention can also have the following additional technical features:

Further, the parameter receiving module includes: a system parameter receiving module, configured to receive multiple channel state parameters and system parameters shared by multiple channels, wherein the system parameters include: frequency point code, pseudo code length, data Subcode length, pilot subcode length, data subcode rate, pilot subcode rate and cosine subcarrier flag; and a channel parameter receiving module for receiving the channel parameters of the channel modulated satellite signal, the channel parameters Including asterisk, initial value of code phase, pseudo-code NCO parameters, carrier NCO parameters, message and message rate.

Further, the signal modulation module includes: a message module, configured to receive the message from the channel parameter receiving module, and output the message bit by bit under the control of the message rate parameter; a pseudocode module, used to simulate When the device is initialized, the corresponding pseudo-code is generated according to the frequency point code, and the pseudo-code phase output of each channel is received when the simulator is running, and the pseudo-code is read and returned to the channel corresponding to the asterisk corresponding to the pseudo-code; The code module is used to generate corresponding subcodes according to the frequency point code when the simulator is initialized, and receives the subcode phases output by each channel when the simulator is running, reads the subcode and returns the subcode corresponding to the star The channel corresponding to the number; the carrier module, used to receive the carrier NCO parameter from the channel parameter receiving module, control the carrier DDS to output the carrier phase, sample the sine wave with the system clock frequency, and output the quantized carrier amplitude; the subcarrier Module, used to receive the cosine subcarrier flag bit and the phase control word output by the pseudocode DDS from the system parameter receiving module, and control the generation of subcarriers; the parameter selection module is used to receive the message, the pseudocode, The subcode, the subcarrier and the carrier, select corresponding parameters according to the frequency point code to output; and the intermediate frequency modulation module, according to the received message, the pseudo code, the subcode, the carrier and For the data of the sub-carriers, a corresponding modulation mode is selected according to the frequency code to complete signal modulation.

Further, an amplitude control module is also included, configured to receive the sum of the output signals of the data path IF modulation module and the pilot path IF modulation module, control the amplitude of the signal, and output channel digital IF signals.

Further, a signal combining module is also included, which is used to combine all channel signals to obtain the final digital intermediate frequency satellite navigation signal.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

Fig. 1 is the structural representation of the digital intermediate frequency satellite navigation signal simulator based on FPGA of the present invention;

Fig. 2 is a flow chart of the present invention's input data storage and update;

Fig. 3 is a flow chart of signal modulation in the present invention.

detailed description

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", " The orientations or positional relationships indicated by "vertical", "horizontal", "top", "bottom", "inner" and "outer" are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and Simplified descriptions, rather than indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and thus should not be construed as limiting the invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and should not be understood as indicating or implying relative importance.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

These and other aspects of embodiments of the invention will become apparent with reference to the following description and drawings. In these descriptions and drawings, some specific implementations of the embodiments of the present invention are specifically disclosed to represent some ways of implementing the principles of the embodiments of the present invention, but it should be understood that the scope of the embodiments of the present invention is not limited by this limit. On the contrary, the embodiments of the present invention include all changes, modifications and equivalents coming within the spirit and scope of the appended claims.

Embodiments of the present invention are described below in conjunction with the accompanying drawings.

Fig. 1 is the structural representation of the FPGA-based digital intermediate frequency satellite navigation signal simulator of the present invention. Please refer to Figure 1. This embodiment is described in detail in conjunction with the L1C frequency point. Those skilled in the art should understand that the embodiment is only used to explain the present invention and is not intended to limit the scope of protection of the present invention. For other frequency points, refer to The embodiments of the present invention are carried out, and details are not repeated here.

The present invention includes an FPGA-based satellite navigation signal simulation system, including a system parameter receiving module 1, a channel parameter module 2, an interrupt module 3, a pseudocode module 4, a subcode module 5, a channel module 6, a message module 7, and a phase control module. Module 8 , subcode phase module 9 , carrier module 10 , subcarrier module 11 , parameter selection module 12 , intermediate frequency modulation module 13 and amplitude control module 14 . The input and output ports of each module are shown in the table below.

Table 1 System parameter receiving module

Table 2 Channel parameter receiving module

Table 3 Interrupt Module

Table 4 Pseudocode module

Table 5 Subcode module

Table 6 Channel Modules

Table 7 Message module

Table 8 Phase Control Module

Table 9 Subcode phase module

Table 10 Carrier module

Table 11 Subcarrier module

Table 12 parameter selection module

Table 13 IF modulation module

Table 14 Amplitude Control Module

Some port parameters are explained here.

Data input parameters: The data input parameters have a bit width of 128 bits, the lower 16 bits provide channel number and FIFO classification information, which are used to judge and control the external input data to be correctly written into the corresponding FIFO or assigned to specific parameters, and the upper 112 bits are for transmission valid data.

Channel state parameter: The bit width of the channel state parameter is 2 bits, which can be divided into four states. Satellites with channel modulation are newly visible, satellites with channel modulation are previously visible, satellites with channel modulation change from visible to invisible, and satellites with no channel modulation. When the channel is in the first state, the channel needs to be re-initialized according to the new visible star information; when the channel is in the second state, the existing state of the channel should be maintained; when the channel is in the third state, the corresponding channel needs to be reset Operation; when the channel is in the fourth state, the corresponding channel needs to be reset.

Channel number parameter: Each channel of the simulator is instantiated from the same channel module. The channel number parameter is declared outside the channel and entered into the channel. Taking L1C as an example, the channel number parameter value is from 1 to 16. Each channel inputs a different channel number, which is used to judge the lower 16 bits of the data input parameter.

NCO parameters: The bit width of the NCO parameters is determined by the system clock frequency, pseudocode rate, light speed, analog accuracy, and analog range. In order to meet the high-precision and high-dynamic analog signal requirements of each frequency point, the system clock frequency is 256M, the pseudo-code rate is 1.023M (to ensure the compatibility of each frequency point of the simulator), and the speed of light is 3×10 ⁸ m/s , simulated speed accuracy 1mm/s, acceleration accuracy 5mm/s ² , jerk accuracy 5mm/s ³ , simulated maximum acceleration 50g, maximum jerk 500m/s ³ , then calculate and select the initial phase control word of the pseudocode to be 48 bits , pseudo-code frequency control word 48 bits, pseudo-code primary frequency control word 24 bits, pseudo-code secondary frequency control word 28 bits, carrier initial phase control word 36 bits, carrier frequency control word 36 bits, carrier primary frequency control word 26 bits , Carrier secondary frequency control word 28 bits.

Modulated signal: The modulated signal has the same bit width as the carrier parameter, and is quantized with 16 bits. The modulated signal is passed through the adder or multiplier to cause the bit width to widen, and the upper 16 bits are taken to ensure that the digital intermediate frequency signal output by the simulator can be used in the subsequent DAC module.

Parameter bit width: The bit width of some parameters is wider than the width required by the actual analog frequency point. In order to be compatible with each frequency point, take the maximum value of the required bit width in each frequency point.

FIG. 2 is a flowchart of input data storage and updating in the present invention, please refer to FIG. 2 .

Step 1: Update and store input data

The storage and update of simulator input data, including system parameter reception, channel parameter reception and interrupt control, execute corresponding functions under the unified control of the system clock.

1.1: System parameter reception

This step mainly completes the receiving and storing of system parameters. The details of the system parameters are shown in Table 1.

The input parameter received in this step is i_BusData_in, which is an external data input, the high bit of this parameter is the input first valid data, and the low bit is used for the type determination of the first valid data. Wherein, the first valid data includes: channel state parameters, system initialization data, initialization data delivery completion flag, NCO parameter update flag and new visible star flag.

Taking L1C as an example, in the initialization stage of the simulator, when the transmission system parameters are input externally, the lower 16 bits have three values: 1, 2, and 3. If it is 1, the parameter is the channel status parameter, received and stored in FIFO. Every time the status of the satellite changes, the external device will output the updated channel status parameter; if it is 2, the parameter is the system initialization data of the analog frequency point, and the code length, subcode length, subcode rate, cosine Subcarrier flag and frequency point code; if it is 3, this parameter is the completion flag of system initialization data delivery, which is valid after the initialization data delivery is completed. For data not stored in FIFO, set corresponding parameters in the system parameter receiving module to complete data reception.

After the simulator is initialized and enters the running stage, when the NCO parameters need to be updated or a new visible star appears, the external device transmits the NCO parameter update flag or the new visible star flag for the simulator under the control of the simulator interrupt. The NCO parameter update flag is used to control the update of the NCO parameters of the phase control module and the carrier module, and the new visible star flag is used to control the reinitialization of each channel. At this time, the value of the lower 16 bits of the input parameter i_BusData_in is 1, and the upper bit can take two bits to transmit the NCO parameter update flag and the new visible star flag.

1.2: Channel parameter reception

This step completes the receiving and storing of channel parameters.

The input parameter received in this step is i_BusData_in, which is an external data input, the high bit of this parameter is the input second valid data, and the low bit is used to determine the type of the second valid data. Wherein, the second valid data includes: channel initialization parameters, NCO parameters and message.

Specifically taking L1C as an example, during the initialization and operation phases of the system, the three types of data are stored in three different FIFOs in the specific channel parameter receiving module according to the low value of the input parameter i_BusData_in. The first type of data is the channel initialization parameters, including asterisk, message rate, pseudo code initial phase, pseudo code DDS initial phase control word and carrier DDS initial phase control word. This type of data is sent when the simulator is initialized and there are new visible stars. and receive; the second type is NCO parameters, including pseudo code frequency control word, pseudo code primary frequency control word, pseudo code secondary frequency control word, carrier frequency control word, carrier primary frequency control word, carrier secondary frequency control word and The channel signal amplitude control word, this type of data is sent and received at regular intervals; the third type is the message, the message is sent one subframe at a time, and the message is updated after the modulation is completed. The message comes from the input of external equipment, which is different from the pseudocode, subcode, carrier and subcarrier generated by FPGA in real time.

1.3: Interrupt Control

This step sends an interrupt signal at regular intervals to control the update of external input data.

After the simulator is initialized and the signal starts to be modulated, the interrupt module starts timing. If the time meets the update cycle conditions, the interrupt module will send an interrupt to the external device and reset the count. The interrupt is used to control the external device to input the latest NCO parameters and the latest message for the simulator to ensure the accuracy of the analog signal. If the time does not meet the update period condition, continue timing.

Taking L1C as an example, the fixed time interval of timing is 20ms. When the system clock is 256M, an interrupt is issued and the count is reset every time 5119999 (256M*20ms-1) is counted.

FIG. 3 is a flow chart of signal modulation in the present invention, please refer to FIG. 3 .

Step 2: Modulation of the signal

After the simulator is initialized, the modulation part receives the modulation of the data start signal from the system parameter receiving module 1 and the channel parameter receiving module 2 .

2.1: Phase Control

The phase control function is mainly completed by the phase control module. The phase control module receives the pseudo-code NCO parameters from the channel parameter receiving module, and controls the generation of the pseudo-code phase through the pseudo-code DDS.

The module judges the pseudo-code DDS output phase control word, and every time the highest bit overflows, the pseudo-code phase is incremented by one; the phase control module sends a pseudo-code period pulse every time a pseudo-code period passes, and the sub-code phase module and the message module receive this pulse Control subcode and message update. The sub-carrier module receives the pseudo-code DDS output by the phase control module and outputs a phase control word, which is used to control the generation of sub-carriers.

2.2: Carrier generation

The carrier is generated by the carrier module, which receives the carrier NCO parameters from the channel parameter receiving module, and controls the generation of the carrier phase through the carrier DDS.

The module uses the IP core to store the amplitude lookup table of the sine wave, and the amplitude is 16bit quantized. The address of the lookup table is to intercept the upper bits of the carrier DDS output phase control word. Take L1C as an example, intercept the upper 14 bits of the carrier DDS output control word, and the simulated pseudo-range accuracy can reach submillimeter level. Sine waves are read from phase 0 and cosine waves are read from phase π/2. The sine and cosine waves generated by the module meet the modulation of frequency point signals that have different requirements for the carrier phase of the pilot channel and the data channel.

2.3: Message generation

The message is generated by the message module, and the message module receives the message from the channel parameter receiving module, the rate parameter of the message and the pseudo-code period pulse from the phase control module.

The message length is one subframe, and is output bit by bit under the control of pulse and message rate parameters.

Taking L1C as an example, the width of each bit of the message is 10ms, and the period of the pseudocode is 10ms, and the message of 1 bit is updated when the period pulse of the pseudocode is valid. At the same time, set the message bit counting parameter. Every time a message is updated by 1 bit, the count is increased by one. When the count reaches 299 (300 bits per subframe), a message subframe update pulse is sent to set the FIFO3 read enable signal of the channel parameter receiving module to 1, thereby Update the input message of the message module.

2.4: Subcode phase generation

The sub-code phase is generated by the sub-code phase module, and the sub-code phase module receives the sub-code length parameter, the sub-code rate parameter and the pseudo-code period pulse output by the phase control module from the channel parameter module. Count the pulses of the pseudo-code period, and output the sub-code phase under the control of the sub-code rate and sub-code length parameters.

There is no subcode at the L1C frequency point, so there is no need to instantiate the subcode phase generation module.

2.5: Pseudo-code reading

The pseudo code module inputs the code phase parameter X, and reads the pseudo code value of the corresponding phase. The pseudo-code is generated when the simulator is initialized and stored in the form of an IP core. The IP core inputs the pseudo-code phase and outputs the corresponding pseudo-code value.

The generation principle of the parameter X is as follows:

Each channel module outputs the asterisk and pseudo code phase of the satellite modulated by the channel, which is used to generate the parameter X including the pseudo code phase of all channels and input to the pseudo code module. Parameter X is not an input or output of a certain module, but an intermediate parameter. Generation method: Taking L1C pseudo code reading as an example, the simulator contains 16 channels, the maximum asterisk is assumed to be 32 bits, and the bit width of the pseudo code phase parameter is 14. Then set the bit width of the parameter X to 448 (32×14), assign the corresponding pseudo code phase to the parameter X from the low bit to the high bit according to the satellite number, and the pseudo code phase value of the unmodulated satellite is 0 by default.

The pseudo-code module inputs the parameter X containing the pseudo-code phase of all channels, obtains the corresponding pseudo-code phase value from the parameter X according to the satellite number, reads the pseudo-code of the corresponding satellite number, and then reads the pseudo-code from low to high according to the asterisk The pseudo code value of 32 stars is assigned to the output data pseudo code and pilot pseudo code parameters, and then the corresponding pseudo code value is sent back to the channel module according to the asterisk.

Taking L1C as an example, 32 IP cores are set to store the pseudo codes of 32 stars respectively, and the pseudo code phases of the corresponding asterisks are input respectively, and the corresponding pseudo code values are output.

2.6: Subcode reading

The subcode module inputs the subcode phase parameter Y, and reads the subcode value of the corresponding phase. The subcode is generated when the simulator is initialized and stored in the form of an IP core. The IP core inputs the subcode phase and outputs the corresponding subcode value.

The generation principle of the parameter Y is as follows:

Each channel module outputs the asterisk and pilot subcode phase of the satellite modulated by the channel, which is used to generate the parameter Y including the subcode phases of all channels and input to the subcode module. Parameter Y is not an input or output of a certain module, but an intermediate parameter. Generation method: The simulator contains 16 channels, the maximum asterisk is assumed to be 32, and the subcode phase parameter bit width is assumed to be 11 bits. Then set the parameter Y bit width to 352 (32×11), assign the corresponding subcode phase from low to high according to the satellite number to the parameter Y, and the pseudo code phase of the unmodulated satellite is 0 by default.

The subcode module inputs the parameter Y including the subcode phase of all channels, obtains the corresponding subcode phase value from the parameter Y according to the satellite number, reads the subcode of the corresponding satellite number, and then reads the subcode according to the satellite number from low to high. The subcode value of 32 satellites is assigned to the output pilot subcode parameter, and then the subcode value is sent back to the channel module according to the satellite number.

Generally, the data subcode is relatively short and each channel is the same, so it only needs to judge the phase of the data subcode in the channel, and assign the corresponding data subcode value to the data subcode input of the IF modulation module.

There is no subcode at the L1C frequency point, so there is no need to instantiate the subcode module.

2.7: Subcarrier generation

The subcarrier is generated by the subcarrier module. The module receives the output phase control word of the pseudo-code DDS of the phase control module and multiplies it by the modulation coefficient of the BOC modulation mode. 10, 11 cyclical changes, using this change and BOC modulation coefficient to control the subcarrier phase jump and output subcarriers bit by bit, including BOC (1,1) subcarriers, BOC (6,1) subcarriers and BOC (15, 10) Subcarriers.

Take the L1C frequency point, the modulation mode is TMBOC (6,1,4/33) as an example, the sub-carriers include BOC (1,1) sub-carriers, BOC (6,1) sub-carriers, and the channel module needs to instantiate two sub-carriers The module inputs different modulation coefficients to generate BOC(1,1) subcarriers and BOC(6,1) subcarriers respectively, and judges the pseudo code phase, and inputs the corresponding subcarrier values into the intermediate frequency modulation module.

2.8: Parameter selection

The parameter selection is realized by the parameter selection module. The message generated in steps 2.1-2.7, data pseudocode, pilot pseudocode, data subcode, pilot subcode, BOC(1,1) subcarrier, BOC(6,1) subcarrier, BOC(15,10) The subcarrier, sine carrier and cosine carrier are input to the parameter selection module. The parameter selection module generates the corresponding data subcode according to the frequency point code and the phase of the data subcode, and outputs the corresponding message, pseudocode, subcode, subcarrier and carrier.

Taking the L1C frequency point as an example, the input parameters are selected to output text, data channel pseudo code, BOC(1,1) subcarrier, cosine carrier for the data channel, and output pilot channel pseudo code, BOC(1, 1) Subcarrier and cosine carrier in time division with BOC(6,1).

2.9: Data channel IF modulation

The intermediate frequency modulation module of the data path receives text, pseudocode, subcode, carrier and subcarrier, and selects the corresponding modulation method according to the frequency point code, including BPSK, BOC, TMBOC, CBOC, QPSK, ALTBOC and TD-ALTBOC (where ALTBOC and TD- ALTBOC can be realized by using QPSK and BPSK) to complete the modulation of the data path signal.

The input data needs to be aligned, that is, when the input pseudo code is updated and jumped, the message, subcode, and subcarrier are also updated and jumped at the same time, which can be realized by setting registers during the transmission of each parameter.

Take the L1C frequency point as an example, input without subcarrier, the module judges the frequency point code, and according to the BOC(1,1) modulation method, the text, pseudocode, and subcode are ORed together to obtain a value, and the value is judged as 1 or 0 Maintain the current phase or reverse the phase of the carrier, and then output the carrier amplitude.

2.10: IF modulation of pilot channel

The intermediate frequency modulation module of the data path receives the pseudocode, subcode, carrier and subcarrier, and selects the corresponding modulation method according to the code of the frequency point, including BPSK, BOC, TMBOC, CBOC, QPSK, ALTBOC and TD-ALTBOC (wherein ALTBOC and TD-ALTBOC can be Adopt QPSK and BPSK to realize), complete the modulation of pilot channel signal.

The input data needs to be aligned, that is, when the input pseudocode updates and jumps, the subcode and subcarrier also update and jump at the same time, which can be realized by setting registers during the transmission of each parameter.

Take the L1C frequency point as an example, input no subcarrier, the module judges the frequency point code, and according to the TMBOC (6, 1, 4/33) modulation method first OR the pseudo code and sub code to get a value, and judge that the value is 1 Or 0 to maintain the current phase or invert the carrier, and then output the carrier amplitude.

2.11: Relative amplitude control of data path

According to the modulated signal output by the intermediate frequency modulation module of the data path, the power of the data path relative to the pilot path is controlled through the first multiplier to obtain a data path signal.

2.12: Relative amplitude control of pilot channel

The modulated signal output by the intermediate frequency modulation module of the pilot channel passes through the second multiplier to control the power of the pilot channel relative to the data channel to obtain a pilot channel signal.

The data path signal and the pilot path signal are added by an adder to take the upper 16 bits as the input of the amplitude control module.

2.13: Channel signal amplitude control

The amplitude control module receives the amplitude control word from the channel parameter receiving module and the output signal amplitude of the adder in 2.12, and uses the third multiplier to control and output the relative amplitude of each satellite, simulating the actual signal received by the receiver Satellite navigation signals with inconsistent power.

2.14: Channel signal merge

Taking L1C as an example, the simulator is set with 16 channels, and each channel module modulates a navigation signal of a visible star, and the output signal amplitude of the channel module that does not modulate the visible star is zero by default. The adder is used to realize the sum of the modulation signals signal_1, signal_2, ..., signal_k, ... signal_16 of each channel, and the upper 16 bits are taken to obtain the final digital intermediate frequency navigation analog signal.

In addition, other components and functions of the FPGA-based satellite navigation signal simulation method and system of the embodiment of the present invention are known to those skilled in the art, and will not be repeated in order to reduce redundancy.

In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the invention is defined by the claims and their equivalents.

Claims (10)

1. a satellite navigation signal simulation method based on FPGA, is characterized in that, comprises the following steps: 1) Receive and store the input system parameters and channel parameters, and send interrupt signals at intervals to control the update of external input data; and 2) Control phase to generate message, pseudocode, subcode, carrier and subcarrier, modulate and output digital intermediate frequency signal; In step 2), it further includes: receiving message rate parameter, pseudocode NCO parameter, carrier NCO parameter, subcode length parameter, subcode rate parameter and pseudocode period pulse, according to the pseudocode period pulse and the message rate Under the control of the parameters, the message is output bit by bit, and the pseudo code phase is generated through the pseudo code DDS control according to the pseudo code NCO parameter, and the pseudo code is read by the pseudo code phase control; the pseudo code periodic pulse is counted, Under the control of the subcode rate and subcode length parameters, the subcode phase is output, and the subcode is read according to the subcode phase control; the carrier phase is generated by the carrier DDS control according to the carrier NCO parameter, and is controlled by the carrier phase Read the sampling amplitude of the carrier to obtain the carrier; receive the output phase control word of the pseudo code DDS, and according to the modulation factor, control the jump of the subcarrier phase to output the subcarrier bit by bit; Wherein, in step 2), the modulation process of the intermediate frequency signal is: receiving the message, the pseudocode, the subcode, the carrier and the subcarrier, and the pilot channel signal and the data channel signal Carry out intermediate frequency modulation, wherein, when the pseudo-code is updated and hopped, the delay is set by the register to realize the simultaneous hopping of the message, sub-code, and sub-carrier along with the pseudo-code under the condition that the required hopping is satisfied. 2. the satellite navigation signal simulation method based on FPGA according to claim 1, is characterized in that, in step 1) in, also comprises the first external parameter of input, the high position of described first external parameter is the first of input Valid data, the lower bits are used to determine the type of the first valid data, and the first valid data includes channel state parameters, system initialization parameters, initialization data delivery completion flags, NCO parameter update flags, and new visible star flags. 3. the satellite navigation signal simulation method based on FPGA according to claim 2, is characterized in that, in step 1) in, also comprises the second external parameter of input, the high position of described second external parameter is the second of input For valid data, the lower bits are used to determine the type of the second valid data, and the second valid data includes channel initialization parameters, NCO parameters and message. 4. the satellite navigation signal simulation method based on FPGA according to claim 1, is characterized in that, in step 1) in, the renewal process of described interruption signal control external input data is: when simulator initialization finishes signal and starts to modulate ,start the timer; If the update cycle conditions are met, an interrupt is sent to the external device and the count is reset, and the interrupt is used to control the external device to input the latest NCO parameters and the latest message for the simulator; If the update period condition is not met, continue timing. 5. the satellite navigation signal simulation method based on FPGA according to claim 1, is characterized in that, in step 2) in, also comprises: described data path signal after intermediate frequency modulation passes through first multiplier control data path with respect to The power of the pilot channel is used to obtain the signal of the data channel; The pilot channel signal after IF modulation passes through the second multiplier to control the power of the pilot channel relative to the data channel to obtain the pilot channel signal. 6. the satellite navigation signal simulation method based on FPGA according to claim 5, is characterized in that, in step 2) in, also comprises: receive the signal of amplitude control word and adder output, adopt the 3rd multiplier control passage to place The amplitude of the satellite signal relative to other satellite signals is modulated and output, so as to simulate the satellite navigation signals with inconsistent power received by the receiver. 7. according to the arbitrary described satellite navigation signal simulation method based on FPGA of claim 1-6, it is characterized in that, in step 2), also comprise all channel signals are merged, obtain the digital intermediate frequency satellite navigation signal of final simulation. 8. A satellite navigation signal simulation system based on FPGA, is characterized in that, comprises: The parameter receiving module is used to receive and store the input system parameters and channel parameters, and transmit the data to the signal modulation module, wherein the parameter receiving module includes: A system parameter receiving module, configured to receive status parameters of multiple channels and system parameters shared by multiple channels, wherein the system parameters include: frequency point code, pseudocode length, data subcode length, pilot subcode length , data subcode rate, pilot subcode rate and cosine subcarrier flag; and The channel parameter receiving module is used to receive the channel parameters of the channel modulated satellite signal, the channel parameters include asterisk, code phase initial value, pseudo code NCO parameters, carrier NCO parameters, message and message rate; The signal modulation module, according to the parameters received from the parameter receiving module, controls the generation of text, pseudocode, subcode, carrier and subcarrier, selects the corresponding modulation mode according to the frequency point code, modulates and outputs the digital intermediate frequency signal, wherein, The signal modulation module includes: A message module, configured to receive the message from the channel parameter receiving module, and output the message bit by bit under the control of the message rate parameter; The pseudo-code module is used to generate corresponding pseudo-codes according to the frequency point code when the simulator is initialized, receive the pseudo-code phases output by each channel when the simulator is running, read the pseudo-codes and return the corresponding pseudo-codes The channel corresponding to the asterisk; The subcode module is used to generate corresponding subcodes according to the frequency point code when the simulator is initialized, receive the subcode phases output by each channel when the simulator is running, read the subcodes and return the corresponding subcodes The channel corresponding to the asterisk; The carrier module is used to receive the carrier NCO parameter from the channel parameter receiving module, control the carrier DDS to output the carrier phase, sample the sine wave at the system clock frequency, and output the quantized carrier amplitude; The subcarrier module is used to receive the cosine subcarrier flag and the phase control word output by the pseudo code DDS from the system parameter receiving module, and control the generation of subcarriers; A parameter selection module, configured to receive the message, the pseudo-code, the sub-code, the sub-carrier and the carrier, and select the corresponding parameter output according to the frequency point code; and The intermediate frequency modulation module selects a corresponding modulation method according to the frequency point code according to the received data of the message, the pseudocode, the subcode, the carrier and the subcarrier, and completes signal modulation. 9. the satellite navigation signal simulation system based on FPGA according to claim 8, is characterized in that, also comprises amplitude control module, is used to receive the sum of the output signal of data road intermediate frequency modulation module and pilot frequency road intermediate frequency modulation module, control Signal amplitude and output channel digital IF signal. 10. according to the satellite navigation signal simulation system based on FPGA of claim 8 or 9, it is characterized in that, also comprise signal combining module, be used to combine all channel digital intermediate frequency signals.