CN104866345B - The storage method of executable code under a kind of ARMv7m frameworks - Google Patents

Abstract

The present invention provides a method for storing executable codes under the ARMv7m architecture, which is composed of five logical units including compiling and burning programs, startup programs, FPB related programs, execution programs, and bus exception handling programs, and a slice of RAM space is allocated through the FPB related programs Associated with an address that is not associated with the physical Flash, it is used as a storage space for storing executable code for the CPU core to obtain and execute machine instructions. At the same time, the RAM space can be dynamically updated to a new value, and can be reset and associated with a new Flash address by the FPB. In this way, the method of the present invention only uses a small piece of internal Flash to store the FPB management code, and can expand the storage space of the executable code of the CPU to 512MB by using a small RAM space and cheap off-chip Flash.

Description

A storage method for executable code under ARMv7m architecture

technical field

The invention relates to a method for storing executable codes under the ARMv7m architecture, in particular to a method for storing executable codes on an off-chip XIP-free Flash under the ARMv7m architecture.

Background technique

In a computer system, the CPU needs to fetch machine instructions first, then decode them, and finally execute the machine instructions. Machine instructions need to be stored in memory directly addressable by the CPU before they can be fetched by the CPU. The memory directly addressable by the CPU is generally an on-chip RAM, an off-chip parallel bus RAM, or a parallel bus supporting XIP (on-chip execution) function Flash memory. The unit storage space price of such a memory is relatively high, so the embedded MCU generally does not configure a large-capacity memory that can store the execution code. This limits the software functionality available on the embedded MCU. If the space for storing and executing code is expanded by expanding the memory of the parallel bus, the PIN resources of the CPU will be occupied, and the available IO resources will be reduced. At present, there is a Flash with SPI bus with XIP function on the market, which can be used to store and execute code on a specific CPU that supports SPIXIP Flash. But this makes the selection of product solutions limited to specific Flash and CPU devices.

ARM v7m is the seventh version of the MCU core architecture released by ARM. Under this architecture, due to the difference in CPU options, sub-models such as Cortex-M3 and Cortex-M4 are derived. Compared with the previous ARM9/ARM11 and other processors, the chip performance of the MCU based on this architecture has been significantly improved, and it has a wide range of applications in industrial control, communication equipment, intelligent peripherals and other fields. However, the MCU of the ARM v7m architecture is difficult to be applied to devices in complex application scenarios due to the above-mentioned limitation of the space that can directly store executable codes. This makes devices with complex application scenarios have to use ARM9/ARM11 processors with low chip performance, or high-cost processors such as ARM v7r and ARM v7a, which in turn affects the price of products.

In the ARMv7m architecture, there is a CPU optional component called FPB (Flash Patch and Breakpoint Module), which is generally used to implement the online debugging function in the processor of the ARMv7m architecture. Although FPB is an optional component, most of the MCU implementations of ARMv7m currently have FPB components. The operating mechanism of FPB is to temporarily take over the access of the CPU core to the Flash memory of certain addresses, replace the Flash content on the corresponding address with the breakpoint code or the instruction code stored in the specified RAM and return it to the CPU core, so that the CPU core can Execute to the breakpoint instruction and stop running, or execute the replaced target instruction code. In the ARMv7m architecture, it is also agreed that the 512MB space at the address 0x00000000~0x1FFFFFFF is the Flash space that can store the execution code. Even if the CPU only has 16KB of Flash space, the address space from 0x4000 to 0x1FFFFFFF is still treated by the CPU core as the Flash address space, and FPB can also take effect on this address that is not actually associated with the physical Flash, that is, through FPB associates a piece of RAM space with an address that is not associated with physical Flash, and uses it as a storage space for storing executable code, which is used by the CPU core to obtain and execute machine instructions; at the same time, this piece of RAM space can be dynamically updated It is a new value and can be reset by FPB to be associated with a new Flash address. When the execution code on the RAM is not in use, it can also be stored on SPINorFlash or NandFlash without XIP function outside the chip, and there is no great requirement for the storage device.

Therefore, if a small piece of on-chip Flash can be used to store the FPB management code, the storage space of the executable code of the CPU can be expanded to 512MB by using a small RAM space and cheap off-chip Flash. In view of this, the inventor has devoted himself to studying the realization method of this idea and has just come out of the present invention.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for storing executable codes under the ARMv7m architecture, which consumes less memory and does not depend on a specific Flash device, and can expand the execution space of program codes to 512MB.

The present invention is realized in the following way: a method for storing executable codes under the ARMv7m architecture, in compiling and burning programs, through the parameter configuration of the compiler, the startup program, FPB associated program, execution program, bus exception handling program and The system and the driver program are positioned on the Flash address space associated with the physical memory on the CPU chip, and other programs are positioned on the Flash address space that is not associated with the physical memory on the CPU chip; compile and generate a binary image file of the target executable code; then, The software developer burns the startup program, FPB associated program, execution program, bus exception handling program and system and driver program to the CPU physical memory at the specified address when compiling, and burns the other programs into the off-chip Flash In the first stage after the device is powered on, the startup program first initializes the basic operating environment of the system and device drivers, initializes FPB components, and software global variables in turn, and then the startup program extracts the first instruction code of the subsequent program The Flash execution address is sent to the FPB associated program to carry out FPB associated processing, and the FPB associated program can be called by the startup program and the execution program; the incoming address parameter of the FPB associated program is the required associated execution The Flash execution address of the first instruction code, execute "the process of loading the executed code and performing FPB association on it"; after obtaining the Flash execution address of the code passed in by the caller, check whether the code at the corresponding address has been loaded If the code is not loaded into the RAM buffer, the corresponding code is loaded into the RAM buffer from the off-chip Flash through the Flash driver. After the loading is completed, the code corresponding to the program instruction address is calculated in the RAM. Assuming that the FPB component has a total of n units available, each unit is associated with m bytes of Flash address space, and the size of the RAM buffer is defined as k bytes, then k bytes should be at least equal to n*m byte, by setting FPB, the RAM address of the storage address beginning n*m bytes is associated with the Flash execution address of the code; the execution program is called after the FPB associated program, and the incoming of the execution program Address parameter is identical with the address parameter that described FPB associated program imports, and described execution program sends the address parameter of import into the PC register of CPU, and then CPU will automatically complete follow-up code execution process; When described execution program execution process When a bus exception is caused, the bus exception handler is called and executed. By querying the exception status register of the CPU, it is known whether the exception is caused by CPU instruction fetching or CPU data access. If the exception is caused by CPU fetching instruction, the exception will be The address is used as a parameter to call the FPB associated program to carry out re-associated processing. If the exception is caused by CPU data access, then the bus exception handler continues to check whether the instruction that causes the exception is an LDM multi-register load instruction. exception handler generation Complete the function of the LDM instruction for the CPU, then return the next instruction code address to allow the CPU to continue to execute, if not, use the data address to be accessed as a parameter to call the FPB associated program to perform re-association processing.

Further, if the CPU has a DMA function, the FPB-associated program also executes the "process of loading code segments that are predicted to be executed soon" after executing the "process of loading the executed code and performing FPB association" , the "process of loading a code segment that is predicted to be executed soon" opens up a piece of RAM space equal to the RAM buffer size k bytes of the "process of loading the executed code and performing FPB association" as an auxiliary RAM buffer , then load the k-byte code following the loaded code on the off-chip Flash into the auxiliary RAM buffer, the loading process is realized by DMA; And the execution result of the "process of loading the code segment predicted to be executed" is used to accelerate the next "process of loading the executed code and performing FPB association on it".

The present invention has the following advantages:

The present invention provides a method for storing execution codes on common ARMv7m processors and low-cost off-chip memory. This method can expand the execution space of program codes to 512MB, consumes less memory, and does not depend on specific The Flash device has low implementation cost and obvious implementation benefits, and is conducive to implementing complex application scenarios on ARMv7m-based MCUs, expanding the application scenarios of ARMv7m MCUs, and reducing the cost of corresponding products.

Description of drawings

The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is a flow chart of the execution of the method of the present invention.

Detailed ways

As shown in Fig. 1, the method of the present invention is mainly participated by five logic units, namely: compiling and burning program 1, startup program 2, FPB associated program 3, execution program 4 and bus exception handling program 5. The coordination relationship of these five logic units in the overall process is shown in Figure 1. The software implementations of the four logic units of the startup program 2, the FPB associated program 3, the execution program 4, and the bus exception handling program 5 are all stored in the natively supported code memory of the CPU, such as in the on-chip Flash or ROM.

In the compiling and burning program 1, through the parameter configuration of the compiler, the startup program 2, the FPB associated program 3, the execution program 4, the bus exception handling program 5 and the system and the driver are positioned on the CPU on-chip physical memory associated on the Flash address space of the CPU, and locate other programs on the Flash address space associated with no physical memory in the CPU chip; compile and generate a binary image file of the target executable code; then, the software developer will start the program 2, FPB associated program 3. Burn the execution program 4, the bus exception handling program 5, the system and the driver program to the CPU physical memory at the specified address when compiling, and burn the other programs to the off-chip Flash. Among them, the system and driver refer to the boot program, task scheduling, timing function, system exception handling, interrupt management, hardware device driver and other programs whose execution effects will be obviously affected by the code execution time and the program segments that realize the functions of this patent ; The other programs refer to programs whose execution effects are not significantly affected by code execution time, generally including middle-level codes of pure software logic, application software, etc.

In the first stage after the device is powered on, the startup program 2 first initializes the basic operating environments such as the system and device drivers, initializes FPB components, and software global variables, and then the startup program extracts the first instruction code of the subsequent program. The Flash execution address is sent to the FPB associated program 3 for FPB associated processing.

The FPB associated program 3 can be called by the startup program 2 and the executive program 4; the FPB associated program 3 incoming address parameter is the Flash execution address of the first instruction code that needs to be associated and executed this time, and the The FPB association program 3 will sequentially execute two processes of "loading the executed code and performing FPB association" and "loading the code segment predicted to be executed". Among them, "the process of loading the executed code and performing FPB association on it" is a mandatory process, and "the process of loading the code segment that is predicted to be executed" can be selected according to the configuration of the CPU, that is, if the CPU has DMA function, Then, the FPB association program also executes "the process of loading the code segment that is predicted to be executed soon" after executing the "process of loading the executed code and performing FPB association on it".

The "process of loading the executed code and performing FPB association on it" checks whether the code at the corresponding address has been loaded into the RAM buffer after obtaining the Flash execution address of the code passed in by the caller, and if the code has not been loaded into the In the RAM buffer, the corresponding code is loaded into the RAM buffer from the off-chip Flash through the Flash driver. After the loading is completed, the process calculates the storage address of the code corresponding to the program instruction address in the RAM, and the FPB component has a total of n units are available, each unit is associated with m bytes of Flash address space, the size of the RAM buffer is defined as k bytes, then k bytes should be at least equal to n*m bytes, by setting FPB, the The RAM address of n*m bytes starting from the storage address is associated with the Flash execution address of the code;

The "process of loading a code segment that is predicted to be executed" opens up a RAM space equal to the RAM buffer size k bytes of the "process of loading the executed code and performing FPB association" as an auxiliary RAM buffer, Then the k-byte code loaded on the off-chip Flash following the code loaded in the "loading the executed code and carrying out the process of FPB association" is loaded into the auxiliary RAM buffer, and the loading process is realized by DMA; and The execution result of the "process of loading the code segment predicted to be executed" is used to accelerate the next "process of loading the executed code and performing FPB association on it".

The executive program 4 is called after the FPB associated program 3, the incoming address parameter of the executive program 4 is the same as the address parameter passed in by the FPB associated program 3, and the incoming address of the executive program 4 The parameters are sent to the PC register of the CPU, and then the CPU will automatically complete the subsequent code execution process;

The bus exception handler 5 will be triggered during the execution of the program 4. When the execution of the program 4 is executed, if the code executes to the Flash address that is not specified by the FPB this time and is not associated with the physical Flash address, it will cause a bus exception because the CPU core cannot extract the machine instruction code, and the bus exception handler 5 is associated with the bus exception vector at the software development stage. Therefore, when an exception occurs, the bus exception handler 5 5 is called to execute. When the bus exception handling program 5 is called for execution, by querying the abnormal state register of the CPU, it is known whether the exception is caused by CPU fetching instructions or caused by CPU data access, if the exception is caused by CPU fetching instructions, the exception address is used as Parameter calls described FPB association program 3 to carry out re-association processing, if exception is caused by CPU data access, then described bus exception handler 5 continues to check whether the instruction that causes exception is LDM multi-register load instruction, if so, then by described bus Abnormal handling program 5 replaces CPU to complete the function of LDM instruction, then returns next instruction code address to allow CPU to continue to execute, if not, then the data address to be accessed is used as parameter to call described FPB association program 3 to carry out re-association processing.

Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we have described are only illustrative, rather than used to limit the scope of the present invention. Equivalent modifications and changes made by skilled personnel in accordance with the spirit of the present invention shall fall within the protection scope of the claims of the present invention.

Claims (2)

1. A method for storing executable codes under the ARMv7m framework, characterized in that: In compiling and burning the program, through the parameter configuration of the compiler, the startup program, FPB related program, execution program, bus exception handling program, system and driver are located in the Flash address space associated with the physical memory on the CPU chip, and Locate other programs on the Flash address space that is not associated with physical memory in the CPU chip; compile and generate a binary image file of the target executable code; , Burn the system and the driver program to the CPU physical memory of the specified address when compiling, and burn the other programs to the off-chip Flash; In the first stage after the device is powered on and started, the startup program first initializes the basic operating environments of the system and device drivers, initializes FPB components, and software global variables, and then the startup program extracts the Flash memory of the first instruction code of the subsequent program. Execution address is sent into the FPB associated program to carry out FPB associated processing, and the FPB associated program can be called by the startup program and the execution program; The incoming address parameter of the FPB associated program is the Flash execution address of the first instruction code that needs to be associated and executed this time, and executes "the process of loading the executed code and performing FPB association to it"; After executing the address of the Flash, check whether the code corresponding to the address has been loaded into the RAM buffer, if the code has not been loaded into the RAM buffer, load the corresponding code from the off-chip Flash into the RAM buffer through the Flash driver, After the loading is completed, calculate the storage address of the code corresponding to the program instruction address in RAM. Suppose that the FPB component has n units available for use, and each unit is associated with m bytes of Flash address space. The size of the RAM buffer is defined as is k bytes, then k bytes should be at least equal to n*m bytes. By setting FPB, the RAM address starting from the storage address of n*m bytes is associated with the Flash execution address of the code; The execution program is called after the FPB associated program, the incoming address parameter of the execution program is the same as the address parameter passed in by the FPB associated program, and the incoming address parameter is sent into the CPU by the execution program PC register, and then the CPU will automatically complete the subsequent code execution process; When the execution process of the execution program causes a bus exception, the bus exception handler is called to execute, and by querying the exception status register of the CPU, it is known whether the exception is caused by CPU instruction fetching or CPU data access, if the exception is caused by the CPU Instruction fetching is caused, then the abnormal address is used as a parameter to call the FPB associated program to carry out re-association processing, if the exception is caused by CPU data access, then the bus exception handler continues to check whether the instruction causing the exception is an LDM multi-register load instruction, If so, the bus exception handler replaces the CPU to complete the function of the LDM instruction, then returns the next instruction code address to allow the CPU to continue executing, if not, the data address to be accessed is used as a parameter to call the FPB associated program to carry out re-association deal with. 2. the storage method of executable code under a kind of ARMv7m framework according to claim 1, it is characterized in that: if CPU possesses DMA function, then described FPB associated program is executing described " loading and executing code and performing After the FPB-associated process", the "process of loading the code segment predicted to be executed" is also executed. The RAM buffer size equal to k bytes in the process of performing FPB association" is used as an auxiliary RAM buffer, and then the off-chip Flash is loaded following the "process of loading the executed code and performing FPB association" The k-byte code after the code is loaded into the auxiliary RAM buffer, and the loading process is realized by DMA; and the execution result of the "loading the code segment that is predicted to be executed" is used to accelerate the next "loading is executed code and FPB-associate it".