CN104851809A - Thin-film transistor, producing method thereof, array substrate, and display device - Google Patents

Abstract

A method for manufacturing a thin film transistor, comprising: a deposition step of a crystallization precursor, the deposition step adopts a chemical vapor deposition process, and a carbon-containing gas and a silicon-containing gas are used as reaction sources in the chemical vapor deposition process; The step of forming an active layer, the step of forming a gate insulating layer and a gate, and the step of forming a source and a drain. The manufacturing method of the above thin film transistor can increase the forbidden band width of the active layer, thereby reducing the leakage current of the low temperature polysilicon thin film transistor. Moreover, it can also reduce the visible light absorption coefficient of the low-temperature polysilicon, and reduce the photoinduced leakage current generated by the backlight source. In addition, the manufacturing method of the above thin film transistor can be applied to the existing polysilicon thin film transistor production line without increasing the number of photomasks or changing production equipment, and the operation method is simple and convenient. The invention also provides a thin film transistor, an array substrate and a display device.

Description

Thin film transistor and manufacturing method thereof, array substrate and display device

technical field

The invention relates to the field of semiconductor devices, in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device.

Background technique

Thin film transistor liquid crystal display (TFT-LCD) is the most important type in the field of flat panel display, because it has many advantages, such as thin size, light weight, excellent picture quality, low power consumption, long life, digital, etc., and it is also the only Display technology that spans all sizes, and its application fields are very wide, covering almost the main electronic products in today's information society, such as TV, monitor, portable computer, mobile phone, PDA, GPS, vehicle display, instrumentation, public display and medical display etc.

In liquid crystal displays, thin film transistors are generally used as switching elements to control pixels, or as driving elements to drive pixels. Thin film transistors can generally be divided into two types: amorphous silicon (a-Si) and polycrystalline silicon (Poly-Si) according to the properties of silicon thin films. Compared with amorphous silicon thin film transistors, the carrier mobility of polycrystalline silicon thin film transistors is 2-3 times higher. An order of magnitude, which makes polysilicon thin film transistors have great advantages in high-resolution flat panels. However, the off-state current (ie, leakage current) of polysilicon thin film transistors is nearly an order of magnitude higher than that of amorphous silicon thin film transistors. If the off-state current is too large, it will affect the switching characteristics of the thin film transistor, which will lead to display defects such as uneven display, whitening, and crosstalk in TFT-LCD.

At present, most panel display manufacturers control the off-state current of polysilicon thin film transistors by changing the TFT structure, such as making the TFT a double gate structure, or making the TFT channel into an S shape, etc., by increasing the length of the TFT channel To increase the aspect ratio of the TFT, thereby reducing its off-state current. However, the negative impact of these methods is that the TFT area increases significantly and the aperture ratio of the display decreases. In high-resolution displays, as the resolution increases, the area of each pixel becomes smaller and smaller. In a limited pixel area, the method of reducing the off-state current of the polysilicon thin film transistor by increasing the channel length of the TFT The disadvantages are also becoming more and more obvious and difficult to maintain. How to solve this contradiction and avoid the reduction of the aperture ratio of the display while controlling the off-state current of the polysilicon thin film transistor has always been the direction pursued by the industry and the focus of research.

Contents of the invention

Based on this, the present invention provides a thin film transistor and its manufacturing method, as well as an array substrate and a display device, which can reduce the off-state current of the polysilicon thin film transistor while avoiding the reduction of the aperture ratio of the display, and this method can be applied to the existing polysilicon thin film The transistor production line does not need to increase the number of photomasks or change production equipment, and the operation method is simple and convenient.

A method for manufacturing a thin film transistor, comprising:

A deposition step of a crystallization precursor, the deposition step adopts a chemical vapor deposition process, and in the chemical vapor deposition process, a carbon-containing gas and a silicon-containing gas are used as reaction sources;

Crystallization step;

the step of forming an active layer;

a step of forming a gate insulating layer and a gate;

The step of forming source and drain.

In one embodiment, in the chemical vapor deposition process, the gas flow ratio of the carbon-containing gas to the silicon-containing gas is 1/10˜1.

In one embodiment, the silicon-containing gas is at least one of SiH ₄ , SiH ₂ Cl ₂ or SiH ₃ Cl, and the carbon-containing gas is CH ₄ , C ₂ H ₆ , CH ₃ OH, C ₂ At least one of H ₅ OH or CH ₃ COOH.

In one embodiment, the chemical deposition process is plasma-enhanced chemical vapor deposition, wherein the temperature used is 250-400°C, the pressure used is 100-400Pa, and the radio frequency power used is 10-80mW /cm ² .

In one of the embodiments, it specifically includes:

Deposit a gate metal layer on the substrate, and form a gate through a patterning process;

depositing a gate insulating layer on the gate;

Depositing a crystallization precursor on the gate insulating layer by using a plasma-enhanced chemical vapor deposition process, and using a carbon-containing gas and a silicon-containing gas as a reaction source in the plasma-enhanced chemical vapor deposition process;

performing an excimer laser annealing process on the crystallization precursor to form a crystallization layer;

performing a patterning process on the crystallized layer to form an active layer;

performing ion implantation on the active layer to achieve channel doping;

depositing a channel insulating layer on the active layer, and forming a channel protective layer through a patterning process;

Using the channel protection layer as a mask, performing ion implantation on the active layer to form a source region and a drain region;

depositing an intermediate protective layer on the active layer, and forming via holes on the intermediate protective layer;

A metal layer is deposited on the intermediate insulating layer, and a source electrode and a drain electrode are formed through a patterning process.

In one of the embodiments, it specifically includes:

forming a buffer layer on the substrate;

Depositing a crystallization precursor on the buffer layer by using a plasma-enhanced chemical vapor deposition process, and using a carbon-containing gas and a silicon-containing gas as a reaction source in the plasma-enhanced chemical vapor deposition process;

performing an excimer laser annealing process on the crystallization precursor to form a crystallization layer;

performing a patterning process on the crystallized layer to form an active layer;

performing ion implantation on the active layer to achieve channel doping;

depositing a gate insulating layer on the active layer;

depositing a gate metal layer on the gate insulating layer, and forming a gate through a patterning process;

Using the gate as a mask, performing ion implantation on the active layer to form a source region and a drain region;

Depositing a passivation layer on the gate, forming via holes in the gate insulating layer and the passivation layer;

Make source and drain.

In one embodiment, the thickness of the crystallization precursor is 40nm-60nm.

A thin film transistor, which is manufactured by any one of the above-mentioned manufacturing methods.

An array substrate, including a substrate, and the above-mentioned thin film transistors, gate lines, data lines and pixel electrodes arranged on the substrate.

A display device includes the above-mentioned array substrate.

The manufacturing method of the above-mentioned thin film transistor uses carbon-containing gas and silicon-containing gas as reaction sources at the same time during the deposition process of the crystallization precursor, and obtains an active layer doped with carbon elements after laser crystallization, and an undoped low-temperature Compared with polysilicon, carbon doping can form Si-C bonds with stronger bond energy in low-temperature polysilicon, increase the band gap of the active layer, and effectively reduce the leakage current of low-temperature polysilicon thin film transistors. Moreover, it can also reduce the visible light absorption coefficient of the low-temperature polysilicon, and reduce the photoinduced leakage current generated by the backlight source. In addition, the manufacturing method of the above thin film transistor can be applied to the existing polysilicon thin film transistor production line without increasing the number of photomasks or changing production equipment, and the operation method is simple and convenient.

Description of drawings

Fig. 1 is the schematic flow chart of the manufacturing method of an embodiment of the present invention;

2 is a schematic flow diagram of a manufacturing method according to another embodiment of the present invention;

3A-3G are structural schematic diagrams of each step in the manufacturing process of the thin film transistor shown in FIG. 2 .

detailed description

In order to further understand the features, technical means and specific objectives and functions achieved by the present invention, the present invention will be further described in detail below in conjunction with specific embodiments.

The invention provides a method for manufacturing a thin film transistor, comprising:

A deposition step of a crystallization precursor, the deposition step adopts a chemical vapor deposition process, and in the chemical vapor deposition process, a carbon-containing gas and a silicon-containing gas are used as reaction sources;

Crystallization step;

the step of forming an active layer;

a step of forming a gate insulating layer and a gate;

The step of forming source and drain.

Thin film transistors can be divided into bottom-gate structure and top-gate structure according to the positional relationship between gate, source and drain. This embodiment can be used to make a thin film transistor with a bottom gate structure, which specifically includes the following steps:

S110: depositing a gate metal layer on the substrate, and forming a gate through a patterning process.

On clean transparent substrates, such as glass, polyimide (PI) and polyethylene terephthalate (PET), etc., using sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (PECVD), low The gate metal layer is deposited by pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), electron cyclotron resonance microwave plasma chemical vapor deposition (ECR-CVD), and then, using a mask (mask) Expose, develop and etch to pattern the gate metal layer to form the gate.

For example, the material of the gate metal layer is metal or alloy such as molybdenum, aluminum, chromium, copper, aluminum-nickel alloy, molybdenum-tungsten alloy, or a combination of the above-mentioned materials. In this embodiment, the thickness of the gate metal layer is 100-800 nm. Of course, the thickness of the gate metal layer can also be selected according to specific process requirements.

S120: depositing a gate insulating layer on the gate.

For example, a gate insulating layer is formed on a substrate on which a gate is formed by using a chemical vapor deposition method. As another example, the deposition temperature is generally controlled below 500°C. As another example, the thickness of the gate insulating layer may be 30-300 nm, and an appropriate thickness may also be selected according to specific process requirements. In another example, the gate insulating layer is a single layer of silicon oxide, silicon nitride, or a stack of the two.

S130: Deposit crystallization precursors on the gate insulating layer by plasma-enhanced chemical vapor deposition, and use carbon-containing gas and silicon-containing gas as reaction sources in the plasma-enhanced chemical vapor deposition process.

The technical principle of plasma-enhanced chemical vapor deposition (PECVD) is to use low-temperature plasma as an energy source. The sample is placed on the electrode of the PECVD equipment, and the heating element is used to heat the sample to a predetermined temperature, and then an appropriate amount of Reactive gas, apply a high-frequency AC voltage on the two electrode plates, the gas is ionized under the high-frequency electric field, and then undergo a series of chemical reactions to form a solid film on the surface of the sample.

Generally, when using PECVD technology to deposit thin film materials, there are mainly the following three basic processes: (1) After the electrons are accelerated by an external electric field in the glow discharge plasma, they undergo a primary reaction with the reactive gas, causing the reactive gas to decompose. Form a mixture of ions and active groups; (2) The positive ions are accelerated by the ion layer acceleration electric field and collide with the upper electrode, and there will be a small ion layer electric field near the lower electrode, so the substrate is also bombarded by ions to a certain extent. Various active groups are diffused and transported to the film growth surface and tube wall, and secondary reactions between reactants occur at the same time; (3) Various primary reactions and secondary reactants that reach the substrate surface are adsorbed and bonded to the surface React with each other to form a thin film, accompanied by the re-emission of gas phase molecules.

In this embodiment, carbon-containing gas and silicon-containing gas are used as reaction sources, hydrogen is used as carrier gas, and the gas flow ratio of carbon-containing gas and silicon-containing gas is controlled to be 1/10-1, that is, 10% to 100%. The plasma-enhanced chemical vapor deposition is performed when the pressure of the reaction chamber is controlled to be 100-400 Pa, the temperature is 250-400° C., and the radio frequency power is 10-80 mW/cm ² . Wherein, the silicon-containing gas may be SiH ₄ , SiH ₂ Cl ₂ or SiH ₃ Cl, and the carbon-containing gas may be CH ₄ , C ₂ H ₆ , CH ₃ OH, C ₂ H ₅ OH or CH ₃ COOH. For example, the volume ratio of the reaction source to the carrier gas is 1-10:1-1000; for example, 1-10:1-100; another example is to use carbon-containing gas and silicon-containing gas as the reaction source and argon as the carrier gas .

In this embodiment, the thickness of the crystallization precursor is 40nm˜60nm. Of course, an appropriate thickness can also be selected according to specific process requirements. For example, the thickness of the crystallization precursor is 42nm-55nm, and for another example, the thickness of the crystallization precursor is 45nm, 48nm, 50nm, 51nm, 52nm or 54nm.

S140: performing a laser annealing process on the crystallization precursor to form a crystallization layer.

For example, laser annealing may use excimer lasers such as xenon chloride (XeCl), krypton fluoride (KrF), argon fluoride (ArF), etc., for example, with a wavelength of 308 nm, for excimer laser annealing. The laser beam becomes a linear light source after passing through the optical system.

For example, the pulse repetition rate (pulse repetition ratio) of excimer laser annealing is 300Hz-800Hz, another example, the pulse repetition rate of excimer laser annealing is 400Hz-600Hz; another example, the scan pitch (scan pitch) is 15μm-30μm; As another example, the laser energy density is 250-600mJ/cm ² , as another example, the laser energy density is 350-500mJ/cm ² ; as another example, the scanning rate is preferably 0.5mm/s-50mm/s, and as another example, the scanning rate is 0.5mm/s～50mm/s 1mm/s～30mm/s, another example, the scan rate is 2mm/s～10mm/s.

Preferably, before performing the laser annealing process, the crystallization precursor needs to be dehydrogenated, so that the hydrogen content is reduced to below 2%, so as to prevent hydrogen explosion. For example, heat treatment is used to remove hydrogen from the crystallization precursor.

S150: performing a patterning process on the crystallized layer to form an active layer;

For example, specifically, it includes the following steps:

S151: Forming a mask by using a photolithography process, forming a pattern by using a dry etching method, and forming an active layer including a source region, a drain region, and a channel region.

S152: performing ion implantation on the active layer to achieve channel doping.

In this embodiment, the purpose of doping is to adjust the threshold voltage of the thin film transistor. For example, when the threshold voltage of the thin film transistor needs to move in the positive direction, the active layer is doped with boron; when the threshold voltage of the thin film transistor needs to be moved in the negative direction, the active layer is doped with phosphorus or Doping with arsenic element; and if the threshold voltage does not need to be adjusted according to the process, it is not necessary to perform ion implantation on the active layer to achieve channel doping.

The ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method, or a solid-state diffusion implantation method. For example, in this embodiment, an ion implantation method with a mass analyzer is used.

According to the requirements of the threshold voltage of the thin film transistor, the injection medium is a gas containing boron element or phosphorus element. For example, when boron-containing elements are required to be implanted, for example, the mixed gas of B ₂ H ₆ and H ₂ is used as the injection medium, and the ratio of B ₂ H ₆ to H ₂ is 1% to 30%, and the implantation energy ranges from 2 to 30%. 50KeV, more preferably the energy range is 4-10KeV, the implantation dose range is 0-5×10 ¹³ atoms/cm ³ , preferably, the implantation dose range is 0-9×10 ¹² atoms/cm ³ . As another example, phosphorus-containing elements are used, such as a mixed gas of PH ₃ and H ₂ as the injection medium, for example, the ratio of PH ₃ and H ₂ is 1% to 30%; the range of injection energy is 5 to 50KeV, and the more preferred energy The range is 7-20KeV; the implantation dose is in the range of 0-5×10 ¹³ atoms/cm ³ , preferably, the implantation dose is in the range of 0-9×10 ¹² atoms/cm ³ .

S160: depositing a channel insulating layer on the active layer, and forming a channel protective layer through a patterning process.

For example, a channel insulating layer is deposited on the active layer using a chemical vapor deposition method. As another example, the deposition temperature is generally controlled below 500°C. As another example, the thickness of the channel insulating layer may be 20-300 nm, and an appropriate thickness may also be selected according to specific process requirements. In another example, the channel insulating layer is made of a single layer of silicon oxide, silicon nitride, or a stack of the two.

For example, a photoresist is coated on the channel insulating layer and exposed through a mask. As another example, using a positive photoresist, the exposure light source passes through the substrate to expose the photoresist from the direction of the substrate, the exposure light source is blocked at the place where the grid is located, and the photoresist behind is not exposed, and a pattern is formed after development.

Using the remaining photoresist as a template, the channel protection layer is etched. The protective layer not covered by photoresist is etched away. The photoresist is then removed by a stripping process.

S170: Using the channel protective layer as a mask, perform ion implantation on the active layer to form a source region and a drain region.

The ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method, or a solid-state diffusion implantation method. For example, in this embodiment, an ion implantation method with a mass analyzer is used.

According to design requirements, the injection medium is a gas containing boron and/or phosphorus to form a P-type or N-type thin film transistor. For example, using boron-containing elements, such as B ₂ H ₆ /H ₂ mixed gas as the injection medium, for example, the ratio of B ₂ H ₆ to H ₂ is 1% to 30%; the range of implantation energy is 5 to 50KeV, more The preferred energy range is 7-25KeV; the implantation dose ranges from 1×10 ¹³ to 1×10 ¹⁷ atoms/cm ³ , preferably, the implantation dose ranges from 5×10 ¹⁴ to 5×10 ¹⁵ atoms/cm ³ ; , using phosphorus-containing elements, such as PH ₃ /H ₂ mixed gas as the injection medium.

S180: Depositing an intermediate insulating layer on the channel protection layer, and forming a via hole in the intermediate insulating layer.

For example, a chemical vapor deposition method is used to deposit an intermediate insulating layer on the channel protection layer. As another example, the deposition temperature is generally controlled below 500°C. In another example, the thickness of the intermediate insulating layer may be 100-1000 nm, and an appropriate thickness may also be selected according to specific process requirements. For another example, the intermediate insulating layer is a single layer of silicon oxide, silicon nitride, or a stack of the two.

For example, a dry etching method is used to form a mask with a photolithography process, and via holes are formed on the intermediate insulating layer to expose the source region and the drain region. Among them, in the dry etching process, gases containing fluorine elements or chlorine elements, such as SF ₆ , CF ₄ , CHF ₃ , CCl ₂ F ₂ , or a mixture of the aforementioned gases and O ₂ can be used as the etching medium. Etching is carried out by reactive ion etching, plasma etching or inductively coupled plasma etching.

S190: Deposit a metal layer on the intermediate protection layer, and form a source electrode and a drain electrode through a patterning process.

For example, S190 specifically includes the following steps:

S191: Depositing a source-drain metal thin film on the intermediate protective layer;

S192: Using wet etching or dry etching, a photolithography process is used to form a mask, and the source and drain metal thin films are patterned to form a source and a drain.

So far, the preparation of the thin film transistors including the gate, source and drain of the array substrate has been completed, and the gate lines, data lines and pixel electrodes on the array substrate can be obtained according to conventional processes. According to the structural requirements of the array substrate, a display panel can be finally formed through conventional processes, and further a display device can be formed.

Another embodiment of the present invention also provides a method for manufacturing a thin film transistor with a top-gate structure, the specific steps of which are as follows:

S210: forming a buffer layer on the substrate.

Referring to FIG. 3A , a buffer layer 200 is formed on a clean substrate 100 , which may be a glass substrate or a flexible substrate. The formed buffer layer 200 can improve the degree of adhesion between the crystallization precursor to be formed and the substrate. At the same time, it can also prevent metal ions in the substrate from diffusing to the active layer, reduce impurity defects, and reduce leakage current generation.

Specifically, a buffer layer with a certain thickness is deposited on the glass substrate by plasma chemical vapor deposition (PECVD). The deposition material can be a single layer of silicon oxide (SiO _x ) film layer or silicon nitride (SiN _x ) film layer, or a stack of silicon oxide (SiO _x ) and silicon nitride (SiN _x ).

Wherein, the reaction gas for forming the SiN _x film layer can be a mixed gas of SiH ₄ , NH ₃ , N ₂ , or a mixed gas of SiH ₂ Cl ₂ , NH ₃ , N ₂ ; the reaction gas for forming a SiO _x film layer can be A mixed gas of SiH ₄ and N2O, or a mixed gas of SiH ₄ and ethyl silicate (TEOS).

S220: Deposit crystallization precursors on the buffer layer by using a plasma-enhanced chemical vapor deposition process, and use carbon-containing gas and silicon-containing gas as reaction sources in the plasma-enhanced chemical vapor deposition process.

In this embodiment, carbon-containing gas and silicon-containing gas are used as reaction sources, hydrogen is used as carrier gas, the gas flow ratio of carbon-containing gas and silicon-containing gas is controlled to be 1/10-1, and the pressure of the reaction chamber is controlled to be 100 ~ 400Pa, the temperature is 250 ~ 400 ℃, and the radio frequency power is 10 ~ 80mW/cm ² for plasma enhanced chemical vapor deposition. Wherein, the silicon-containing gas may be SiH ₄ , SiH ₂ Cl ₂ or SiH ₃ Cl, and the carbon-containing gas may be CH ₄ , C ₂ H ₆ , CH ₃ OH, C ₂ H ₅ OH or CH ₃ COOH. For example, the volume ratio of the reaction source to the carrier gas is 1-10:1-1000; for example, 1-10:1-100; another example is to use carbon-containing gas and silicon-containing gas as the reaction source and argon as the carrier gas .

In this embodiment, the thickness of the crystallization precursor is 40nm˜60nm. Of course, an appropriate thickness can also be selected according to specific process requirements. For example, the thickness of the crystallization precursor is 42nm-55nm, and for another example, the thickness of the crystallization precursor is 45nm, 48nm, 50nm, 51nm, 52nm or 54nm.

S230: performing a laser annealing process on the crystallization precursor to form a crystallization layer.

For example, laser annealing may use excimer lasers such as xenon chloride (XeCl), krypton fluoride (KrF), argon fluoride (ArF), etc., for example, with a wavelength of 308 nm, for excimer laser annealing. The laser beam becomes a linear light source after passing through the optical system.

For example, the pulse repetition rate (pulse repetition ratio) of excimer laser annealing is 300Hz-800Hz, another example, the pulse repetition rate of excimer laser annealing is 400Hz-600Hz; another example, the scan pitch (scan pitch) is 15μm-30μm; As another example, the laser energy density is 250-600mJ/cm ² , as another example, the laser energy density is 350-500mJ/cm ² ; as another example, the scanning rate is preferably 0.5mm/s-50mm/s, and as another example, the scanning rate is 0.5mm/s～50mm/s 1mm/s～30mm/s, another example, the scan rate is 2mm/s～10mm/s.

Preferably, before performing the laser annealing process, the crystallization precursor needs to be dehydrogenated, so that the hydrogen content is reduced to below 2%, so as to prevent hydrogen explosion. For example, hydrogen is removed from the crystallization precursor using a thermal annealing treatment.

S240: Perform a patterning process on the crystallized layer to form an active layer.

For example, specifically, it includes the following steps:

S241: Form a mask by using a photolithography process, and form a pattern by dry etching to form an active layer 300 including a source region, a drain region and a channel region. Please refer to FIG. 3B for a cross-section after completion.

S242: performing ion implantation on the active layer to achieve channel doping.

The purpose of doping the channel is to adjust the threshold voltage of the device. For example, when the threshold voltage of the thin film transistor needs to move in the positive direction, the active layer is doped with boron; when the threshold voltage of the thin film transistor needs to be moved in the negative direction, the active layer is doped with phosphorus or Doping with arsenic element; and if the threshold voltage does not need to be adjusted according to the process, it is not necessary to perform ion implantation on the active layer to achieve channel doping.

S250 : Deposit a gate insulating layer 400 on the active layer 300 , and refer to FIG. 3C for a cross-section after completion.

For example, a gate insulating layer is formed on the substrate on which the active layer is formed using a chemical vapor deposition method. As another example, the deposition temperature is generally controlled below 500°C. As another example, the thickness of the gate insulating layer may be 80-200 nm, and an appropriate thickness may also be selected according to specific process requirements. In another example, the gate insulating layer is a single layer of silicon oxide, silicon nitride, or a stack of the two.

S260: Deposit a gate metal layer on the gate insulating layer 400, and form a gate 500 through a patterning process. Please refer to FIG. 3D for a cross-section after completion.

For example, sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), electron cyclotron resonance microwave plasma chemical vapor deposition (ECR- CVD) and other methods to deposit a gate metal layer, and then use a mask to perform exposure, development and etching to pattern the gate metal layer to form a gate.

For example, the material of the gate metal layer is metal or alloy such as molybdenum, aluminum, chromium, copper, aluminum-nickel alloy, molybdenum-tungsten alloy, or a combination of the above-mentioned materials. In this embodiment, the thickness of the gate metal layer is 100-800 nm. Of course, the thickness of the gate metal layer can also be selected according to specific process requirements.

S270 : Using the gate 500 as a mask, perform ion implantation on the active layer 300 to form the source region 310 and the drain region 320 , please refer to FIG. 3E for the completed cross-section.

For example, in this embodiment, an ion implantation method with a mass analyzer is used. For another example, according to design requirements, the implant medium is a gas containing boron and/or phosphorus to form a P-type or N-type thin film transistor. For example, using boron-containing elements, such as B ₂ H ₆ /H ₂ mixed gas as the injection medium, for example, the ratio of B ₂ H ₆ to H ₂ is 1% to 30%; the range of implantation energy is 5 to 50KeV, more The preferred energy range is 20-30KeV; the implantation dose ranges from 1×10 ¹³ to 1×10 ¹⁷ atoms/cm ³ , preferably, the implantation dose ranges from 5×10 ¹⁴ to 5×10 ¹⁵ atoms/cm ³ ; , using phosphorus-containing elements, such as PH ₃ /H ₂ mixed gas as the injection medium. For example, the mixed gas of PH ₃ /H ₂ is used as the injection medium, for example, the ratio of PH ₃ to H ₂ is 1% to 30%; the injection energy range is 20 to 110KeV, and the more preferred energy range is 50 to 70KeV; the injection dose The range is 1×10 ¹³ to 1×10 ¹⁷ atoms/cm ³ , preferably, the injection dose is in the range of 5×10 ¹⁴ to 5×10 ¹⁵ atoms/cm ³ .

S280: Deposit a passivation layer 600 on the gate 500, and form a via hole 610 in the gate insulating layer 400 and the passivation layer 600. Please refer to FIG. 3F for a cross-section after completion.

Specifically, a passivation layer with a thickness of 200 nm to 800 nm can be deposited by a chemical vapor deposition process, for example, the passivation layer is an oxide, nitride or oxynitride compound, and for another example, the passivation layer is a single-layer structure or a multi-layer structure , as another example, the gas for forming the passivation layer is SiH ₄ , NH ₃ , N ₂ or SiH ₄ , N ₂ O.

For example, a dry etching method is used to form a mask by a photolithography process, and via holes are formed on the passivation layer and the gate insulating layer to expose the source region and the drain region. Among them, in the dry etching process, gases containing fluorine elements or chlorine elements, such as SF ₆ , CF ₄ , CHF ₃ , CCl ₂ F ₂ , or a mixture of the aforementioned gases and O ₂ can be used as the etching medium. Etching is carried out by reactive ion etching, plasma etching or inductively coupled plasma etching.

S290 : Fabricate the source electrode 710 and the drain electrode 720 , please refer to FIG. 3G for the completed cross section.

Specifically, the metal layer is formed on the passivation layer by sputtering, thermal evaporation or plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. Above the metal layer, a photoresist mask is formed with photoresist by photolithography process, and patterns including source and drain are formed by wet etching or dry etching. Referring to FIG. 3G , the source 710 penetrates through the via hole 610 and is electrically connected to the source region 310 , and the drain 720 penetrates through the via hole 610 and is electrically connected to the drain region 320 .

So far, through this method, the preparation of the thin film transistors including the gate, source and drain of the array substrate has been completed, and the gate lines, data lines and pixel electrodes on the array substrate can be obtained according to conventional processes. According to the structural requirements of the array substrate, a display panel can be finally formed through conventional processes, and further a display device can be formed.

As another example, a thin film transistor is manufactured by using the manufacturing method described in any of the above embodiments.

Another example is an array substrate, which includes a substrate, and thin film transistors, gate lines, data lines, and pixel electrodes disposed on the substrate, wherein the thin film transistors are prepared by the manufacturing method described in any of the above-mentioned embodiments .

In this embodiment, a display device is provided, and the display device includes the array substrate in any one of the above embodiments. For example, the display device is a product or component with a display function; for example, the display device is a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame or navigator.

The manufacturing method of the above-mentioned thin film transistor uses carbon-containing gas and silicon-containing gas as reaction sources at the same time during the deposition process of the crystallization precursor, and obtains an active layer doped with carbon elements after excimer laser crystallization, which is different from that without doping. Compared with low-temperature polysilicon, carbon doping can form Si-C bonds with stronger bond energy in low-temperature polysilicon, and increase the band gap of the active layer.

The leakage current in low-temperature polysilicon mainly includes: reverse saturation current, band-band tunneling current and defect-assisted band-band tunneling current.

For the reverse saturation current, according to the reverse saturation current formula:

$\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; A</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; \&kappa;\; T</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; A</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; \&kappa;\; T</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; wxya</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; \&kappa;\; T</span>}}<span\; class="notranslate">\; )</span>$

Among them: j is the reverse saturation current, A and κ are the coefficients, T is the temperature, E _g is the band gap width of the material, L _n and L _p are the diffusion lengths of electron holes as minority carriers, τ _n and τ _p are respectively is the minority carrier lifetime when electrons and holes are minority carriers, N _A and N _D are the doping concentrations of the P region and N region respectively, q is the charge, and V is the reverse bias voltage.

It can be seen that the reaction saturation current j decreases exponentially with the increase of the material gap _Eg .

For band-band tunneling current and defect-assisted band-band tunneling current, according to the Kane band-band tunneling probability formula:

Among them: G _BTBT is the band tunneling probability, m ^* is the electron effective mass, E is the transverse electric field strength, is the reduced Planck constant.

It can be seen that the probability of band-band tunneling _{G BTBT} decreases with the increase of the material gap Eg, so the band-band tunneling current and defect-assisted band-band tunneling current will also increase with the increase of the material gap _Eg increase and decrease.

Therefore, carbon doping increases the forbidden band width of the active layer, thereby effectively reducing the leakage current of the low temperature polysilicon thin film transistor. Moreover, increasing the band gap of the active layer can also reduce its visible light absorption coefficient and reduce the photo-induced leakage current generated by the backlight source.

In addition, the manufacturing method of the above thin film transistor can be applied to the existing polysilicon thin film transistor production line without increasing the number of photomasks or changing the production equipment, and the operation method is simple and convenient.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. A method for manufacturing a thin film transistor, comprising: A deposition step of a crystallization precursor, the deposition step adopts a chemical vapor deposition process, and in the chemical vapor deposition process, a carbon-containing gas and a silicon-containing gas are used as reaction sources; crystallization step; the step of forming an active layer; a step of forming a gate insulating layer and a gate; The step of forming source and drain. 2 . The manufacturing method according to claim 1 , wherein, in the chemical vapor deposition process, the gas flow ratio of the carbon-containing gas to the silicon-containing gas is 1/10˜1. 3. The production method according to claim 2, wherein the silicon-containing gas is at least one of SiH ₄ , SiH ₂ Cl ₂ or SiH ₃ Cl, and the carbon-containing gas is CH ₄ , C ₂ At least one of H ₆ , CH ₃ OH, C ₂ H ₅ OH or CH ₃ COOH. 4. The manufacturing method according to claim 2, wherein the chemical deposition process is plasma-enhanced chemical vapor deposition, wherein the temperature used is 250-400°C, the pressure used is 100-400Pa, The radio frequency power used is 10-80mW/cm ² . 5. The preparation method according to claim 1, characterized in that, specifically comprising: Deposit a gate metal layer on the substrate, and form a gate through a patterning process; depositing a gate insulating layer on the gate; Depositing a crystallization precursor on the gate insulating layer by using a plasma-enhanced chemical vapor deposition process, and using a carbon-containing gas and a silicon-containing gas as a reaction source in the plasma-enhanced chemical vapor deposition process; performing a laser annealing process on the crystallization precursor to form a crystallization layer; performing a patterning process on the crystallized layer to form an active layer; Performing ion implantation on the layer to achieve channel doping; depositing a channel insulating layer on the active layer, and forming a channel protective layer through a patterning process; Using the channel protection layer as a mask, performing ion implantation on the active layer to form a source region and a drain region; depositing an intermediate protective layer on the active layer, and forming via holes on the intermediate protective layer; A metal layer is deposited on the intermediate protection layer, and a source electrode and a drain electrode are formed through a patterning process. 6. The preparation method according to claim 1, characterized in that, specifically comprising: forming a buffer layer on the substrate; Depositing a crystallization precursor on the buffer layer by using a plasma-enhanced chemical vapor deposition process, and using a carbon-containing gas and a silicon-containing gas as a reaction source in the plasma-enhanced chemical vapor deposition process; performing an excimer laser annealing process on the crystallization precursor to form a crystallization layer; performing a patterning process on the crystallized layer to form an active layer; Performing ion implantation on the layer to achieve channel doping; depositing a gate insulating layer on the active layer; depositing a gate metal layer on the gate insulating layer, and forming a gate through a patterning process; Using the gate as a mask, performing ion implantation on the active layer to form a source region and a drain region; depositing a passivation layer on the gate, and forming via holes in the gate insulating layer and the passivation layer; Make source and drain. 7 . The manufacturing method according to claim 1 , wherein the thickness of the crystallization precursor is 40 nm˜60 nm. 8. A thin film transistor, characterized in that, the thin film transistor is manufactured by the manufacturing method according to any one of claims 1 to 7. 9 . An array substrate, characterized by comprising a substrate, and the thin film transistor according to claim 8 , gate lines, data lines and pixel electrodes disposed on the substrate. 10. A display device, comprising the array substrate according to claim 9.