CN104835827A - Display panel - Google Patents

Abstract

The invention discloses a display panel, wherein a thin film transistor substrate of the display panel comprises a bottom plate, a grid layer, a grid dielectric layer, a semiconductor layer, a first electrode layer, a first passivation layer, a second passivation layer, a through hole and a second electrode layer. The gate layer is located on the substrate. The gate dielectric layer is located on the gate layer. The semiconductor layer is located on the gate dielectric layer. The first electrode layer is located on the semiconductor layer. The first passivation layer is located on the first electrode layer. The second passivation layer is on the first passivation layer. The through hole penetrates through the first passivation layer and the second passivation layer to expose a part of the first electrode layer. The second electrode layer is electrically connected to the first electrode layer through the through hole. The first passivation layer has a first inclination angle at the side edge of the through hole, the second passivation layer has a second inclination angle at the side edge of the through hole, and the angle difference between the first inclination angle and the second inclination angle is smaller than 30 degrees.

Description

display panel

technical field

The present invention relates to a display panel, and in particular to a display panel with a thin film transistor substrate.

Background technique

In the manufacturing process of the display panel, if the conductive layers on the upper and lower sides of the insulating layer are to be conducted, a via or contact hole will be designed so that the conductive layers on the upper and lower sides can be electrically connected. For example, the method of electrically connecting the pixel electrode and the drain of the thin film transistor in the pixel structure is to perform a patterning process before forming the pixel electrode to form a via hole in the insulating layer to expose the underlying drain, and then After the pixel electrode is plated, the pixel electrode and the drain can be electrically connected through the through hole.

However, with the development of high-resolution display panels, their structures and manufacturing processes are becoming more complex, and there may be more than one insulating layer between different conductive layers. Due to the different film-forming conditions of different insulating layers, it is easy to form chamfers when etching to form through holes. Such chamfering tends to cause incomplete filling of the through hole, or disconnection occurs when the conductive layer is plated, which affects the quality of the display panel.

Contents of the invention

The purpose of the present invention is to provide a display panel with a specific design of the passivation layer, which can make the junction of the passivation layer on the side wall of the through hole smooth and avoid the disconnection of the upper electrode layer.

According to a first aspect of the present invention, a display panel is provided. The display panel includes a TFT substrate, an opposite substrate and a display layer between them. The TFT substrate includes a bottom plate, a gate layer, a gate dielectric layer, a semiconductor layer, a first electrode layer, a first passivation layer, a second passivation layer and a second electrode layer. The gate layer is on the bottom plate. A gate dielectric layer is located on the gate layer. The semiconductor layer is on the gate dielectric layer. The first electrode layer is located on the semiconductor layer. The first passivation layer is located on the first electrode layer. The second passivation layer is located on the first passivation layer, and has a through hole penetrating through the first passivation layer to expose part of the first electrode layer. The second electrode layer is located on the second passivation layer and electrically connected to the first electrode layer through the through hole. Wherein, the first passivation layer has a first inclination angle on the side of the through hole, the second passivation layer has a second inclination angle on the side of the through hole, and the angle difference between the first inclination angle and the second inclination angle is less than 30 degrees.

According to a second aspect of the present invention, a display panel is provided. The display panel includes a TFT substrate, an opposite substrate and a display layer between them. The TFT substrate includes a bottom plate, a gate layer, a gate dielectric layer, a semiconductor layer, a first electrode layer, a first passivation layer, a second passivation layer and a second electrode layer. The gate layer is on the bottom plate. A gate dielectric layer is located on the gate layer. The semiconductor layer is on the gate dielectric layer. The first electrode layer is located on the semiconductor layer. The first passivation layer is located on the first electrode layer. The second passivation layer is located on the first passivation layer and has a through hole penetrating through the first passivation layer to expose part of the first electrode layer. The second electrode layer is located on the second passivation layer and electrically connected to the first electrode layer through the through hole. Wherein, the second passivation layer is a multi-layer structure composed of multiple passivation films, and the second passivation layer has a second inclination angle between 10-80 degrees at the side of the through hole.

Description of drawings

FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.

FIG. 2A is a schematic diagram of a thin film transistor substrate according to an embodiment of the present invention.

FIG. 2B is an enlarged schematic diagram of area A in FIG. 2A .

FIG. 3 is a schematic diagram of a thin film transistor substrate according to another embodiment of the present invention.

4A-4D are schematic diagrams illustrating the manufacturing method of the via hole in FIG. 2A and FIG. 3 .

Symbol Description

1: display device

10, 11, 12: thin film transistor substrate

100: Bottom plate

110: gate layer

120: gate dielectric layer

130: semiconductor layer

135: etch stop layer

140: first electrode layer

141: Part One

142: Part II

150: first passivation layer

151: First Edge

160: organic layer

161: opening

170: Second passivation layer

171: first passivation film

172: Second passivation film

173: The third passivation film

174: Second Edge

180: Second electrode layer

190: Through hole

191: Through hole side

200: common electrode layer

2: Display panel

20: display layer

30: facing substrate

40: Backlight module

θ1: the first inclination angle

θ2: second inclination angle

d: distance

Detailed ways

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals are used in the drawings to designate the same or similar parts. It should be noted that the drawings have been simplified to clearly illustrate the content of the embodiments, and the size ratios in the drawings are not drawn to the same scale as the actual product, so they are not used to limit the protection scope of the present invention.

Please refer to FIG. 1 , which illustrates a display device according to an embodiment of the present invention. The display device 1 includes a display panel 2 and a backlight module 40 . When the display panel 2 is a liquid crystal display panel, it is composed of a thin film transistor substrate 10 , a display layer 20 and an opposite substrate 30 , and the display layer is a liquid crystal layer. The display layer 20 is located between the TFT substrate 10 and the opposite substrate 30 , and can be driven by a voltage to change its light transmittance. The opposite substrate 30 is designed relative to the TFT substrate 10 , for example, a color filter substrate, enabling the display panel 2 to display colors. It should be noted that when the display panel 2 is an organic light emitting diode panel, the backlight module 40 may not be provided, and the display layer 20 is an organic light emitting layer.

The thin film transistor substrate 10 is the main component of the display panel 2 and is divided into a plurality of pixel areas. Each pixel area has a corresponding thin film transistor, which can adjust the light transmittance of the display layer in this area. TFT substrates can be divided into various types according to the design of the pixel structure. The following uses FIG. 2A and FIG. 2B as examples.

Please refer to FIG. 2A , which illustrates a thin film transistor substrate according to an embodiment of the present invention. The TFT substrate 11 of FIG. 2A is a back channel etch (back channel etch, BCE) structure, including a base plate 100, a gate layer 110, a gate dielectric layer 120, a semiconductor layer 130, a first electrode layer 140, a first passivation layer 150 (passivation layer), the second passivation layer 170, the second electrode layer 180 and the through hole 190.

As shown in FIG. 2A , the gate layer 110 is located on the base plate 100 , the gate dielectric layer 120 is located on the gate layer 110 , and the semiconductor layer 130 is located on the gate dielectric layer 120 . That is, the gate dielectric layer 120 separates the gate layer 110 from the semiconductor layer 130 . In this example, the gate layer is located under the semiconductor layer 130 as the active layer, so it is called a bottom gate structure. The first electrode layer 140 is located on the semiconductor layer 130 and electrically connected to the semiconductor layer 130 to form a thin film transistor, and the semiconductor layer 130 is used as an active layer of the thin film transistor. In detail, the first electrode layer 140 is patterned into a first part 141 and a second part 142 that are separated, the first part 141 is electrically connected to the semiconductor layer 130 to form a source contact; the second part 142 is electrically connected to the semiconductor layer 130, Form the drain contact.

As shown in FIG. 2A , the first passivation layer 150 is formed on the first electrode layer 140 , the organic layer 160 is formed on the first passivation layer 150 , and the second passivation layer 170 is formed on the organic layer 160 . The common electrode layer 200 is formed between the second passivation layer 170 and the organic layer 160 . The materials of the first passivation layer 150 and the second passivation layer 170 are related to the material of the semiconductor layer 130. For example, when the semiconductor layer 130 is made of indium gallium zinc oxide (IGZO), the first passivation layer 150 can be selected from silicon oxide ( SiO _X ), and silicon nitride (SiN _X ) can be used for the second passivation layer. The passivation layers 150 and 170 have properties such as water and gas resistance and insulation, and can protect other structures on the TFT substrate. The material of the organic layer 160 is, for example, acrylic or PFA resin (Perfluoroalkoxy), which is used to increase the distance between the pixel electrode (second electrode layer 180) and the signal line (not shown), and is applied to a high-resolution thin film transistor substrate. It can significantly reduce the coupling interference of signals between the two. In one embodiment, the thicknesses of the first passivation layer 150 and the second passivation layer 170 are about And the thickness of the organic layer 160 is about It should be noted that, in other embodiments, the organic layer may not be disposed in the thin film transistor substrate, or may be replaced by other elements, which is not limited.

As shown in FIG. 2A, the via hole 190 has a via hole side 191, and penetrates through the first passivation layer 150, the organic layer 160, and the second passivation layer 170, so as to expose the second portion 142 (drain) of the first electrode layer 140. extreme contact). The second electrode layer 180 is, for example, a pixel electrode, located on the second passivation layer 170 and electrically connected to the first electrode layer 140 through the through hole 190 . It should be noted that although the first passivation layer 150 and the second passivation layer 170 above the thin film transistor are separated by the organic layer 160, the second passivation layer 170 directly covers the first passivation layer 191 at the side 191 of the via hole. over the passivation layer 150 (region A). It should be noted that since the first passivation layer 150 and the second passivation layer 170 have different compositions, there will be different etching rates when etching the through hole 190, so the first passivation layer 150 and the second passivation layer 150 at the side 191 of the through hole The second passivation layer 170 does not necessarily have to be in a straight line, for example, it may be in a stepped shape, as shown in FIG. 2A .

Please refer to FIG. 2B , which shows an enlarged view of the region A (the sidewall of the through hole 190 ) in FIG. 2A . For the convenience of illustration, some components are omitted in this figure. As shown, the first passivation layer 150 has a first taper angle θ1 (taper angle) at the via side 191 ( FIG. 2A ), and the second passivation layer 170 has a second taper angle θ2 at the via side 191 . Since the first passivation layer 150 and the second passivation layer have different compositions, the etching rate will be different when forming the through hole, so the values of the first inclination angle θ1 and the second inclination angle θ2 are different, and when the difference is too large, it will be The chamfer may be generated, and the second electrode layer 180 formed later may be disconnected. In this embodiment, the second passivation layer 170 is designed as a three-layer passivation film structure, which are the first passivation film 171, the second passivation film 172 and the third passivation film 173 in sequence, and are adjusted under the same etching conditions. Lower the etching rate so that the first passivation film 171 < the second passivation film 172 < the third passivation film 173 , that is, the passivation film closer to the first passivation layer 150 has a slower etching rate. In this way, the size of the second inclination angle θ2 can be significantly controlled. In one embodiment, the difference between the first inclination angle θ1 and the second inclination angle θ2 is less than 30 degrees, while in other embodiments the difference may be less than 3 degrees. In another embodiment, the second inclination angle is between 10-80 degrees, or between 45-60 degrees. By adjusting the angles of the first passivation layer 150 and the second passivation layer 170 at the sides 191 of the through holes to be close together, it is possible to prevent the second electrode layer 180 from being disconnected during coating and maintain the quality of the TFT substrate.

In addition, in this example, since the second passivation layer 170 is formed after the organic layer 160, a film formation temperature that is too high (>250° C.) cannot be used to avoid damage to the organic layer 160 (usually a low temperature of 200-220° C. film forming). Therefore, the etch rate of the second passivation layer 170 will be greater than that of the first passivation layer 150 (at least 2 times), so that the first edge 151 of the first passivation layer 150 at the side 191 of the via hole and the second passivation layer 170 at the The second edge 174 of the side edge 191 of the through hole is not necessarily aligned. The second edge 174 is farther away from the through hole 190 than the first edge 151, forming a stepped shape. The first edge 15 and the edge of the second edge 174 form a distance d( Figure 2B). In one embodiment, the range of distance d is between 500-2000 Angstroms

Please refer to FIG. 3 , which illustrates a thin film transistor substrate 12 according to another embodiment of the present invention. The thin film transistor substrate 12 adopts an etching stop layer (etching stop layer, ESL) structure, and the difference from the thin film transistor substrate 11 in FIG. 2A is that an etching stop layer 135 is provided between the first electrode layer 140 and the semiconductor layer 130 . The remaining components are similar to the thin film transistor substrate 11 in FIG. 2A , and will not be repeated here.

4A to 4D below illustrate the manufacturing method of the through hole 190 in FIG. 2A and FIG. 3 . For the convenience of illustration, the drawings only list the adjacent components of the through hole 190, and do not show the entire thin film transistor substrate.

First, as shown in FIG. 4A , the first passivation layer 150 and the organic layer 160 are deposited on the first electrode layer 140 in sequence. The material of the first passivation layer 150 is silicon nitride or silicon oxide, and the material of the organic layer is, for example, acrylic.

Next, as shown in FIG. 4B , a photolithographic etching process is performed with a photomask (not shown) to form an opening 161 on the organic layer 160 and expose the first passivation layer 150 .

Next, as shown in FIG. 4C , a second passivation layer 170 is formed to cover the first passivation layer 150 and the organic layer 160 . The material of the second passivation layer 170 is silicon nitride. In this step, a plurality of passivation films with different etching rates under the same etching conditions are formed to form the second passivation layer 170, wherein the lower passivation film etch rate is slower, and the first passivation film 171< The second passivation film 172<the third passivation film 173 . In one embodiment, the etching rate of the first passivation film 171 is about The etching rate of the second passivation film 172 is about The etching rate of the third passivation film 173 is about The etch rate can be changed by adjusting the pressure and the ratio of the injected gas. For example, the higher the pressure, the faster the etching rate of the formed passivation film; and the larger the ratio of (NH ₃ /SiH ₄ ) in the gas (NH ₃ is more), the etching rate of the formed passivation film The slower the rate. In this embodiment, the second passivation layer 170 composed of three passivation films 171, 172, and 173 is taken as an example, but in other embodiments, the second passivation layer 170 can also be two or more layers structure.

Then, as shown in FIG. 4D, the second passivation layer 170 and the first passivation layer 150 are subjected to a photolithographic etching process with a photomask (which may be the same as or different from the photomask used in FIG. The hole 190 is formed to expose the first electrode layer 140 . Since the etching rate of the passivation film close to the first passivation layer 150 (below) in the second passivation layer is relatively slow, and the etching rate of the passivation film far away from the first passivation layer 150 (above) is relatively fast, thus enabling passivation The second passivation layer 170 on the sidewall of the hole is not vertical, but has a second inclination angle θ2 less than 80 degrees, and the angle difference between the first inclination angle θ1 and the second inclination angle θ2 can also be made similar. Finally, a second electrode layer (not shown) is plated in the through hole to complete the through hole 190 in FIG. 2A and FIG. 3 .

In the display panel of the above embodiment, by adjusting the etching rate of the passivation layer in the thin film transistor substrate, the passivation layer on the sidewall of the through hole can be made relatively smooth and have a small angle difference. When the pixel electrode is plated in the through hole, it is not easy to form a disconnection, maintain low impedance, and improve the quality of the panel. In detail, the difference between the first inclination angle θ1 and the second inclination angle θ2 is less than 30 degrees, and the contact resistance between the pixel electrode and the drain electrode is 2286.1 ohms (Ω), compared with the existing first inclination angle θ1 and the second inclination angle θ2 If the difference is greater than 30 degrees, the contact impedance is 71930.6 ohms (Ω), which has the effect of greatly reducing the impedance.

In summary, although the present invention is disclosed in combination with the above embodiments, they are not intended to limit the present invention. Those skilled in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (20)

1. A display panel, comprising: Thin film transistor substrates, including: floor; a gate layer located on the bottom plate; a gate dielectric layer located on the gate layer; a semiconductor layer located on the gate dielectric layer; a first electrode layer located on the semiconductor layer; a first passivation layer located on the first electrode layer; a second passivation layer located on the first passivation layer, the second passivation layer has a through hole penetrating through the first passivation layer to expose part of the first electrode layer; and a second electrode layer located on the second passivation layer and electrically connected to the first electrode layer through the through hole, Wherein, the first passivation layer has a first inclination angle on the side of the through hole, the second passivation layer has a second inclination angle on the side of the through hole, and the angle difference between the first inclination angle and the second inclination angle less than 30 degrees; the opposite substrate is arranged opposite to the thin film transistor substrate; and The display layer is located between the TFT substrate and the opposite substrate. 2. The display panel as claimed in claim 1, wherein the TFT substrate further has an organic layer located between the first passivation layer and the second passivation layer. 3. The display panel as claimed in claim 1, wherein the second passivation layer directly covers the first passivation layer at a side of the through hole. 4. The display panel as claimed in claim 1, wherein the second passivation layer is composed of a first passivation film and a second passivation film, and the first passivation film is located between the first passivation layer and between the second passivation films. 5. The display panel as claimed in claim 4, wherein the etching rate of the first passivation film is lower than the etching rate of the second passivation film under the same etching condition. 6. The display panel as claimed in claim 1, wherein a material of the semiconductor layer is indium gallium zinc oxide (IGZO). 7. The display panel as claimed in claim 1, wherein the material of the first passivation layer is silicon oxide, and the material of the second passivation layer is silicon nitride. 8. The display panel as claimed in claim 3, wherein the first passivation layer has a first edge at the side of the through hole, the second passivation layer has a second edge at the side of the through hole, the The second edge is farther away from the through hole than the first edge. 9. The display panel as claimed in claim 8, wherein the distance between the first edge and the second edge is between 500-2000 angstroms 10. The display panel as claimed in claim 1, wherein an angle difference between the first inclination angle and the second inclination angle is between 3-10 degrees. 11. A display panel comprising: Thin film transistor substrates, including: floor; a gate layer located on the bottom plate; a gate dielectric layer located on the gate layer; a semiconductor layer located on the gate dielectric layer; a first electrode layer located on the semiconductor layer; a first passivation layer located on the first electrode layer; a second passivation layer located on the first passivation layer, the second passivation layer has a through hole penetrating through the first passivation layer to expose part of the first electrode layer; and a second electrode layer located on the second passivation layer and electrically connected to the first electrode layer through the through hole, Wherein, the second passivation layer is a multi-layer structure composed of multi-layer passivation films, and the second passivation layer has a second inclination angle between 10-80 degrees on the side of the through hole; the opposite substrate is arranged opposite to the thin film transistor substrate; and The display layer is located between the TFT substrate and the opposite substrate. 12. The display panel as claimed in claim 11, wherein the TFT substrate further has an organic layer located between the first passivation layer and the second passivation layer. 13. The display panel as claimed in claim 11, wherein the second passivation layer directly covers the first passivation layer at a side of the through hole. 14. The display panel according to claim 11, wherein the second passivation layer is composed of a first passivation film and a second passivation film, and the first passivation film is located between the first passivation layer and the between the second passivation films. 15. The display panel as claimed in claim 14, wherein the etching rate of the first passivation film is lower than the etching rate of the second passivation film under the same etching condition. 16. The display panel as claimed in claim 11, wherein a material of the semiconductor layer is indium gallium zinc oxide (IGZO). 17. The display panel as claimed in claim 11, wherein the material of the first passivation layer is silicon oxide, and the material of the second passivation layer is silicon nitride. 18. The display panel as claimed in claim 13, wherein the first passivation layer has a first edge at the side of the through hole, the second passivation layer has a second edge at the side of the through hole, the The second edge is farther away from the through hole than the first edge. 19. The display panel as claimed in claim 18, wherein the distance between the first edge and the second edge is between 500-2000 angstroms 20. The display panel as claimed in claim 11, wherein the second inclination angle is between 45-60 degrees.