CN104821350A - Manufacturing method of inversion structure of III semiconductor light-emitting device - Google Patents

Abstract

The present application discloses a method for manufacturing a flip-chip structure of a III-group semiconductor light-emitting device, including the steps of: growing a substrate, a buffer layer, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer sequentially from bottom to top Forming an epitaxial structure, the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer; depositing a transparent conductive layer; yellow photoetching process defines isolation grooves; depositing the first insulating layer structure; depositing P-type contact metal and N-type Contact the metal; deposit the second insulating layer structure; deposit flip-chip P-type electrodes and flip-chip N-type electrodes to obtain wafers; perform thinning, scribing, splitting, testing, and sorting of the wafers. The present invention all adopts the line convex mesa technology to replace the multiple hole vias technology in the prior art. In the first step of the present invention, the transparent conductive layer and the linear convex mesa pattern can be produced together, which not only simplifies a manufacturing process, but also solves the problem of alignment between the transparent conductive layer and the linear convex mesa pattern.

Description

Fabrication method of flip-chip structure of Group III semiconductor light-emitting device

technical field

The present application relates to the technical field of semiconductor lighting, in particular, to a method for fabricating a flip-chip structure of a Group III semiconductor light-emitting device.

Background technique

Traditional light-emitting diodes adopt a front-mount structure. Generally, the transparent conductive layer is made of high-transmittance materials, such as ITO, AZO, etc., and the electrodes are generally made of Cr/Pt/Au, etc. However, in the flip-chip structure, the light excited by the active layer It is directly emitted from the substrate on the other side of the electrode, so the requirement for the P-type electrode is changed to a highly reflective material covering the entire p-type nitride semiconductor layer as a mirror structure. The first is on the p-type nitride semiconductor layer Plating a transparent electrode with high transmittance plus high reflective metal, such as ITO/Ag, etc., the other is to directly coat a high reflective metal on the p-type nitride semiconductor layer as an ohmic contact layer and a mirror, For example, Ag, Al, etc., no matter which method is used, a metal protective layer (guard metal) must be used later to cover the highly reflective material to avoid instability, and then etch multiple holes (vias). The schematic diagram of the structure is shown in Figure 1. The surface is covered with the first insulating layer, with openings to access the n-type nitride semiconductor layer and metal protection layer, and then P-type contact metal and N-type contact metal are plated, and the entire surface is covered with the second insulating layer, with openings to access the P-type contact Metal and N-type contact metal, and finally flip-chip P-type electrodes and N-type electrodes are plated. Due to the relatively high precision of etching holes, the process is complicated and the production cost is also high.

Contents of the invention

In order to solve the problems in the above-mentioned prior art, the object of the present invention is to provide a method for fabricating a flip-chip structure of a Group III semiconductor light-emitting device, comprising the steps of:

Growing the substrate, the buffer layer, the n-type nitride semiconductor layer, the active layer and the p-type nitride semiconductor layer sequentially from bottom to top to form an epitaxial structure, and the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer ;

Deposit a transparent conductive layer on the upper surface of the p-type nitride semiconductor, and use a yellow photolithography process to define a line convex mesa pattern, and then etch the transparent conductive layer, p-type nitride semiconductor layer and active layer to expose the n-type nitride semiconductor layer, and then shrink the transparent conductive layer with an etching solution, and finally remove the photoresist to obtain a line convex mesa, and the upper surface of the line convex mesa has a transparent conductive layer, wherein the line convex mesa includes: The first upper surface, the side surface and the second upper surface, the first upper surface and the second upper surface respectively form an L-shaped structure with the side surface, and the first upper surface of the linear convex mesa is p-type nitrogen The upper surface of the compound semiconductor layer, the second upper surface of the linear convex mesa is the upper surface of the n-type nitride semiconductor layer;

The yellow photoetching process defines the isolation groove, then etches the n-type nitride semiconductor layer and the buffer layer to expose the substrate, and finally removes the photoresist;

Define the connection pattern between the P-type contact metal and the transparent conductive layer and the N-type contact metal and the second upper surface of the line convex mesa by using a yellow photolithography process, then etch the connection pattern of the first insulating layer structure, and finally remove the photoresist , to obtain the first insulating layer structure;

The yellow light stripping process defines the pattern of P-type contact metal and N-type contact metal, deposits P-type contact metal and N-type contact metal at the same time, and then uses the stripping process to remove the photoresist to obtain P-type contact metal and N-type contact metal;

Deposit the second insulating layer structure, use the photolithography process to define the opening access pattern of the P-type contact metal and N-type contact metal, etch the opening pattern of the second insulating layer structure, and finally remove the photoresist;

The yellow light lift-off process defines the pattern of flip-chip P-type electrodes and flip-chip N-type electrodes, deposits flip-chip P-type electrodes and flip-chip N-type electrodes, and then uses the lift-off process to remove the photoresist to obtain wafers;

Thinning, scribing, splitting, testing and sorting of the wafer.

Preferably, the first insulating layer structure is located on the first upper surface, the side surface, the second upper surface, the transparent conductive layer and the isolation groove.

Preferably, the structure of the first insulating layer is a single-layer oxide insulating layer, and the material of the single-layer oxide insulating layer is aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, One of silicon oxynitride and silicon nitride.

Preferably, the single-layer oxide insulating layer has a thickness of 30-2000 nm.

Preferably, the P-type contact metal is a full-surface metal, and the lower end of the P-type contact metal is arranged on the surface of the first insulating layer structure and on the transparent conductive layer;

The N-type contact metal is a full-surface metal, and the lower end of the N-type contact metal is arranged on the surface of the first insulating layer structure and the second upper surface.

Preferably, the P-type contact metal includes: a P-type wire electrode and a positive P-type pad, the lower end of the positive P-type pad is arranged on the surface of the first insulating layer structure, and the P-type wire electrode The lower end is arranged on the surface of the first insulating layer structure and the transparent conductive layer;

The N-type contact metal includes: an N-type wire electrode and a positive N-type pad, the lower end of the positive N-type pad is arranged on the surface of the first insulating layer structure, and the lower end of the N-type wire electrode is set on the first insulating layer structure and the second upper surface.

Preferably, the P-type contact metal and the N-type contact metal have the same structure, and both are composed of a first Ni layer, an Al layer, a second Ni layer, an Au layer and a third Ni layer arranged in sequence from inside to outside, or consist of Composed of Ti layer, Al layer, second Ni layer, Au layer and third Ni layer arranged in sequence from inside to outside, or composed of Ti layer, Al layer and third Ni layer arranged in sequence from inside to outside, or arranged in sequence from inside to outside The first Ni layer, the Al layer, the second Ni layer, the Pt layer, the Au layer and the third Ni layer, or the Cr layer, the Pt layer, the Au layer and the third Ni layer arranged in sequence from the inside to the outside, or the The first Ni layer, the Al layer, and the third Ni layer arranged in sequence from the inside to the outside are composed of a Rh layer, wherein the thickness of the Rh layer is 50-3000nm, the thickness of the first Ni layer is 0.3-300nm, and the Al layer The thickness of the second Ni layer is 10-300nm, the thickness of the Pt layer is 10-300nm, the thickness of the Au layer is 10-3000nm, and the thickness of the third Ni layer is 0.3-300nm.

Preferably, the second insulating layer structure is located on the upper surface of the first insulating layer structure, the upper surface of the P-type contact metal, and the upper surface of the N-type contact metal.

Preferably, the structure of the second insulating layer structure is a single-layer oxide insulating layer, and the material of the single-layer oxide insulating layer is aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, di One of niobium, silicon oxynitride and silicon nitride, the thickness of the single-layer oxide insulating layer is 30-2000nm.

Preferably, the lower end of the inverted P-type electrode is disposed on the surface of the P-type contact metal and the second insulating layer structure;

The lower end of the flip-chip N-type electrode is arranged on the surface of the N-type contact metal and the second insulating layer structure.

Preferably, the flip-chip P-type electrode has the same structure as the flip-chip N-type electrode, and is further composed of a Ti layer, a second Ni layer, and an Au layer arranged in sequence from the inside to the outside, or an intermediate Cr layer arranged in sequence from the inside to the outside , Pt layer, Au layer, second Ni layer, Pt layer, second Ni layer, AuSn layer, or consist of first Ni layer, Al layer, second Ni layer, Au layer arranged in sequence from inside to outside, or consist of Composed of middle Cr layer, Pt layer and Au layer arranged in sequence from inside to outside, or composed of first Ni layer, Al layer, middle Cr layer, second Ni layer and Au layer arranged in sequence from inside to outside, or arranged in sequence from inside to outside The composition of the first Ni layer, Al layer, second Ni layer, Pt layer, Au layer, wherein, the thickness of the first Ni layer is 0.4-3nm, the thickness of the second Ni layer is 10-300nm, the Ti layer The thickness of the Al layer is 50-300nm, the thickness of the Au layer is 20-3000nm, the thickness of the middle Cr layer is 10-300nm, the thickness of the Pt layer is 10-300nm, and the thickness of the AuSn layer is 1000- 5000nm.

Compared with the prior art, the manufacturing method of the flip-chip structure of the Group III semiconductor light-emitting device described in the present application has the following advantages:

(1) The present invention uniformly adopts the linear convex mesa technology to replace the multiple vias technology in the prior art.

(2) In the first step of the present invention, the transparent conductive layer and the linear convex mesa pattern can be fabricated together, which not only simplifies a manufacturing process, but also solves the problem of alignment between the transparent conductive layer and the linear convex mesa pattern.

(3) If the new structure of the present invention uses the first insulating layer structure 8-1 as a single-layer oxide insulating layer, then plate P-type contact metal 9 and N-type contact metal 10, and the P-type contact metal 9 and N-type contact The metal 10 includes a P-type wire electrode 15, an N-type wire electrode 17, a positively mounted P-type pad 16, and a positively mounted N-type pad 18. The structure shown in FIG. Use this step to estimate the photoelectric characteristics of the flip chip. If the guess does not reach the photoelectric characteristics of the flip chip, you can ship it in the normal package at this step.

Of course, implementing any product of the present application does not necessarily need to achieve all the technical effects described above at the same time.

Description of drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application. In the attached picture:

FIG. 1 is a schematic diagram of a flip-chip structure of an existing Group III nitride semiconductor light emitting device;

Fig. 2a-Fig. 2g are structural schematic diagrams corresponding to each step of the manufacturing process of the flip-chip LED chip in Example 1;

Figure 3a-Figure 3b is a top view and a cross-sectional view of a plurality of holes (vias) in the prior art;

The top view and cross-sectional view of the line convex mesa of Fig. 4a-Fig. 4b;

Figure 5 is a cross-sectional view of a P-type wire electrode;

Figure 6 is a cross-sectional view of an N-type wire electrode;

Fig. 7 is the structural representation of the flip-chip LED chip of embodiment 5;

Fig. 8 is the brightness-current-voltage characteristic of the flip-chip LED chip of embodiment 7;

Fig. 9 is the peak wavelength-current characteristic diagram of the flip-chip LED chip of embodiment 7;

Detailed ways

Certain terms are used, for example, in the description and claims to refer to particular components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. As mentioned throughout the specification and claims, "comprising" is an open term, so it should be interpreted as "including but not limited to". "Approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect. In addition, the term "coupled" herein includes any direct and indirect electrical coupling means. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically coupled to the second device, or indirectly electrically coupled through other devices or coupling means. connected to the second device. The subsequent description of the specification is a preferred implementation mode for implementing the application, but the description is for the purpose of illustrating the general principle of the application, and is not intended to limit the scope of the application. The scope of protection of the present application should be defined by the appended claims.

The present application will be described in further detail below in conjunction with the accompanying drawings, but it is not intended to limit the present application.

Example 1:

This embodiment provides a method for fabricating a flip-chip structure of a Group III semiconductor light-emitting device, as shown in Fig. 2a-Fig. 2g for details, including the following steps:

Step 1: The structural diagram is shown in Figure 2a, where the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4 and the p-type nitride semiconductor layer 5 are grown sequentially from bottom to top An epitaxial structure, the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer 5, this structure is an epitaxial structure, which is obtained through the manufacturing process in the prior art, and a flip chip is fabricated on the epitaxial structure The chip method includes the following steps:

The second step: the structural diagram is shown in Figure 2b, depositing a transparent conductive layer 14 on the upper surface of the p-type nitride semiconductor 5, and using a yellow photolithography process to define the line convex mesa 19 pattern, and then etching the transparent conductive layer 14, p-type Nitride semiconductor layer 5 and active layer 4, and expose n-type nitride semiconductor layer 3, then use etching solution to shrink transparent conductive layer 14, finally remove photoresist, obtain line convex mesa 19, and the line convex There is a transparent conductive layer 14 on the upper surface of the shaped mesa 19. It should be noted that this step can also be done separately from the transparent conductive layer 14 and the line convex mesa 19;

The third step: the structural diagram is shown in FIG. 2c. The method is to define the pattern of the isolation groove 20 in the yellow photoetching process, then etch the n-type nitride semiconductor layer 3 and the buffer layer 2 to expose the substrate 1, and finally remove the photoresist. Steps can be placed in any step;

Step 4: The structure of the first insulating layer structure 8-1 is a single-layer oxide insulating layer. The structure diagram is shown in Figure 2d. The method is to deposit the first insulating layer. The structure of the structure 8-1 is a single-layer oxide insulating layer , define the connection patterns between the P-type contact metal 9 and the transparent conductive layer 14 and the N-type contact metal 10 and the second upper surface 19-3 of the line convex mesa by using a yellow photolithography process, and then etch the first insulating layer structure 8-1 connection pattern, and finally remove the photoresist to obtain the first insulating layer structure 8-1;

Step 5: The structure diagram is shown in Figure 2e. The method is to define the patterns of the P-type contact metal 9 and the N-type contact metal 10 through the yellow light lift-off process, deposit the P-type contact metal 9 and the N-type contact metal 10 at the same time, and then use the lift-off process , and then remove the photoresist to obtain the P-type contact metal 9 and the N-type contact metal 10;

Step 6: The structure diagram is shown in FIG. 2f. The method is to deposit the second insulating layer structure 11-1, use the photolithography process to define openings to access the patterns of the P-type contact metal 9 and the N-type contact metal 10, and then etch the second insulating layer structure 11-1. The opening pattern of the two insulating layer structure 11-1, and finally remove the photoresist;

Step 7: The structure diagram is shown in Figure 2g. The method is to define the flip-chip P/N-type electrode 12 and 13 patterns through the yellow light stripping process, deposit the flip-chip P-type pad 12 and N-type pad 13, and then use the stripping process , and then remove the photoresist;

Step 8: Finally, the wafer is thinned, diced, split, tested, and sorted, and the steps are obtained through the manufacturing process in the prior art.

Through the above method, a flip-chip structure of a Group III semiconductor light emitting device is obtained, the structure comprising: a substrate 1, a buffer layer 2, an n-type nitride semiconductor layer 3, an active layer 4, a p-type nitride semiconductor layer 5, The first insulating layer structure 8-1, the P-type contact metal 9, the N-type contact metal 10, the second insulating layer structure 11-1, the flip-chip P-type electrode 12, the flip-chip N-type electrode 13 and the transparent conductive layer 14;

The substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4 and the p-type nitride semiconductor layer 5 form a nitride semiconductor structure with a line convex mesa 19;

The line convex mesa 19 includes a first upper surface 19-1 of the line convex mesa, a side surface 19-2 of the line convex mesa and a second upper surface 19-3 of the line convex mesa. Both ends of the surface are respectively provided with an L-shaped surface formed by the side surface and the second upper surface;

The first upper surface 19-1 of the linear convex mesa is the upper surface of the p-type nitride semiconductor layer 5, and the second upper surface 19-3 of the linear convex mesa is the upper surface of the n-type nitride semiconductor layer 3. surface;

The etched area of the line convex mesa 19 is single or multiple lines;

A transparent conductive layer 14 is provided on the first upper surface 19-1 of the linear convex mesa;

The material of the transparent conductive layer 14 can be a group consisting of indium tin oxide, cadmium tin oxide, zinc oxide, indium oxide, tin oxide, copper aluminum oxide, copper gallium oxide and strontium copper oxide.

The first upper surface 19-1, the side surface 19-2, the second upper surface 19-3 of the linear convex mesa, the upper surface of the transparent conductive layer 14 and the surface of the isolation groove 20 are all provided with a first insulating layer structure 8 -1;

The structure of the first insulating layer structure 8-1 is a single-layer oxide insulating layer;

The material of the single-layer oxide insulating layer is one of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride, and silicon nitride;

The thickness of each layer of the single-layer oxide insulating layer is 30-2000nm.

The P-type contact metal 9 and the N-type contact metal 10 can be divided into the following two situations:

(1) The P-type contact metal 9 is an entire surface metal, and the lower end of the entire surface metal is arranged on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14;

The N-type contact metal 10 is a solid metal, and the lower end of the solid metal is set on the surface of the first insulating layer structure 8-1 and the second upper surface 19-3 of the convex mesa;

(2) The P-type contact metal 9 includes a P-type wire electrode 15 and a positive P-type pad 16, and the lower end of the positive P-type pad 16 is arranged on the surface of the first insulating layer structure 8-1, so The lower end of the P-type wire electrode 15 is disposed on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14;

The N-type contact metal 10 includes an N-type wire electrode 17 and a positive N-type pad 18, the lower end of the positive N-type pad 18 is arranged on the surface of the first insulating layer structure 8-1, and the N-type The lower end of the wire electrode 17 is disposed on the first insulating layer structure 8-1 and the second upper surface 19-3 of the wire convex mesa.

The P-type contact metal 9 and the N-type contact metal 10 have the same structure, and are composed of a first Ni layer, an Al layer, a second Ni layer, an Au layer and a third Ni layer arranged in sequence from inside to outside, or from inside to outside Ti layer, Al layer, second Ni layer, Au layer and third Ni layer arranged in sequence from outside, or Ti layer, Al layer and third Ni layer arranged in sequence from inside to outside, or arranged in sequence from inside to outside The first Ni layer, the Al layer, the second Ni layer, the Pt layer, the Au layer and the third Ni layer, or the Cr layer, the Pt layer, the Au layer and the third Ni layer arranged in order from the inside to the outside, or the inside to the outside. The first Ni layer, the Al layer, and the third Ni layer arranged in sequence, or the Rh layer, wherein the thickness of the Rh layer is 50-3000nm, the thickness of the first Ni layer is 0.3-300nm, and the thickness of the Al layer The thickness of the second Ni layer is 10-300nm, the thickness of the Pt layer is 10-300nm, the thickness of the Au layer is 10-3000nm, and the thickness of the third Ni layer is 0.3-300nm.

The upper surfaces of the first insulating layer structure 8-1, the P-type contact metal 9 and the N-type contact metal 10 are provided with a second insulating layer structure 11-1;

The structure of the second insulating layer structure 11-1 is a single-layer oxide insulating layer

The material of the single-layer oxide insulating layer is one of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride and silicon nitride.

The thickness of the single-layer oxide insulating layer is 30-2000nm.

The lower end of the flip-chip P-type electrode 12 is disposed on the surface of the P-type contact metal 9 and the second insulating layer structure 11-1;

The lower end of the flip-chip N-type electrode 13 is disposed on the surface of the N-type contact metal 10 and the second insulating layer structure 11-1;

The structure of the above-mentioned flip-chip P-type electrode 12 and flip-chip N-type electrode 13 is composed of a Ti layer, a second Ni layer, and an Au layer arranged in sequence from the inside to the outside, or an intermediate Cr layer, a Pt layer, and an Au layer arranged in sequence from the inside to the outside. layer, the second Ni layer, the Pt layer, the second Ni layer, and the AuSn layer, or the first Ni layer, the Al layer, the second Ni layer, and the Au layer arranged in sequence from the inside to the outside, or the The middle Cr layer, Pt layer, Au layer, or the first Ni layer, Al layer, middle Cr layer, second Ni layer and Au layer arranged in sequence from inside to outside, or the first Ni layer arranged in sequence from inside to outside , an Al layer, a second Ni layer, a Pt layer, and an Au layer, wherein the first Ni layer has a thickness of 0.4 to 3 nm, the second Ni layer has a thickness of 10 to 300 nm, and the Ti layer has a thickness of 10 to 300 nm, The thickness of the Al layer is 50-300nm, the thickness of the Au layer is 20-3000nm, the thickness of the intermediate Cr layer is 10-300nm, the thickness of the Pt layer is 10-300nm, and the thickness of the AuSn layer is 1000-5000nm.

Example 2:

The new structure of the present invention adopts the technology of linear convex mesa 19 to replace the technology of multiple vias.

FIG. 3a is a top view of a plurality of vias in the prior art, and FIG. 3b is a cross-sectional view of FIG. 3a along the direction A-B.

FIG. 4a is a top view of the linear convex mesa, and FIG. 4b is a cross-sectional view along the A-B direction of FIG. 4a.

The etched area of the line convex mesa 19 is single or multiple lines;

The substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4 and the p-type nitride semiconductor layer 5 form a nitride semiconductor structure with a line convex mesa 19;

The linear convex mesa includes a first upper surface 19-1, a side surface 19-2 and a second upper surface 19-3, and the two ends of the first upper surface are respectively provided with the side surface and the second upper surface. 2. an L-shaped surface formed by the upper surface;

The first upper surface 19-1 of the linear convex mesa is the upper surface of the p-type nitride semiconductor layer, and the second upper surface 19-3 of the linear convex mesa is the upper surface of the n-type nitride semiconductor layer.

Example 3:

On the basis of Embodiment 1, the lower end of the P-type wire electrode 15 in the flip-chip structure obtained in this embodiment is arranged on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14 (as shown in Figure 5 shown).

Example 4:

On the basis of Example 1, this embodiment obtains that the N-type line electrode 17 in the flip-chip structure fills the groove of the line convex mesa 19, and is located on the first insulating layer structure 8-1 and the line convex mesa On the second upper surface 19-3 of (as shown in Figure 6).

Example 5:

In the fourth step of making the chip, as shown in FIG. 2d , this embodiment provides that the first insulating layer structure 8 - 1 is a single-layer oxide insulating layer.

The material of the above-mentioned single-layer oxide insulating layer is one of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride and silicon nitride, wherein the single-layer oxide The thickness of each insulating layer is 30-2000nm.

In the above technical solution, the method for making the first insulating layer structure 8-1 is a single-layer oxide insulating layer is as follows, using chemical vapor deposition or optical coating machine deposition to manufacture a single-layer oxide insulating layer, and then using yellow The photoetching process defines the pattern of the first insulating layer structure 8-1, and then etches the pattern of the first insulating layer structure 8-1 by dry method or wet method, and finally removes the photoresist to obtain the first insulating layer structure 8-1, wherein The etching gas for dry etching is SF ₆ /O ₂ or CF ₄ /CHF ₃ /O ₂ ;

Example 5:

In the fifth step of making the chip, the structural diagram is shown in Figure 2e or Figure 7. The method is to define the patterns of P-type contact metal 9 and N-type contact metal 10 in the yellow light stripping process, and deposit P-type contact metal 9 and N-type contact metal at the same time. Metal 10, and then use the stripping process to remove the photoresist to obtain P-type contact metal 9 and N-type contact metal 10;

Figure 2e shows that the P-type contact metal 9 and the N-type contact metal 10 include: P-type wire electrodes 15, N-type wire electrodes 17, positively installed P-type pads 16, and positively installed N-type pads 18. The lower end of the disk 16 is arranged on the surface of the first insulating layer structure 8-1, and the lower end of the P-type wire electrode 15 is arranged on the surface of the first insulating layer structure 8-1 and on the transparent conductive layer 14; The N-type contact metal 10 includes an N-type wire electrode 17 and a positive N-type pad 18, the lower end of the positive N-type pad 18 is arranged on the surface of the first insulating layer structure 8-1, and the N-type wire The lower end of the electrode 17 is disposed on the first insulating layer structure 8-1 and the second upper surface 19-3 of the line convex mesa;

7 shows that the P-type contact metal 9 and the N-type contact metal 10 are full-surface metals, and the lower end of the entire-surface metal of the P-type contact metal 9 is arranged on the surface of the first insulating layer structure 8-1 and is transparent. On the conductive layer 14; the entire metal lower end of the N-type contact metal 10 is disposed on the surface of the first insulating layer structure 8-1 and on the second upper surface 19-3 of the convex mesa;

Embodiment 7:

On the basis of Example 1, Example 2, Example 3, Example 4, Example 5, and Example 6, a group III nitride semiconductor flip-chip light-emitting device was fabricated, with a specification of 760um×250um. The manufacturing method of the semiconductor flip-chip device comprises the following steps:

The first step: the structural diagram is shown in Figure 2a, the method is to sequentially form the substrate 1, the buffer layer 2, the n-type nitride semiconductor layer 3, the active layer 4 and the p-type nitride semiconductor layer 5 from bottom to top grow to form an epitaxial structure, the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer 5, this structure is an epitaxial structure, which is obtained by the manufacturing process in the prior art, and is fabricated on the epitaxial structure The chip method includes the following steps:

The second step: the structural diagram is as shown in Figure 2b, using electron beam evaporation, or sputtering, or reactive plasma (reactive plasma deposition, RPD) to deposit ITO (indium tin oxide) when the transparent conductive layer 14 is in the p-type On the upper surface of the nitride semiconductor 5, the ITO thickness is 10-400nm, and the pattern of the line convex mesa 19 is defined by a yellow photolithography process, and then the transparent conductive layer 14, the p-type nitride semiconductor layer 5 and the active layer 4 are etched by ICP, The n-type nitride semiconductor layer 3 is exposed, and then the transparent conductive layer 14 is retracted with an etching solution, and finally the photoresist is removed to obtain a line convex mesa 19, and the upper surface of the line convex mesa 19 has a transparent conductive layer 14 (This step can also be done separately with the transparent conductive layer 14 and the line convex mesa 19); then Wafer is subjected to high-temperature annealing to form good ohmic contact and penetration between the transparent conductive layer 14 and the p-type nitride semiconductor layer 5 Rate. The annealing method uses a rapid annealing furnace (RTA) for rapid annealing at a temperature of 560° C. for 3 minutes.

The third step: the structural diagram is shown in FIG. 2c. The method is to define the pattern of the isolation groove 20 in the yellow photoetching process, then etch the n-type nitride semiconductor layer 3 and the buffer layer 2 to expose the substrate 1, and finally remove the photoresist. Steps can be placed in any step;

Step 4: The structure of the first insulating layer structure 8-1 is a single-layer oxide insulating layer, as shown in Figure 2d, using PECVD (Plasma Enhanced Chemical Vapor Deposition) to deposit _SiO2 as the first insulating layer structure 8-1, the thickness of SiO ₂ is 30-2000nm, the power is 50W, the pressure is 850mTorr, the temperature is 200-400°C, the N ₂ O is 1000sccm, the N ₂ is 400sccm, and the 5% SiH ₄ /N ₂ is 400sccm; use The photoetching process defines the connection pattern between the P-type contact metal 9 and the transparent conductive layer 14 and the N-type contact metal 10 and the second upper surface 19-3 of the line convex mesa, and then etches the first insulating layer by dry or wet method The connection pattern of structure 8-1, and finally remove the photoresist to obtain the first insulating layer structure 8-1;

Step 5: The structure diagram is shown in Figure 2e. The method is to define the patterns of P-type contact metal 9 and N-type contact metal 10 (including P-type line electrodes 15, N-type line electrodes 17 and positively mounted P-type pads) for the yellow light stripping process. 16. Formally install N-type pads 18), use electron beam evaporation to simultaneously deposit P-type contact metal 9 and N-type contact metal 10, and then use the stripping process to remove the photoresist to obtain P-type contact metal 9 and N-type contact metal 10;

In this embodiment, the P-type contact metal 9 and the N-type contact metal 10 have the same structure, and they are all arranged in sequence from the inside to the outside with a first Ni layer, an Al layer, a second Ni layer, an Au layer and a third Ni layer, wherein the first The thickness of the Ni layer is 0.4-3nm, the thickness of the Al layer is 50-300nm, the thickness of the second Ni layer is 10-300nm, the thickness of the Au layer is 10-3000nm, and the thickness of the third Ni layer is 0.4-3nm.

Figure 2e of this structure is the front-mount structure. The photoelectric characteristics of the front-mount can be measured in this step, and the photoelectric characteristics of the flip-chip can be estimated by using this step. If the photoelectric characteristics of the flip-chip are not estimated, the photoelectric characteristics of the flip-chip can be shipped in this step. .

Step 6: The structure of the second insulating layer structure 11-1 is a single-layer oxide insulating layer, as shown in Figure 2f, using PECVD (Plasma Enhanced Chemical Vapor Deposition) to deposit _SiO2 as the second insulating layer structure 11-1, the thickness of SiO ₂ is 30-2000nm, the power is 50W, the pressure is 850mTorr, the temperature is 200-400°C, the N ₂ O is 1000sccm, the N ₂ is 400sccm, and the 5% SiH ₄ /N ₂ is 400sccm; use The yellow photoetching process defines openings to access the P-type contact metal 9 and N-type contact metal 10 patterns, and then dry or wet etch the opening patterns of the second insulating layer structure 11-1, and finally remove the photoresist;

Step 7: The structure diagram is shown in Figure 2g. The method is to define the patterns of flip-chip P-type electrodes 12 and flip-chip N-type electrodes 13 in the yellow light stripping process, and simultaneously deposit flip-chip P-type electrodes 12 and flip-chip N-type electrodes 13 using electron beam evaporation. Install the N-type electrode 13, and then use the stripping process to remove the photoresist;

In this embodiment, the flip-chip P-type electrode 12 and the flip-chip N-type electrode 13 have the same structure, and they are all arranged in sequence from the inside to the outside Ti layer, the second Ni layer, and the Au layer, or the first Ni layer arranged in sequence from the inside to the outside. layer, Al layer, second Ni layer, and Au layer, wherein the thickness of the Ti layer is 10-300nm, the thickness of the first Ni layer is 0.4-3nm, the thickness of the second Ni layer is 10-300nm, and the thickness of the Al layer 50-300nm, and the thickness of the Au layer is 20-3000nm.

Step 8: Finally, the wafer is thinned, diced, split, tested, and sorted, and the steps are obtained through the manufacturing process in the prior art.

Step 9: Package the flip chip and measure the photoelectric characteristics.

According to the product made by the method provided in Example 7, the characteristic test results are as shown in Figure 8 and Figure 9:

From Figure 8 and Figure 9, we can see the photoelectric characteristics of the product. When the input current is 60mA, the product voltage is 2.82V, the product brightness is 23.4lm (color temperature 6807K), and the peak wavelength is 449.5nm; when the input current is 150mA, the product The voltage is 3.02V, the product brightness is 50.3lm (color temperature 7095K), and the peak wavelength is 447.3nm; when the input current is 620mA, the product voltage is 3.56V, the product brightness is 116.3lm (color temperature 7832K), and the peak wavelength is 447.3nm; It can be seen from Figure 8 and Figure 9 that this product can operate at a higher current and lower voltage than the standard device, with higher brightness and less wavelength shift.

Embodiment 8:

The manufacturing method of this embodiment is the same as that of Embodiment 7, the difference is that in the fifth step, the P-type contact metal 9 and the N-type contact metal 10 in this embodiment are full-surface metals, and other steps are the same, and the reverse of Embodiment 7 The installation structure diagram is shown in Figure 7.

Test condition is identical with embodiment 7, the technical product label of embodiment 7 is S1, the product label S2 that makes according to the method that embodiment 7 provides, detects under the same condition, test result is as table 1: as can be seen from table 1 , The photoelectric characteristics of S1 and S2 are almost the same.

Table 1 Comparison of product test results

Compared with the prior art, the manufacturing method of the flip-chip structure of the Group III semiconductor light-emitting device described in the present application has the following advantages:

(1) The new structures of the present invention all adopt the linear convex mesa technology to replace the multiple vias technology in the prior art.

(2) In the first step of the present invention, the transparent conductive layer and the linear convex mesa pattern can be fabricated together, which not only simplifies a manufacturing process, but also solves the problem of alignment between the transparent conductive layer and the linear convex mesa pattern.

(3) If the new structure of the present invention uses the first insulating layer structure 8-1 as a single-layer oxide insulating layer, then plate P-type contact metal 9 and N-type contact metal 10, and the P-type contact metal 9 and N-type contact The metal 10 includes a P-type wire electrode 15, an N-type wire electrode 17, a positively mounted P-type pad 16, and a positively mounted N-type pad 18. The structure shown in FIG. Use this step to estimate the photoelectric characteristics of the flip chip. If the guess does not reach the photoelectric characteristics of the flip chip, you can ship it in the normal package at this step.

The above description shows and describes several preferred embodiments of the present application, but as mentioned above, it should be understood that the present application is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various Various other combinations, modifications and environments, and can be modified by the above teachings or the technology or knowledge in the related field within the scope of the application concept described herein. However, modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present application, and should all be within the protection scope of the appended claims of the present application.

A1, a method for manufacturing a flip-chip structure of a Group III semiconductor light emitting device, characterized in that it comprises the steps of:

Growing the substrate, the buffer layer, the n-type nitride semiconductor layer, the active layer and the p-type nitride semiconductor layer sequentially from bottom to top to form an epitaxial structure, and the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer ;

Deposit a transparent conductive layer on the upper surface of the p-type nitride semiconductor, and use a yellow photolithography process to define a line convex mesa pattern, and then etch the transparent conductive layer, p-type nitride semiconductor layer and active layer to expose the n-type nitride semiconductor layer, and then shrink the transparent conductive layer with an etching solution, and finally remove the photoresist to obtain a line convex mesa, and the upper surface of the line convex mesa has a transparent conductive layer, wherein the line convex mesa includes: The first upper surface, the side surface and the second upper surface, the first upper surface and the second upper surface respectively form an L-shaped structure with the side surface, and the first upper surface of the linear convex mesa is p-type nitrogen The upper surface of the compound semiconductor layer, the second upper surface of the linear convex mesa is the upper surface of the n-type nitride semiconductor layer;

The yellow photoetching process defines the isolation groove, then etches the n-type nitride semiconductor layer and the buffer layer to expose the substrate, and finally removes the photoresist;

Define the connection pattern between the P-type contact metal and the transparent conductive layer and the N-type contact metal and the second upper surface of the line convex mesa by using a yellow photolithography process, then etch the connection pattern of the first insulating layer structure, and finally remove the photoresist , to obtain the first insulating layer structure;

The yellow light stripping process defines the pattern of P-type contact metal and N-type contact metal, deposits P-type contact metal and N-type contact metal at the same time, and then uses the stripping process to remove the photoresist to obtain P-type contact metal and N-type contact metal;

Deposit the second insulating layer structure, use the photolithography process to define the opening access pattern of the P-type contact metal and N-type contact metal, etch the opening pattern of the second insulating layer structure, and finally remove the photoresist;

The yellow light lift-off process defines the pattern of flip-chip P-type electrodes and flip-chip N-type electrodes, deposits flip-chip P-type electrodes and flip-chip N-type electrodes, and then uses the lift-off process to remove the photoresist to obtain wafers;

Thinning, scribing, splitting, testing and sorting of the wafer.

A2. The method for manufacturing the flip-chip structure of the Group III semiconductor light emitting device according to A1, wherein the first insulating layer structure is located on the first upper surface, the side surface, the second upper surface, and the transparent conductive layer. and isolation tanks.

A3. The method for manufacturing the flip-chip structure of the Group III semiconductor light-emitting device according to A2, wherein the structure of the first insulating layer is a single-layer oxide insulating layer, and the material of the single-layer oxide insulating layer is three One of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride and silicon nitride.

A4. The method for manufacturing the flip-chip structure of the Group III semiconductor light-emitting device according to A3, wherein the thickness of the single-layer oxide insulating layer is 30-2000 nm.

A5. The method for manufacturing the flip-chip structure of the Group III semiconductor light-emitting device according to A1, wherein the P-type contact metal is a full-surface metal, and the lower end of the P-type contact metal is arranged on the first insulating layer structure on the surface and on the transparent conductive layer;

The N-type contact metal is a full-surface metal, and the lower end of the N-type contact metal is arranged on the surface of the first insulating layer structure and the second upper surface.

A6, according to the method for manufacturing the flip-chip structure of the Group III semiconductor light-emitting device described in A1, it is characterized in that the P-type contact metal includes: P-type wire electrodes and positive P-type pads, and the positive P-type pads The lower end of the P-type wire electrode is arranged on the surface of the first insulating layer structure, and the lower end of the P-type wire electrode is arranged on the surface of the first insulating layer structure and the transparent conductive layer;

The N-type contact metal includes: an N-type wire electrode and a positive N-type pad, the lower end of the positive N-type pad is arranged on the surface of the first insulating layer structure, and the lower end of the N-type wire electrode is set on the first insulating layer structure and the second upper surface.

A7. The method for manufacturing the flip-chip structure of the Group III semiconductor light-emitting device according to A5 or A6, wherein the P-type contact metal and the N-type contact metal have the same structure, and both are the first ones arranged in sequence from inside to outside. Ni layer, Al layer, second Ni layer, Au layer and third Ni layer, or Ti layer, Al layer, second Ni layer, Au layer and third Ni layer arranged in order from inside to outside, or from inside to outside The Ti layer, the Al layer and the third Ni layer arranged in sequence from the outside, or the first Ni layer, the Al layer, the second Ni layer, the Pt layer, the Au layer and the third Ni layer arranged in order from the inside to the outside, or the It consists of a Cr layer, a Pt layer, an Au layer and a third Ni layer arranged in sequence from inside to outside, or consists of a first Ni layer, an Al layer, and a third Ni layer arranged in sequence from inside to outside, or consists of a Rh layer, wherein, The thickness of the Rh layer is 50-3000nm, the thickness of the first Ni layer is 0.3-300nm, the thickness of the Al layer is 50-3000nm, the thickness of the second Ni layer is 10-300nm, the thickness of the Pt layer is 10-300nm, Au The thickness of the layer is 10-3000nm, and the thickness of the third Ni layer is 0.3-300nm.

A8. The method for manufacturing the flip-chip structure of the Group III semiconductor light emitting device according to A1, wherein the second insulating layer structure is located on the upper surface of the first insulating layer structure, the upper surface of the P-type contact metal, and The N type contacts the upper surface of the metal.

A9, according to the method for manufacturing the flip-chip structure of the Group III semiconductor light-emitting device described in A8, it is characterized in that the structure of the second insulating layer structure is a single-layer oxide insulating layer, and the material of the single-layer oxide insulating layer It is one of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride and silicon nitride, and the thickness of the single-layer oxide insulating layer is 30-2000nm.

A10. The method for fabricating a flip-chip structure of a Group III semiconductor light-emitting device according to A1, wherein the lower end of the flip-chip P-type electrode is arranged on the surface of the P-type contact metal and the second insulating layer structure;

The lower end of the flip-chip N-type electrode is arranged on the surface of the N-type contact metal and the second insulating layer structure.

A11, according to the manufacturing method of the flip-chip structure of the Group III semiconductor light-emitting device described in A10, it is characterized in that the flip-chip P-type electrode has the same structure as the flip-chip N-type electrode, and further comprises Ti layers arranged in sequence from the inside to the outside , the second Ni layer, and the Au layer, or the middle Cr layer, the Pt layer, the Au layer, the second Ni layer, the Pt layer, the second Ni layer, and the AuSn layer arranged in sequence from the inside to the outside, or arranged in sequence from the inside to the outside The first Ni layer, Al layer, second Ni layer, Au layer, or the middle Cr layer, Pt layer, Au layer arranged in order from inside to outside, or the first Ni layer, Al layer arranged in order from inside to outside , the middle Cr layer, the second Ni layer and the Au layer, or the first Ni layer, the Al layer, the second Ni layer, the Pt layer, and the Au layer arranged in sequence from inside to outside, wherein the first Ni layer The thickness is 0.4-3nm, the thickness of the second Ni layer is 10-300nm, the thickness of the Ti layer is 10-300nm, the thickness of the Al layer is 50-300nm, the thickness of the Au layer is 20-3000nm, and the thickness of the middle Cr layer is 10-300nm, the thickness of the Pt layer is 10-300nm, and the thickness of the AuSn layer is 1000-5000nm.

Claims (10)

1. A method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device, characterized in that it comprises the steps of: Growing the substrate, the buffer layer, the n-type nitride semiconductor layer, the active layer and the p-type nitride semiconductor layer sequentially from bottom to top to form an epitaxial structure, and the upper surface of the epitaxial structure is the upper surface of the p-type nitride semiconductor layer ; Deposit a transparent conductive layer on the upper surface of the p-type nitride semiconductor, and use a yellow photolithography process to define a line convex mesa pattern, and then etch the transparent conductive layer, p-type nitride semiconductor layer and active layer to expose the n-type nitride semiconductor layer, and then shrink the transparent conductive layer with an etching solution, and finally remove the photoresist to obtain a line convex mesa, and the upper surface of the line convex mesa has a transparent conductive layer, wherein the line convex mesa includes: The first upper surface, the side surface and the second upper surface, the first upper surface and the second upper surface respectively form an L-shaped structure with the side surface, and the first upper surface of the linear convex mesa is p-type nitrogen The upper surface of the compound semiconductor layer, the second upper surface of the linear convex mesa is the upper surface of the n-type nitride semiconductor layer; The yellow photoetching process defines the isolation groove, then etches the n-type nitride semiconductor layer and the buffer layer to expose the substrate, and finally removes the photoresist; Define the connection pattern between the P-type contact metal and the transparent conductive layer and the N-type contact metal and the second upper surface of the line convex mesa by using a yellow photolithography process, then etch the connection pattern of the first insulating layer structure, and finally remove the photoresist , to obtain the first insulating layer structure; The yellow light stripping process defines the pattern of P-type contact metal and N-type contact metal, deposits P-type contact metal and N-type contact metal at the same time, and then uses the stripping process to remove the photoresist to obtain P-type contact metal and N-type contact metal; Deposit the second insulating layer structure, use the photolithography process to define the opening access pattern of the P-type contact metal and N-type contact metal, etch the opening pattern of the second insulating layer structure, and finally remove the photoresist; The yellow light lift-off process defines the pattern of flip-chip P-type electrodes and flip-chip N-type electrodes, deposits flip-chip P-type electrodes and flip-chip N-type electrodes, and then uses the lift-off process to remove the photoresist to obtain wafers; Thinning, scribing, splitting, testing and sorting of the wafer. 2. The method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device according to claim 1, wherein the first insulating layer structure is located on the first upper surface, side surface, second upper surface, transparent Conductive layer and isolation groove. 3. The method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device according to claim 2, wherein the structure of the first insulating layer is a single-layer oxide insulating layer, and the material of the single-layer oxide insulating layer It is one of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride and silicon nitride. 4 . The method for manufacturing a flip-chip structure of a Group III semiconductor light emitting device according to claim 3 , wherein the thickness of the single-layer oxide insulating layer is 30-2000 nm. 5. The method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device according to claim 1, wherein the P-type contact metal is a full-surface metal, and the lower end of the P-type contact metal is arranged on the first insulating layer. on the surface of the layer structure and on the transparent conductive layer; The N-type contact metal is a full-surface metal, and the lower end of the N-type contact metal is arranged on the surface of the first insulating layer structure and the second upper surface. 6. The method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device according to claim 1, wherein the P-type contact metal includes: a P-type wire electrode and a positive-mounted P-type pad, and the positive-mounted P-type The lower end of the pad is arranged on the surface of the first insulating layer structure, and the lower end of the P-type wire electrode is arranged on the surface of the first insulating layer structure and the transparent conductive layer; The N-type contact metal includes: an N-type wire electrode and a positive N-type pad, the lower end of the positive N-type pad is arranged on the surface of the first insulating layer structure, and the lower end of the N-type wire electrode is set on the first insulating layer structure and the second upper surface. 7. The method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device according to claim 5 or 6, wherein the P-type contact metal and the N-type contact metal have the same structure and are arranged sequentially from inside to outside The first Ni layer, the Al layer, the second Ni layer, the Au layer and the third Ni layer, or the Ti layer, the Al layer, the second Ni layer, the Au layer and the third Ni layer arranged in sequence from inside to outside, or It consists of a Ti layer, an Al layer and a third Ni layer arranged in sequence from inside to outside, or a first Ni layer, an Al layer, a second Ni layer, a Pt layer, an Au layer and a third Ni layer arranged in sequence from the inside to outside, Or it consists of a Cr layer, a Pt layer, an Au layer and a third Ni layer arranged in sequence from inside to outside, or it consists of a first Ni layer, an Al layer and a third Ni layer arranged in sequence from inside to outside, or it consists of a Rh layer, Among them, the thickness of the Rh layer is 50-3000nm, the thickness of the first Ni layer is 0.3-300nm, the thickness of the Al layer is 50-3000nm, the thickness of the second Ni layer is 10-300nm, and the thickness of the Pt layer is 10-300nm , the thickness of the Au layer is 10-3000nm, and the thickness of the third Ni layer is 0.3-300nm. 8. The method for manufacturing a flip-chip structure of a Group III semiconductor light emitting device according to claim 1, wherein the second insulating layer structure is located on the upper surface of the first insulating layer structure and on the P-type contact metal surface as well as the upper surface of the N-type contact metal. 9. The method for manufacturing a flip-chip structure of a Group III semiconductor light-emitting device according to claim 8, wherein the structure of the second insulating layer structure is a single-layer oxide insulating layer, and the single-layer oxide insulating layer The material is one of aluminum oxide, silicon dioxide, titanium dioxide, tantalum pentoxide, niobium pentoxide, silicon oxynitride and silicon nitride, and the thickness of the single-layer oxide insulating layer is 30-2000nm . 10. The method for fabricating a flip-chip structure of a Group III semiconductor light-emitting device according to claim 1, wherein the lower end of the flip-chip P-type electrode is arranged on the surface of the P-type contact metal and the second insulating layer structure superior; The lower end of the flip-chip N-type electrode is arranged on the surface of the N-type contact metal and the second insulating layer structure.