CN104820812B - The coding/decoding method and decoding apparatus of a kind of miller code of subcarrier modulation - Google Patents
The coding/decoding method and decoding apparatus of a kind of miller code of subcarrier modulation Download PDFInfo
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Abstract
The invention belongs to super high frequency radio frequency identification technology field, disclose the coding/decoding method and decoding apparatus of a kind of miller code of subcarrier modulation, this method and device use two clocks, Cycle Length at the phase bit flipping of miller code is counted, when count value reaches a subcarrier cycle, the pulse PA of a subcarrier cycle half is produced at phase bit flipping.Using another counter, the cycle of miller code is counted, when count value reaches the cycle of miller code, a pulse PB is produced.When a pulse PB is produced, judge whether there are phase bit flipping pulse PA generations in the corresponding code-element periods of pulse PB, if so, corresponding miller code then is decoded as into initial data 1, if it is not, corresponding miller code then is decoded as into initial data 0.Inventive algorithm and simple in construction, decoding efficiency height.
Description
Technical field
The invention belongs to super high frequency radio frequency identification technology field, more particularly to a kind of be used for super high frequency radio frequency identification
Subcarrier modulation miller code fast decoding method and decoding apparatus.
Background technology
Super high frequency radio frequency is recognized（UHF RFID）The general principle of technology is by by passive target（Label）Reflect
Signal realize the acquisition and identification to its information, this technology and radar operation principle be similar.
UHF RFID super high frequency radio frequency identification technologies are current state-of-the-art 4th generation automatic identification technologies, and the technology has
Recognition speed is fast, and identification distance is remote, and label cost is low, and recognition accuracy is high, and strong antijamming capability, service life is long, can penetrate
The advantages of nonmetallic materials.
UHF RFID application systems include passive electronic label, read write line and backend information system.When label is as waiting to know
Other object enters in read write line identification range, the ultra-high frequency wireless electric signal that read write line is sent in identification range, through label plus
Carry identification information back reflection and return read write line, then USB is utilized by read write line, Ethernet, the digital interface such as WIFI is uploaded to information
System.
UHF RFID read write line includes circuits below part：Digital baseband, transmission link, receives link, antenna
Radio-frequency front-end and digital interface.Transmission link is that the encoded signal for exporting digital baseband is modulated into ultra-high frequency wireless electric signal simultaneously
Antenna rf front end is delivered to through power amplifier amplification, receives link is the modulation returned from label of reception antenna radio-frequency front-end
Signal be demodulated to baseband signal deliver to digital baseband carry out the Digital Signal Processing such as decode.
The function that UHF RFID digital baseband is realized includes the physical layer of RFID air interface protocols（PHY layer）With media
Media access control layer（MAC layer）, including with lower module：Air protocol parsing, high-pass digital filter, low-pass digital filter
Device, burst bit synchronizer, frame starting identifier, codec, data check, receiving filter, the selection of I/Q signal intensity
Device, matched filter, decision device, data buffer etc..
Because the baseband signal of digital baseband is easily disturbed in transmitting procedure by surrounding environment, signal is set to propagate road
Wave distortion occurs in footpath, data and symbol signal integrity issue is produced.
Due in ultra-wideband systems, carrier frequency（800/900MHz）It is too high, it is impossible to recover to be available for label in carrier wave
The system clock used, it is therefore desirable to which oscillating circuit is set in passive label chip, but clock circuit in piece by technique,
The factors such as temperature, operating current, operating voltage influence, and precision is not ideal enough, and the operating current and work electricity of passive label
Pressure is formed by the reception energy rectification of label antenna, and the space-time path loss that signal and energy are propagated in atmosphere can be according to label
Change with read write line relative position and change, cause the operating current spread of voltage of tag clock circuit, ultimately result in label
The baseband signal of transmission has just produced deviation when sending, and produces the integrity issue of data and symbol signal.
Due to baseband signal in communication process with that will introduce error during generation, produce the complete of symbol signal
Sex chromosome mosaicism, is mainly shown as the frequency shift (FS) of symbol waveform and the skew of code element dutycycle, offset reference 5% to 35%.
Due to the skew of benchmark can be at random from 5% to 35%, thus have impact on the detection of baseband signal in digital baseband
Identification, bit synchronization, the decoding of data decision and code element.Cause decoding rate to decline with discrimination to decline.
The radio-frequency recognition system of current hyperfrequency（UHF RFID）The code encoding/decoding mode of base band data uses FM0 codes and Miller
Code.
The wave character of the miller code of conventional subcarrier modulation is：1）Each original " 0 " " 1 " data symbol contains M
The subcarrier cycle；2）Phase bit flipping does not occur for M subcarrier in symbol " 0 " cycle；3）Symbol " 1 " is the M/2 subcarrier week
Subcarrier phase is overturn after phase；4）Two adjacent symbols " 0 ", overturn, adjacent two in symbol boundary subcarrier
Symbol " 1 " is not overturn in symbol boundary subcarrier.
The content of the invention
The problem of in order to make up and solve above-mentioned, the present invention proposes a kind of algorithm structure simply, efficient miller code
Decoding scheme, to improve the accuracy rate of decoding miller code and reduce decoding difficulty and complexity.
In order to solve the above-mentioned technical problem, the present invention is achieved using following technical scheme.
A kind of miller code fast decoding method with miller code offset estimation with correction, it is characterised in that high level meter
Number device HC and low level counter LC high level respectively to miller code signal and low-level period length are counted, high level
When counter HC or low level counter LC counting steps reach a subcarrier Cycle Length, a phase bit flipping pulse is exported
Intermediate variable T values are rewritten in PA, triggering；Code-element period counter CC, is counted to the cycle of miller code, when count value reaches rice
When strangling a cycle of code, a cycle pulse PB is exported, triggering determining device judges current symbol period according to intermediate variable T values
Inside whether there is phase bit flipping pulse PA generation, if nothing, current miller code symbol decoding be 0, if so, then judge PA generation times away from
From the half whether upper recurrent pulse input time is more than the miller code cycle, if so, be 1 by current miller code symbol decoding,
If it is not, reinitializing, decoding is re-started；The intermediate variable T is reset when each cycle starts.
The real-time zero passage detection code stream lower edges saltus step of zero passage detection module, offset estimation counter AC is to adjacent two
The length of upper saltus step or lower saltus step carries out multiple counting statistics, and count value is returned into solution code controller, solves code controller
Offset estimation counter AC count value and the difference of code-element period counter CC count values are calculated, and regard result of calculation as frequency
The setting value of offset calibration code-element period counter CC count frequency；Duty cycle counter BC is long to the cycle of saltus step up and down
Degree carries out counting statistics, and count value is returned into solution code controller, and solution code controller calculates duty cycle counter BC counting
The difference of value and subcarrier half cycle length, and result of calculation is calibrated into high level counter HC and low as duty-cycle offset amount
The setting value of level counter LC count frequency.
The present invention miller code coding/decoding method, using n times of subcarrier frequency of clock frequency high level counter HC and
Low level counter LC high level respectively to miller code signal and low-level period length are counted, high level counter HC
Or low level counter LC counting steps are when reaching a subcarrier Cycle Length, it is subcarrier cycle half to produce a length
Phase bit flipping pulse PA.
Using code-element period counter CC, the cycle of miller code is counted, when count value reaches the cycle of miller code
When, produce a cycle pulse PB.
When a cycle pulse PB is produced, judge whether there is phase bit flipping in the corresponding code-element periods of recurrent pulse PB
Pulse PA is produced, if so, corresponding miller code then is decoded as into initial data 1, if it is not, corresponding miller code then is decoded as into original
Beginning data 0.
Specifically, high level counter HC is reset in low level, is counted in high level；Low level counter LC exists
Reset, counted in low level during high level.
Intermediate variable T values are defaulted as 0, when phase bit flipping pulse PA is produced, and triggering intermediate variable T values are 1, recurrent pulse PB
During generation, the judgement to T values is triggered, if T is 1, the corresponding miller code symbol datas of recurrent pulse PB are decoded as original
Data 1, then or when next cycle starts trigger intermediate variable T values and reset to 0, if T is 0, recurrent pulse PB
Corresponding miller code symbol data is decoded as initial data 0.
Further, real-time zero passage detection code stream lower edges saltus step, by offset estimation counter AC to adjacent two
The length of individual upper saltus step or lower saltus step carries out multiple counting statistics, uses offset estimation counter AC count value and code element week
The difference of phase counter CC count value as frequency offset calibration symbols cycle rate counter CC count frequency setting value.
Further, real-time zero passage detection code stream lower edges saltus step, by duty cycle counter BC to saltus step up and down
Cycle Length carries out counting statistics, using duty cycle counter BC count value and the difference of subcarrier half cycle length as accounting for
The setting value of empty ratio deviation amount calibration high level counter HC and low level counter LC count frequency.
Further, after judging to have phase bit flipping pulse PA generations, judge whether decoding is correct by the following method：Sentence
Whether disconnected phase bit flipping pulse entry time was more than the half in miller code cycle apart from upper recurrent pulse input time, if so,
Then decode correct, if it is not, then decoding abnormal.
The present invention also proposes a kind of miller code decoding apparatus of subcarrier modulation, including AD sampling modules, digital filter,
Detection module, IQ channel signal intensity selecting module, leading end judge module, decoder module and frequency deviation estimating modules, account for
Compared estimate module conciliates code controller, and each module clock is synchronous；AD sampling modules, digital filter, detection module, IQ passages letter
Number intensity selecting module, leading end judge module, decoder module and frequency deviation estimating modules and accounting estimation module are led to respectively
Digital interface is crossed to be connected with solution code controller.
Miller code baseband signal data stream is inputted from AD sampling modules input, AD sampling modules output termination digital filtering
Device input, digital filter output termination detection module input, detection module output termination IQ channel signals intensity selection
Module, the baseband signal of output is selected by IQ channel signal intensity selecting module, and a point three-channel parallel is output to offset estimation mould
Block, accounting estimation module, leading end judge module, decoder module is inputted by the baseband signal of leading end judge module.
Decoder module includes：High level counter HC, low level counter LC, code-element period counter CC, determining device, string
And converter, register.
High level counter HC and low level counter LC output ends are connected with register respectively, provided with centre in register
Variable T, high level counter HC and low level counter LC respectively to input decoder module miller code signal high level and
Low-level period length is counted, and high level counter HC or low level counter LC counting steps reach a subcarrier week
During phase length, a phase bit flipping pulse PA is exported to register, trigger register rewrites its intermediate variable T；Code-element period meter
The solution originator of number device CC output termination determining device, the output end of determining device connects deserializer, code element week by parallel interface
Phase, counter CC was counted to the cycle of miller code, when count value reaches a cycle of miller code, was exported to determining device
A cycle pulse PB, triggering determining device reads intermediate variable T values from register, and according to being in a T values judgement upper cycle
It is no to have phase bit flipping pulse PA generations, and will determine that result is output to as the decoded result of a upper period symbols with parallel signal
Deserializer；Parallel signal is converted into after serial signal exporting as final decoding data by deserializer, register
Intermediate variable is reset after a cycle terminates.
Offset estimation includes zero cross detection circuit and offset estimation counter AC, the real-time zero passage detection of its zero cross detection circuit
Code stream lower edges saltus step, offset estimation counter AC is repeatedly counted to the length of adjacent two upper saltus steps or lower saltus step
Number statistics, and count value is returned into solution code controller, solution code controller calculates offset estimation counter AC count value and code
The difference of first cycle rate counter CC count values, and it is used as using result of calculation frequency offset calibration symbols cycle rate counter CC counting
The setting value of frequency（The cycle of Miller code element is defined in international standard ISO/IEC 18000-6c 25us, 12.5us,
6.25us and 3.125us, if the sample rate of this system is 25MHz（That is 0.04us）, then the setting value after quantifying is exactly solid
Fixed 25us/0.04us=625,12.5us/0.04us=312,6.25us/0.04us=156,3.125us/0.04us
=78）.
Accounting estimation module includes zero cross detection circuit and duty cycle counter BC, the real-time zero passage inspection of its zero cross detection circuit
Code stream lower edges saltus step is surveyed, duty cycle counter BC carries out counting statistics to the Cycle Length of saltus step up and down, and by count value
Return to solution code controller, solution code controller calculate duty cycle counter BC count value and subcarrier half cycle length it
Difference, and the calibration high level counter HC and low level counter LC count frequency using result of calculation as duty-cycle offset amount
Setting value.
Miller code coding/decoding method proposed by the present invention and decoding apparatus, by counter respectively to phase bit flipping and code element week
Phase is counted, and is decoded based on count value, its algorithm and simple in construction, decoding efficiency height.Miller code frequency deviation is introduced to estimate
Meter is with correcting function, in the case of the existing frequency shift (FS) of base band miller code outflow, is rapidly performed by offset estimation, adjustment decoding ginseng
Number, improves the accuracy rate of decoding miller code and reduces decoding difficulty and complexity.
Brief description of the drawings
Fig. 1 is the miller code schematic diagram of subcarrier modulation.
Fig. 2 is the characteristic pulse time diagram of subcarrier modulation miller code stream.
Fig. 3 is subcarrier modulation miller code frequency deviation and duty-cycle offset schematic diagram.
Fig. 4 is subcarrier modulation miller code decoded state figure.
Fig. 5 is subcarrier modulation miller code decoding program flow chart.
Fig. 6 is that FPGA synchronous circuits realize structure chart.
Embodiment
The embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Realize that subcarrier modulation miller code is decoded, it is usually required mainly for solve, waveshape feature abstraction, the judgement of wave period, solution
Code, offset estimation and correction, duty-cycle offset estimation and correction.
To the waveshape feature abstraction of subcarrier modulation miller code：Use the clock of two n times of subcarrier frequencies（N is general
Be take 2 integral multiple, n depends on the ratio between sample rate and chip rate in the system of realization）, at the phase bit flipping of miller code
Cycle Length is counted, when count value reaches a subcarrier cycle, and a subcarrier cycle is produced at phase bit flipping
The pulse PA of half.
Judgement to the wave period of the symbol of subcarrier modulation miller code：Using n times of subcarrier frequency when
The counter CC of clock, is counted to the cycle of miller code, when count value reaches the cycle of miller code, produces a pulse
PB。
The counter that the Miller code phase upset Cycle Length modulated to subcarrier is counted：The phase of subcarrier modulation miller code
Level at bit flipping may keep high level to remain low level（, it is necessary to carry out signal intensity before being decoded
Calculating, while draw the baseline threshold of signal, when the signal quantization value of input more than baseline threshold is then judged as high level, instead
Be judged as low level）, two counters count the cycle of low and high level respectively, and high level counter HC is clear in low level
Zero, counted during high level, low level counter LC is opposite.
The quick decoding for the miller code modulated to subcarrier：When high level counter HC or low level counter LC is counted
When value is equal to the cycle of subcarrier（Cycle Length i.e. at phase bit flipping）Pulse PA is produced, and triggering intermediate variable T values are
1, when miller code recurrent pulse PB is triggered, if T is 1, miller code is decoded as initial data 1, if T is 0, miller code
It is decoded as initial data 0.
The error analysis occurred in the fast decoding method for the miller code modulated to subcarrier：The Miller modulated when subcarrier
When code has frequency deviation, the cycle rate counter CC of the miller code of subcarrier modulation count value is unable to the cycle of correct response miller code
Length, PB pulse sequence mistakes, the error accumulation after multiple code-element periods leads to not decoding；The Miller modulated when subcarrier
When code has duty cycle deviations, the cycle that low and high level counter HC and LC count values are unable at correct response phase bit flipping is long
Degree, PA pulse sequence mistakes cause decoding error.
The offset estimation for the miller code modulated to subcarrier and miller code cycle rate counter CC count calibrations methods：Real-time mistake
Zero detection code stream lower edges saltus step, by the length to adjacent two upper saltus steps or lower saltus step repeatedly count and unites
Meter, is counted using counter AC, and the difference of AC count values and CC count values is amounts of frequency offset, and AC count values can be used to calibrate CC countings
Value.
The duty compared estimate for the miller code modulated to subcarrier counts school with miller code low and high level counter HC and LC
Quasi- method：Real-time zero passage detection code stream lower edges saltus step, is carried out to this counting statistics to waveform by saltus step up and down, uses meter
Number device BC is counted, BC count values and CC/4 (subcarrier M=2), CC/8（Subcarrier M=4）, CC/16 (subcarrier M=8) difference be
Duty-cycle offset amount.
Fast decoding method is corrected to the miller code that subcarrier is modulated：Using offset estimation counter AC count values as
Code-element period counter CC calibration setup value, produce PB pulses, using duty cycle counter BC count values as phase bit flipping at
Low and high level counter HC, LC calibration setup value, produce PA pulses, PB pulse-triggered decision devices judge whether to generate PA
Pulse, whether code element is ' 0 ' if without PA pulses, if there is PA pulses, judge the PA pulsed times in CC counters 1/2
After, if then code element is ' 1 '.
Accompanying drawing 1 show the miller code schematic diagram of common subcarrier modulation, the miller code of subcarrier modulation M values be 2,4,
Waveform when 8, can extract its wave character from figure：1）Each original " 0 " " 1 " data symbol contains M subcarrier cycle；
2）Phase bit flipping does not occur for M subcarrier in symbol " 0 " cycle；3）Symbol " 1 " subcarrier phase after the M/2 subcarrier cycle
Bit flipping；4）Two adjacent symbols " 0 ", overturn in symbol boundary subcarrier, and two adjacent symbols " 1 " are in symbol
Boundary subcarrier is not overturn.
Accompanying drawing 2 show the characteristic pulse time diagram of subcarrier modulation miller code stream, secondary load according to the above description
The wave character of the miller code of ripple modulation, code-element period is counted using counter CC, and each code element cycle produces a PB pulse
205, the threshold value of the low and high level of waveform is detected and calculated in the detection stage, it is right respectively using low and high level counter HC and LC
Low and high level is counted and clear operation, and when wave level is more than threshold value, HC adds 1, and LC is reset, when waveform is less than threshold value
HC is reset, and LC adds 1, thus can 201,202 one PA pulse 203,204 of generation at phase bit flipping.
Feature according to Fig. 1 and Fig. 2, the quick decoding program state diagram designed according to the sequential of waveform, the present invention
As shown in figure 4, whole decoding process is divided into：Init state 401, offset estimation state 402, frame starting judges 403, decoding
State 404, frame end judges state 405, and abnormality processing state 406, baseband signal sequentially passes through 401,402,403,404,405
The original serial data stream of final output 01 is handled under state,
Shown in accompanying drawing 3,301 ideal waveform cycles, when there is duty-cycle offset, the cycle count value between 302 and 303
As the calibration data of duty-cycle offset, is that the cycle count value between 304 and 305 is the calibration of frequency deviation when there is frequency deviation
Data.
With reference to the accompanying drawings shown in 5, implementation subcarrier modulation miller code decoding process of the invention specifically includes following steps：
501:Parameter initialization, initializes the decoding pattern of baseband signal, chip rate, and air protocol parameter etc.；
502:Whether detection label signal arrives, and is passed because the signal transmission that super high frequency radio frequency is recognized belongs to burst
It is defeated, without synchronised clock, it is necessary to which whether detection baseband signal arrives in real time；
503:Reached if waveform is detected, program enters the stage of zero passage detection, the lower edges saltus step to waveform is entered
Mark is gone, to carry out the starting that frequency deviation and accounting are offset and the condition terminated；
504:The frequency shift (FS) degree of waveform is identified using the signal and counter of saltus step zero passage detection, and is counted with it
Calculating result goes calibration cycle to count；
505:The accounting degrees of offset of waveform is identified using the signal and counter of saltus step zero passage detection, and uses it
Result of calculation goes calibration cycle to count；
506:At low and high level counter detection phase bit flipping, and phase-triggered upset pulse；
507:The original position of code-element period is marked using counter, and triggers recurrent pulse；
508:After recurrent pulse is triggered, whether detection has phase bit flipping pulse in code-element period, if nothing, is decoded as 0,
Programming jump is to judgment frame termination condition, if so, jumping to 509；
509:The pulsed relative time interval with code-element period pulse of phase bit flipping is detected, if interval is more than 1/2
Code-element period be then decoded as 1, programming jump to judgment frame termination condition, if interval is less than 1/2 code-element period, baseband signal is different
Often, programming jump is to 510；
510:Baseband waveform abnormality processing, from new initiation parameter, carries out the idle port communication interaction of a new wheel.
With reference to the accompanying drawings shown in 6（Hollow arrow represents the data flowing of baseband signal in figure, and solid black arrow represents each
Handshake communication and state instruction between module）, the synchronous circuit structure that hardware description language of the invention is implemented is described as follows：
601:System clock, all module clocks are synchronous, using same work clock, worked using same edge；
602:The controller of decoder based on FSM, enables or closes each module, obtains the state of each module, and to each
Module is controlled, and the decoding process sequential made is operated according to the set sequential of controller；
603:Patten transformation is carried out to baseband signal, baseband waveform digitized, while being sampled to two paths of signals IQ；
604:The signal transactings such as digital filtering are carried out to baseband signal and remove signal noise；
605:The baseband signal of ultrahigh-frequency radio-frequency identification system belongs to Bursty signal transitions, is not notified without reference to clock
Signal, it is therefore desirable to which the data flow to baseband signal carries out detection computing, synchronous baseband signal；
606:Because baseband signal has two-way,（In UHF RFID application systems, the signal of base band is 2 tunnels and deposited,
Be referred to as I roads signal all the way, all the way referred to as Q roads signal, two paths of signals is generally propagated in atmosphere, due to environmental difference with
The design of hardware circuit, it may appear that the quality of IQ two paths of signals is different）The signal quality of two-way is different, and processing needs selection one
Signal intensity preferably, by sliding window mean algorithm, at calculating a good passage of signal intensity as follow-up signal at
The data flow of reason；
607:The miller code data of baseband subcarrier modulation are flowed into frequency deviation estimating modules, pass through Edge Detection
The saltus step up and down of waveform is extracted, the cycle parameter of actual waveform is judged by rolling counters forward；
608:The miller code data of baseband subcarrier modulation are flowed into accounting estimation module, pass through Edge Detection
The saltus step up and down of waveform is extracted, the accounting parameter of actual waveform is judged by rolling counters forward；
609:The air protocol specification of the ultrahigh-frequency radio-frequency identification system lead code of baseband signal, knows according to protocol contents
Do not go out after lead code, you can mark needs the beginning of decoding data；
610:After recurrent pulse is triggered, whether detection has phase bit flipping pulse in code-element period, if nothing, is decoded as 0,
Programming jump is to judgment frame termination condition, if so, the detection phase bit flipping pulsed relative time with code-element period pulse
Interval, is decoded as 1, programming jump to judgment frame termination condition, if interval is less than 1/2 if code-element period of the interval more than 1/2
Code-element period, baseband signal is abnormal；
611:Serioparallel exchange is carried out to ' 0 ' ' 1 ' decoded data flow to store in units of byte to data buffer zone
In；
612:The code stream of baseband signal is entered with n times of stream rate and handled in base band after over-sampling, bandwidth
N times of increase simultaneously.
Claims (9)
1. a kind of miller code fast decoding method with miller code offset estimation with correction, it is characterised in that high level is counted
Device HC and low level counter LC high level respectively to miller code signal and low-level period length are counted, high level meter
When number device HC or low level counter LC counting steps reach a subcarrier Cycle Length, a phase bit flipping pulse is exported
Intermediate variable T values are rewritten in PA, triggering；Code-element period counter CC, is counted to the cycle of miller code, when count value reaches rice
When strangling a cycle of code, a cycle pulse PB is exported, triggering determining device judges current symbol period according to intermediate variable T values
Phase bit flipping pulse PA generations are inside whether there is, if nothing, current miller code symbol decoding is 0, if so, then judging phase bit flipping pulse
Whether PA generation times were more than the half in miller code cycle apart from upper recurrent pulse PB input times, if so, by current Miller
Code symbol decoding is 1, if it is not, reinitializing, re-starts decoding；The intermediate variable T is reset when each cycle starts；
The real-time zero passage detection code stream lower edges saltus step of zero passage detection module, offset estimation counter AC is upper to adjacent two to jump
Become or the length of lower saltus step carries out multiple counting statistics, and count value is returned into solution code controller, solution code controller is calculated
Offset estimation counter AC count value and the difference of code-element period counter CC count values, and it regard result of calculation as frequency shift (FS)
Measure the setting value of calibration symbols cycle rate counter CC count frequency；Duty cycle counter BC enters to the Cycle Length of saltus step up and down
Row counting statistics, and count value is returned into solution code controller, solution code controller calculate duty cycle counter BC count value with
The difference of subcarrier half cycle length, and calibrate high level counter HC and low level using result of calculation as duty-cycle offset amount
The setting value of counter LC count frequency.
2. a kind of miller code decoding apparatus of subcarrier modulation, it is characterised in that including AD sampling modules, digital filter, inspection
Ripple module, IQ channel signal intensity selecting module, leading end judge module, decoder module and frequency deviation estimating modules, accounting
Estimation module conciliates code controller, and each module clock is synchronous；AD sampling modules, digital filter, detection module, IQ channel signals
Intensity selecting module, leading end judge module, decoder module and frequency deviation estimating modules and accounting estimation module pass through respectively
Digital interface is connected with solution code controller；
Miller code baseband signal data stream is inputted from AD sampling modules input, and AD sampling modules output termination digital filter is defeated
Enter end, digital filter output termination detection module input, detection module output terminates IQ channel signal intensity selecting modules,
The baseband signal of output is selected by IQ channel signal intensity selecting module, a point three-channel parallel is output to frequency deviation estimating modules, accounted for
Compared estimate module, leading end judge module, decoder module is inputted by the baseband signal of leading end judge module；
Decoder module includes：High level counter HC, low level counter LC, code-element period counter CC, determining device, string simultaneously turn
Parallel operation, register；
High level counter HC and low level counter LC output ends are connected with register respectively, and intermediate variable is provided with register
T, high level counter HC and low level counter LC are respectively to the high level and low electricity of the miller code signal for inputting decoder module
Mean period length is counted, and high level counter HC or low level counter LC counting steps reach that a subcarrier cycle is long
When spending, a phase bit flipping pulse PA is exported to register, trigger register rewrites its intermediate variable T；
The solution originator of code-element period counter CC output termination determining device, the output end of determining device connects string simultaneously by parallel interface
Converter, code-element period counter CC is counted to the cycle of miller code, when count value reaches a cycle of miller code,
A cycle pulse PB is exported to determining device, triggering determining device reads intermediate variable T values from register, and judges according to T values
Whether there are phase bit flipping pulse PA generations in a upper cycle, and will determine that result as the decoded result of a upper period symbols with simultaneously
Row signal output is to deserializer；Parallel signal is converted into after serial signal defeated as final decoding data by deserializer
Go out, the intermediate variable of register is reset after a cycle terminates；
Frequency deviation estimating modules include zero cross detection circuit and offset estimation counter AC, the real-time zero passage detection of its zero cross detection circuit
Code stream lower edges saltus step, offset estimation counter AC is repeatedly counted to the length of adjacent two upper saltus steps or lower saltus step
Number statistics, and count value is returned into solution code controller, solution code controller calculates offset estimation counter AC count value and code
The difference of first cycle rate counter CC count values, and it is used as using result of calculation frequency offset calibration symbols cycle rate counter CC counting
The setting value of frequency；
Accounting estimation module includes zero cross detection circuit and duty cycle counter BC, the real-time zero passage detection code of its zero cross detection circuit
Lower edges saltus step is flowed, duty cycle counter BC reads skip signal from solution code controller, the Cycle Length of saltus step up and down is entered
Row counting statistics, and count value is returned into solution code controller, solution code controller calculate duty cycle counter BC count value with
The difference of subcarrier half cycle length, and calibration high level counter HC and low level using result of calculation as duty-cycle offset amount
The setting value of counter LC count frequency.
3. the miller code decoding apparatus of subcarrier modulation according to claim 2, it is characterised in that when determining device judges have
Phase bit flipping pulse PA produce when, determining device judge phase bit flipping pulse PA generation times apart from upper recurrent pulse PB input when
Between whether be more than the miller code cycle half, if so, by current miller code symbol decoding be 1, if it is not, initialization systematic parameter,
Re-start decoding.
4. a kind of coding/decoding method of the miller code of subcarrier modulation, it is characterised in that use n times of subcarrier frequency of clock frequency
High level counter HC and low level counter LC high level respectively to miller code signal and low-level period length carry out
The counting step of any counter reaches that a subcarrier cycle is long in counting, high level counter HC and low level counter LC
When spending, the phase bit flipping pulse PA that a length is subcarrier cycle half is produced；
Using code-element period counter CC, the cycle of miller code is counted, when count value reaches the cycle of miller code, production
Raw a cycle pulse PB；
When a cycle pulse PB is produced, judge whether there is phase bit flipping pulse in the corresponding code-element periods of recurrent pulse PB
PA is produced, if so, corresponding miller code then is decoded as into initial data 1, if it is not, corresponding miller code then is decoded as into original number
According to 0.
5. the coding/decoding method of the miller code of subcarrier modulation according to claim 4, it is characterised in that high level counter
HC is reset in low level, is counted in high level；Low level counter LC is reset in high level, is counted in low level.
6. the coding/decoding method of the miller code of subcarrier modulation according to claim 5, it is characterised in that phase bit flipping pulse
When PA is produced, triggering intermediate variable T values are 1, when recurrent pulse PB is produced, and trigger the judgement to T values, if T is 1, this week
The corresponding miller code symbol datas of phase pulse PB are decoded as initial data 1, then or when next cycle starts in the middle of triggering
Variable T values reset to 0, if T is 0, the corresponding miller code symbol datas of recurrent pulse PB are decoded as initial data 0.
7. the coding/decoding method of the miller code of subcarrier modulation according to claim 4, it is characterised in that real-time zero passage detection
Code stream lower edges saltus step, is carried out many by offset estimation counter AC to the length of adjacent two upper saltus steps or lower saltus step
Secondary counting statistics, it is inclined as frequency using offset estimation counter AC count value and the difference of code-element period counter CC count values
The setting value of shifting amount calibration symbols cycle rate counter CC count frequency.
8. the coding/decoding method of the miller code of subcarrier modulation according to claim 4, it is characterised in that real-time zero passage detection
Code stream lower edges saltus step, carries out counting statistics to the Cycle Length of saltus step up and down by duty cycle counter BC, uses duty
The difference of count value and subcarrier half cycle length than counter BC calibrates high level counter HC as duty-cycle offset amount
With the setting value of low level counter LC count frequency.
9. the coding/decoding method of the miller code of subcarrier modulation according to claim 4, it is characterised in that when judgement has phase
Overturn after pulse PA generations, judge whether decoding is correct by the following method：Judge phase bit flipping pulse PA input time distances
Whether upper recurrent pulse PB input times are more than the half in miller code cycle, if so, then decoding correct, if it is not, then decoding different
Often.
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| CN105577588B (en) * | 2015-12-22 | 2019-01-18 | 山东大学 | A kind of coding/decoding method of Miller modulating subcarrier sequence |
| CN106911324A (en) * | 2015-12-23 | 2017-06-30 | 华大半导体有限公司 | A kind of PPM coding/decoding methods of high-frequency label |
| CN106921466B (en) * | 2015-12-25 | 2019-11-29 | 航天信息股份有限公司 | The method and apparatus being decoded are encoded to FM0 |
| CN106921462B (en) * | 2015-12-25 | 2019-11-29 | 航天信息股份有限公司 | The method and apparatus being decoded are encoded to FM0 |
| CN105718830B (en) * | 2016-01-29 | 2018-08-28 | 深圳市航天华拓科技有限公司 | A kind of decoder and coding/decoding method for UHF RFID readers |
| CN108256370B (en) * | 2016-12-29 | 2021-04-02 | 航天信息股份有限公司 | Decoding method and decoding system of RFID reader-writer |
| CN107302355A (en) * | 2017-06-21 | 2017-10-27 | 四川工业科技学院 | The clock recovery method and system of a kind of serial data decoding |
| CN108964868B (en) * | 2018-04-28 | 2020-08-18 | 昆明联诚科技股份有限公司 | FPGA-based ultrahigh frequency RFID reader-writer Miller subcarrier decoding method |
| GB2578296B (en) * | 2018-10-19 | 2022-03-16 | Univ Cranfield | Materials with structures exhibiting zero Poisson's ratio |
| CN109818713B (en) * | 2019-01-24 | 2021-07-20 | 浙江大华技术股份有限公司 | Subcarrier modulated Miller code decoding method, apparatus and device and storage medium |
| CN109885525B (en) * | 2019-03-19 | 2021-02-12 | 西安联飞智能装备研究院有限责任公司 | UART receiving method, device, electronic equipment and readable storage medium |
| CN111147107B (en) * | 2019-12-25 | 2021-12-24 | 天地融科技股份有限公司 | Data receiving method and device |
| CN113098809B (en) * | 2021-04-14 | 2023-10-10 | 中电海康无锡科技有限公司 | Software self-adaptive decoding method, device and wireless charging system |
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