CN104808126B - The test structure and method of testing of MOS transistor - Google Patents
The test structure and method of testing of MOS transistor Download PDFInfo
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Abstract
The test structure and method of testing of a kind of MOS transistor.The MOS transistor includes substrate, source electrode, drain electrode and grid, and the test structure of the MOS transistor includes：First driving electrodes, the source electrode is connected to by the first conductive plunger；First induction electrode, the source electrode is connected to by the second conductive plunger；Second driving electrodes, the drain electrode is connected to by the 3rd conductive plunger；Second induction electrode, the drain electrode is connected to by the 4th conductive plunger；3rd driving electrodes, the grid is connected to by the 5th conductive plunger；3rd induction electrode, the grid is connected to by the 6th conductive plunger.The test structure and method of testing of MOS transistor provided by the invention, eliminate the accuracy for because of influence of the dead resistance and the dead resistance of conductive plunger for testing electrode to test result, improving test MOS transistor resistance.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a testing structure and a testing method of an MOS transistor.
Background
In semiconductor processing, many important parameters and performance of a MOS transistor are related to the series resistance between its drain and source. Therefore, before modeling and simulation verification of the MOS transistor, the source-drain series resistance of the MOS transistor needs to be tested by using a testing device.
Fig. 1 is a schematic cross-sectional view of a conventional MOS transistor and a test structure thereof. Referring to fig. 1, the MOS transistor includes: a substrate 100; a source 101 and a drain 102 located within the substrate 100; a gate 103 over the substrate 100. And the source-drain series resistance Rm of the MOS transistor is the sum of the source parasitic resistance Rs, the drain parasitic resistance Rd and the channel parasitic resistance Rch. The test structure of the MOS transistor comprises: a first test electrode S connected to the source electrode 101 through a first conductive plug T1; a second test electrode D connected to the drain electrode 102 through a second conductive plug T2; a third test electrode G connected to the gate 103 through a third conductive plug T3.
Fig. 2 is a schematic circuit diagram of the MOS transistor shown in fig. 1 and its test structure. With reference to fig. 1 and fig. 2, when the source-drain series resistance Rm is tested, a source voltage Vs is applied to the source 101 through the first test electrode S and the first conductive plug T1, a drain voltage Vd is applied to the drain 102 through the second test electrode D and the second conductive plug T2, and a gate voltage Vg is applied to the gate 103 through the third test electrode G and the third conductive plug T3. Typically, the source voltage Vs applied to the source 101 is 0V.
After applying a voltage to each electrode of the MOS transistor, the drain current Id of the MOS transistor is tested through the first test electrode S, the first conductive plug T1, the second test electrode D, and the second conductive plug T2. Acquiring the source-drain series resistance Rm according to the characteristics of the MOS transistor: and Rm is a resistance value of the source-drain series resistance Rm, Uds is a voltage value of a drain-source voltage of the MOS transistor, namely a voltage value obtained by subtracting the source voltage Vs from the drain voltage Vd, and Id is a current value of the drain current Id. It should be noted that the resistance Rm of the source-drain series resistor Rm varies with the voltage value of the gate voltage Vg, that is, the gate voltage Vg with different voltage values is applied, and the obtained resistance Rm of the source-drain series resistor Rm is also different.
In some modeling and simulation verification, not only the source-drain series resistance Rm but also the sum of the source parasitic resistance Rs and the drain parasitic resistance Rd need to be known. In the prior art, when the sum of the source parasitic resistance Rs and the drain parasitic resistance Rd is tested, at least two MOS transistors with the same channel width and different channel lengths are selected for testing. Both the channel width and the channel length refer to design values, and there is a tendency for a deviation between the design values and actual values of the channel width and the channel length due to limitations of a manufacturing process.
Under the condition of applying the same grid voltage, the resistance Rm of the source-drain series resistance Rm of each MOS transistor is obtained by adopting the method. Referring to fig. 3, a two-dimensional coordinate system is established: the abscissa represents the designed channel length Lm of the MOS transistor, and the ordinate represents the source-drain series resistance Rm of the MOS transistor; making discrete points in the two-dimensional coordinate system according to the resistance Rm of the source-drain series resistor Rm of each MOS transistor and the length value of the designed channel length Lm corresponding to the resistance Rm; and performing linear fitting on the discrete points to obtain a characteristic curve of the source-drain series resistance Rm of the MOS transistor changing along with the designed channel length Lm, wherein in the figure 3, 5 MOS transistors are selected for testing. By adopting the same method, under the condition of applying different grid voltages, a characteristic curve of source-drain series resistance Rm of at least two MOS transistors changing along with the designed channel length Lm is obtained. Fig. 3 shows characteristic curves (L1, L2, L3, L4) of source-drain series resistances Rm of four MOS transistors varying with a designed channel length Lm thereof, and the four characteristic curves (L1, L2, L3, L4) intersect at a point a.
According to the characteristics of the MOS transistor: rm ═ r (rd + rs) + (lm- Δ L)/μ x Co x W × (Vgs-V)T) Wherein Rd is a resistance value of the drain parasitic resistance Rd, Rs is a resistance value of the source parasitic resistance Rs, Lm is a length value of the design channel length Lm, Δ L is a deviation value of the design channel length Lm and an actual channel length, μ is a carrier mobility of the MOS transistor, Co is a capacitance value of a gate unit area oxide layer capacitor of the MOS transistor, W is a width value of a channel width of the MOS transistor, Vgs is a voltage value obtained by subtracting the source voltage Vs from the gate voltage Vg, and V is a voltage value obtained by subtracting the source voltage Vs from the gate voltage VgTIs the voltage value of the threshold voltage of the MOS transistor. With reference to fig. 3 and the above formula, an abscissa value corresponding to the point a is a deviation value Δ L between the designed channel length Lm and the actual channel length, and an ordinate value corresponding to the point a is a sum of the resistance Rd of the drain parasitic resistor Rd and the resistance Rs of the source parasitic resistor Rs.
Parasitic resistances exist in the first test electrode S, the first conductive plug T1, the second test electrode D, the second conductive plug T2, the third test electrode G, and the third conductive plug T3, when the resistance values of the source parasitic resistance Rs and the drain parasitic resistance Rd are large, the parasitic resistances of each test electrode and each conductive plug can be ignored, and it is feasible to obtain the source-drain resistance Rm, the source parasitic resistance Rs, the drain parasitic resistance Rd, and the deviation value Δ L between the designed channel length Lm and the actual channel length by using the method in the prior art. However, as semiconductor technology advances, the resistance values of the source parasitic resistance Rs and the drain parasitic resistance Rd are made smaller and smaller, and the accuracy of the MOS transistor resistance obtained by using the prior art is low, which affects the accuracy of modeling and simulation verification.
Disclosure of Invention
The invention solves the problem of low accuracy of testing the resistance of the MOS transistor.
In order to solve the above problem, the present invention provides a test structure of a MOS transistor, where the MOS transistor includes a substrate, a source, a drain, and a gate, and the test structure of the MOS transistor includes:
a first driving electrode connected to the source electrode through a first conductive plug;
the first induction electrode is connected to the source electrode through a second conductive plug;
a second driving electrode connected to the drain electrode through a third conductive plug;
the second induction electrode is connected to the drain electrode through a fourth conductive plug;
a third driving electrode connected to the gate electrode through a fifth conductive plug;
and the third induction electrode is connected to the grid electrode through a sixth conductive plug.
Based on the test structure of the MOS transistor, the invention also provides a test method of the MOS transistor, which comprises the following steps: executing a voltage and current obtaining step to obtain a gate-source voltage, a drain-source voltage and a drain current of the MOS transistor;
wherein the voltage and current obtaining step comprises:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
and testing the potential of the first sensing electrode, the potential of the second sensing electrode and the potential of the third sensing electrode to obtain the gate-source voltage and the drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain the drain current.
Based on the test structure of the MOS transistor, the invention also provides another test method of the MOS transistor, which comprises the following steps:
setting the distance from the second conductive plug to the grid and the distance from the fourth conductive plug to the grid to be adjustable distances;
executing a resistance obtaining step to obtain a source-drain series resistance of the MOS transistor;
changing the distance value of the adjustable distance, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance of the MOS transistor along with the change of the adjustable distance;
according to a characteristic curve that the source-drain series resistance of the MOS transistor changes along with the adjustable distance, the channel parasitic resistance of the MOS transistor is equal to the source-drain series resistance of the corresponding MOS transistor when the distance value of the adjustable distance is zero;
wherein the resistance obtaining step includes:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode and the potential of the second sensing electrode to obtain drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain drain current;
and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
Based on the test structure of the MOS transistor, the invention also provides another test method of the MOS transistor, which comprises the following steps:
setting the distance from the second conductive plug to the grid electrode as a minimum safety distance, and setting the distance from the fourth conductive plug to the grid electrode as an adjustable distance;
executing a resistance obtaining step to obtain a source-drain series resistance of the MOS transistor;
changing the distance value of the adjustable distance, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance of the MOS transistor along with the change of the adjustable distance;
according to a characteristic curve that the source-drain series resistance of the MOS transistor changes along with the adjustable distance, the sum of the minimum source parasitic resistance and the channel parasitic resistance of the MOS transistor is equal to the source-drain series resistance of the corresponding MOS transistor when the distance value of the adjustable distance is zero;
wherein the resistance obtaining step includes:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode and the potential of the second sensing electrode to obtain drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain drain current;
and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
Based on the test structure of the MOS transistor, the invention also provides another test method of the MOS transistor, which comprises the following steps:
setting the distance from the fourth conductive plug to the grid electrode as a minimum safety distance, and setting the distance from the second conductive plug to the grid electrode as an adjustable distance;
executing a resistance obtaining step to obtain a source-drain series resistance of the MOS transistor;
changing the distance value of the adjustable distance, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance of the MOS transistor along with the change of the adjustable distance;
according to a characteristic curve that the source-drain series resistance of the MOS transistor changes along with the adjustable distance, the sum of the minimum drain parasitic resistance and the channel parasitic resistance of the MOS transistor is equal to the source-drain series resistance of the corresponding MOS transistor when the distance value of the adjustable distance is zero;
wherein the resistance obtaining step includes:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode and the potential of the second sensing electrode to obtain drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain drain current;
and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
Based on the test structure of the MOS transistor, the invention also provides another test method of the MOS transistor, which comprises the following steps:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode, the potential of the second sensing electrode, the potential of the fourth sensing electrode and the potential of the fifth sensing electrode to obtain a first drain-source voltage and a second drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain a drain current, wherein the first drain-source voltage is equal to the potential of the second sensing electrode minus the potential of the first sensing electrode, and the second drain-source voltage is equal to the potential of the fifth sensing electrode minus the potential of the fourth sensing electrode;
obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the first drain-source voltage compared with the drain current;
and obtaining the sum of the parasitic resistance of the first conductive plug and the parasitic resistance of the third conductive plug according to the fact that the sum of the source-drain series resistance of the MOS transistor, the parasitic resistance of the first conductive plug and the parasitic resistance of the third conductive plug is equal to the ratio of the second drain-source voltage to the drain current.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the test structure of the MOS transistor, the source electrode, the drain electrode and the grid electrode of the MOS transistor are respectively connected with the two test electrodes, wherein one test electrode is used as a driving electrode, and the other test electrode is used as an induction electrode. When testing the resistance of the MOS transistor, the driving and the testing are separately carried out, no large current flows through the induction electrode, the influence of the parasitic resistance of the testing electrode and the parasitic resistance of the conductive plug on the testing result is eliminated, and the accuracy of testing the resistance of the MOS transistor is improved.
In the alternative scheme of the invention, the number of the first conductive plugs, the number of the second conductive plugs, the number of the third conductive plugs and the number of the fourth conductive plugs are at least two, so that the parasitic resistance of the conductive plugs is reduced, and the accuracy of testing the resistance of the MOS transistor is further improved.
In the alternative of the invention, the distance from the first conductive plug to the grid is greater than the distance from the second conductive plug to the grid, the distance from the third conductive plug to the grid is greater than the distance from the fourth conductive plug to the grid, and the distance from the connecting end of the fifth conductive plug and the grid to the center of the grid is greater than the distance from the connecting end of the sixth conductive plug and the grid to the center of the grid.
Based on the test structure of the MOS transistor provided by the invention, the test method of the MOS transistor provided by the invention can accurately obtain the source-drain series resistance, the transfer characteristic curve, the output characteristic curve, the channel parasitic resistance, the minimum source parasitic resistance, the minimum drain parasitic resistance of the MOS transistor, and the sum of the parasitic resistance of the second conductive plug and the parasitic resistance of the fourth conductive plug.
Drawings
FIG. 1 is a schematic cross-sectional view of a prior art MOS transistor and test structure thereof;
FIG. 2 is a schematic circuit diagram of the MOS transistor and its test structure shown in FIG. 1;
FIG. 3 is a schematic diagram showing the relationship between the source-drain series resistance of the MOS transistor shown in FIG. 1 and the variation of the designed channel length;
FIG. 4 is a cross-sectional structure diagram of a MOS transistor and a test structure thereof according to an embodiment of the present invention;
FIG. 5 is a layout diagram of the MOS transistor and its test structure shown in FIG. 4;
FIG. 6 is a schematic perspective view of the MOS transistor and its test structure shown in FIG. 4;
FIG. 7 is a schematic flow chart of testing the source-drain series resistance of the MOS transistor according to the embodiment of the present invention;
fig. 8 is a schematic diagram of a variation relationship between source-drain series resistance of the MOS transistor and variation of an adjustable distance when the distance from the second conductive plug to the gate and the distance from the fourth conductive plug to the gate shown in fig. 4 are both adjustable distances;
fig. 9 is a schematic diagram of a variation relationship between the source-drain series resistance of the MOS transistor and the variation of the adjustable distance when the distance from the second conductive plug to the gate is the minimum safe distance and the distance from the fourth conductive plug to the gate is the adjustable distance shown in fig. 4;
fig. 10 is a schematic diagram of a variation relationship between the source-drain series resistance of the MOS transistor and the variation of the adjustable distance when the distance from the fourth conductive plug to the gate is the minimum safe distance and the distances from the second conductive plug to the gate are both adjustable distances, as shown in fig. 4;
FIG. 11 is a cross-sectional view of another MOS transistor and its test structure according to the embodiment of the invention;
fig. 12 is a layout diagram of the MOS transistor and its test structure shown in fig. 10;
fig. 13 is a schematic perspective view of the MOS transistor shown in fig. 10 and a test structure thereof.
Detailed Description
Referring to fig. 1, since the first test electrode S, the first conductive plug T1, the second test electrode D, the second conductive plug T2, the third test electrode G, and the third conductive plug T3 all have parasitic resistances, an error exists between the voltage of the source 101 and the source voltage Vs, an error exists between the voltage of the drain 102 and the drain voltage Vd, and an error exists between the voltage of the gate 103 and the gate voltage Vg. Therefore, when the test structure of the MOS transistor shown in fig. 1 is used to test the resistance of the MOS transistor, the accuracy of the test result is low.
The technical scheme of the invention provides a test structure and a test method of an MOS transistor, which separately operate driving and testing by arranging a driving electrode and an induction electrode, and no large current flows through the induction electrode, thereby improving the accuracy of testing the resistance of the MOS transistor.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to fig. 6 are a schematic cross-sectional structure diagram, a schematic layout diagram, and a schematic perspective structure diagram of an MOS transistor and a test structure thereof according to an embodiment of the present invention. Referring to fig. 4 to 6, the MOS transistor includes: a substrate 400; a source 401 and a drain 402 within the substrate 400; a gate 403 over the substrate 400. And the source-drain series resistance Rm of the MOS transistor is the sum of the source parasitic resistance Rs, the drain parasitic resistance Rd and the channel parasitic resistance Rch.
The test structure of the MOS transistor comprises a first driving electrode FS, a first sensing electrode SS, a second driving electrode FD, a second sensing electrode SD, a third driving electrode FG and a third sensing electrode SG. Wherein the first driving electrode FS is connected to the source electrode 401 through a first conductive plug; the first sensing electrode SS is connected to the source electrode 401 through a second conductive plug; the second driving electrode FD is connected to the drain 402 through a third conductive plug; the second sensing electrode SD is connected to the drain electrode through a fourth conductive plug; the third driving electrode FG is connected to the gate 403 through a fifth conductive plug T5; the third sensing electrode SG is connected to the gate electrode 403 through a sixth conductive plug T6.
It should be noted that the number of the first conductive plugs, the number of the second conductive plugs, the number of the third conductive plugs, and the number of the fourth conductive plugs may be one, or may be at least two, so as to reduce parasitic resistances of the first conductive plugs, the second conductive plugs, the third conductive plugs, and the fourth conductive plugs. When the number of the first conductive plugs, the number of the second conductive plugs, the number of the third conductive plugs, and the number of the fourth conductive plugs are at least two, the distance from each first conductive plug to the gate 403 is equal, the distance from each second conductive plug to the gate 403 is equal, the distance from each third conductive plug to the gate 403 is equal, and the distance from each fourth conductive plug to the gate 403 is equal.
In this embodiment, the number of the first conductive plugs, the number of the second conductive plugs, the number of the third conductive plugs, and the number of the fourth conductive plugs are all four. Specifically, the first driving electrode FS is connected to the source electrode 401 through a first conductive plug (T11 to T14); the first sensing electrode SS is connected to the source electrode 401 through a second conductive plug (T21-T24); the second driving electrode FD is connected to the drain electrode 402 through a fourth conductive plug (T41-T44); the second sensing electrode SD is connected to the drain electrode through a third conductive plug (T31-T34). The distances from the first conductive plugs (T11-T14) to the gate 403 are equal, the distances from the second conductive plugs (T21-T24) to the gate 403 are equal, the distances from the third conductive plugs (T31-T34) to the gate 403 are equal, and the distances from the fourth conductive plugs (T41-T44) to the gate 403 are equal.
When the test structure of the MOS transistor according to the embodiment of the present invention is used to test the resistance of the MOS transistor, the first driving electrode FS, the second driving electrode FD, and the third driving electrode FG are adapted to receive a test voltage, and the first sensing electrode SS, the second sensing electrode SD, and the third sensing electrode SG are respectively adapted to sense the voltages of the source 401, the drain 402, and the gate 403. The first sensing electrode SS, the second sensing electrode SD and the third sensing electrode SG are disposed on a path through which a current passes, and the accuracy of the sensed voltage is higher.
Therefore, in this embodiment, the distance d1 from the first conductive plug (T11-T14) to the gate 403 is greater than the distance d2 from the second conductive plug (T21-T24) to the gate 403, and the distance d3 from the third conductive plug (T31-T34) to the gate 403 is greater than the distance d4 from the fourth conductive plug (T41-T44) to the gate 403. The connection end of the fifth conductive plug T5 and the gate 403 and the connection end of the sixth conductive plug T6 and the gate 403 are located on the same side of the gate 403, and the distance from the connection end of the fifth conductive plug T5 and the gate 403 to the center of the gate 403 is greater than the distance from the connection end of the sixth conductive plug T6 and the gate 403 to the center of the gate 403. Wherein the center of the gate 403 is the geometric center of the surface of the gate 403.
In the test structure of the MOS transistor provided in the embodiment of the present invention, the source 401, the drain 402, and the gate 403 of the MOS transistor are respectively connected to two test electrodes, where one test electrode is used as a driving electrode and the other test electrode is used as an induction electrode. When testing the resistance of the MOS transistor, a driving voltage is applied to the source 401, the drain 402, and the gate 403 through the first driving electrode FS, the second driving electrode FD, and the third driving electrode SG, and a voltage of the source 401, the drain 402, and the gate 403 is sensed through the first sensing electrode SS, the second sensing electrode SD, and the third sensing electrode SG. Because the driving and the testing are separately performed, no large current flows through the first sensing electrode SS, the second sensing electrode SD and the third sensing electrode SG, the influence of the parasitic resistance of the testing electrode and the parasitic resistance of the conductive plug on the testing result is eliminated, and the accuracy of testing the resistance of the MOS transistor is improved.
How to test the resistance of the MOS transistor using the test structure of the MOS transistor of the present embodiment is described in detail below. Fig. 7 is a schematic flow chart of testing the source-drain series resistance Rm of the MOS transistor according to the embodiment of the present invention. Referring to fig. 7, the testing of the source-drain series resistance Rm of the MOS transistor includes:
step S11: a source voltage Vs is applied to the first driving electrode FS, a drain voltage Vd is applied to the second driving electrode FD, and a gate voltage Vg is applied to the third driving electrode FG. Typically, the source voltage Vs applied to the first driving electrode FS is 0V.
Step S12: and testing the potential of the first sensing electrode SS, the potential of the second sensing electrode SD and the potential of the third sensing electrode SG to obtain a gate-source voltage Vgs and a drain-source voltage Vds, and testing the current flowing from the second driving electrode FD to the first driving electrode FS to obtain a drain current Id. Specifically, when the potential of the first sensing electrode SS, the potential of the second sensing electrode SD, and the potential of the third sensing electrode SG are tested, a measuring instrument with high input impedance is adopted, no large current flows through the first sensing electrode SS, the second sensing electrode SD, the third sensing electrode SG, the second conductive plugs (T21 to T24), the fourth conductive plugs (T21 to T24), and the sixth conductive plug T6, the potential of the first sensing electrode SS is the potential of the source 401, the potential of the second sensing electrode SD is the potential of the drain 402, and the potential of the third sensing electrode SG is the potential of the gate 403. Therefore, the gate-source voltage Vgs is equal to the potential of the third sensing electrode SG minus the potential of the first sensing electrode SS, and the drain-source voltage Vds is equal to the potential of the second sensing electrode SG minus the potential of the first sensing electrode SS.
Steps S11 and S12 are voltage and current obtaining steps adapted to obtain a gate-source voltage Vgs, a drain-source voltage Vds, and a drain current Id of the MOS transistor.
Step S13: and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance Rm of the MOS transistor is equal to the drain-source voltage Vds in comparison with the drain current Id. It should be noted that, according to the characteristics of the MOS transistor, the resistance value of the source-drain series resistor Rm varies with the voltage value of the gate voltage Vg, that is, the gate voltage Vg with different voltage values is applied, and the obtained resistance values of the source-drain series resistor Rm are also different.
The test structure of the MOS transistor of the embodiment can also be used for testing the transfer characteristic curve and the output characteristic curve of the MOS transistor. Specifically, testing the transfer characteristic curve and the output characteristic curve of the MOS transistor includes:
changing the voltage values of the source voltage Vs, the drain voltage Vd and the gate voltage Vg, repeatedly executing the voltage and current obtaining steps, namely repeatedly executing the steps S11 and S12, and obtaining drain current Id with different current values and gate-source voltage Vgs and drain-source voltage Vds with different voltage values. Obtaining a transfer characteristic curve of the MOS transistor according to the drain current Id with different current values and the corresponding gate-source voltage Vgs with different voltage values, and obtaining an output characteristic curve of the MOS transistor according to the drain current Id with different current values and the corresponding drain voltage Vds with different voltage values. A person skilled in the art knows how to obtain the transfer characteristic curve of the MOS transistor according to the drain current Id with different current values and the gate-source voltage Vgs with different voltage values corresponding to the drain current Id, and also knows how to obtain the output characteristic curve of the MOS transistor according to the drain current Id with different current values and the drain-source voltage Vds with different voltage values corresponding to the drain current Id with different current values, which is not described herein again.
The channel parasitic resistance Rch can also be tested by adopting the test structure of the MOS transistor of the embodiment. Specifically, testing the channel parasitic resistance Rch of the MOS transistor includes:
the distance d2 from the second conductive plugs (T21-T24) to the grid 403 and the distance d4 from the fourth conductive plugs (T41-T44) to the grid 403 are both adjustable distances d 0.
And executing a resistance obtaining step to obtain a source-drain series resistance Rm of the MOS transistor. The resistance obtaining step includes: applying a source voltage Vs to the first driving electrode FS, a drain voltage Vd to the second driving electrode FD, and a gate voltage Vg to the third driving electrode FG; testing the potential of the first sensing electrode SS and the potential of the second sensing electrode SD to obtain a drain-source voltage Vds, and testing the FS current flowing from the second driving electrode FD to the first driving electrode to obtain a drain current Id; and obtaining the source-drain series resistance Rm of the MOS transistor according to the fact that the source-drain series resistance Rm of the MOS transistor is equal to the drain-source voltage Vds in comparison with the drain current Id. The resistance obtaining step is similar to the steps S11 to S13, and the detailed operations can refer to the description of the steps S11 to S13, which are not repeated herein.
Changing the distance value of the adjustable distance d0, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance Rm of the MOS transistor changing along with the adjustable distance d 0. Specifically, referring to fig. 8, a two-dimensional coordinate system is established with the X axis as the adjustable distance d0 and the Y axis as the source-drain series resistance Rm of the MOS transistor; discrete points are made in the two-dimensional coordinate system according to different distance values of the adjustable distance d0 and the resistance value of the source-drain series resistance Rm of the MOS transistor corresponding to the different distance values; and performing linear fitting on the discrete points to obtain a characteristic curve L11 of the source-drain series resistance Rm of the MOS transistor changing along with the adjustable distance d 0.
There are various ways to linearly fit the discrete points, the simplest one is to determine a straight line between two points, and thus the characteristic curve L11 can be obtained by repeating the resistance obtaining step once. The number of times of repeatedly performing the resistance obtaining step may be determined according to actual requirements, and the more the number of times of repetition is, the more discrete points are obtained, and the more accurate the obtained characteristic curve L11 is.
Since the distance d2 from the second conductive plug (T21-T24) to the gate 403 and the distance d4 from the fourth conductive plug (T41-T44) to the gate 403 are equal to the adjustable distance d0, the resistance values of the source parasitic resistance Rs and the drain parasitic resistance Rd are equal. Thus: rm is Rch +2 × Rs, where Rm is a resistance value of a source-drain series resistance Rm of the MOS transistor, Rch is a resistance value of the channel parasitic resistance Rch, and Rs is a resistance value of the source parasitic resistance Rs, that is, a resistance value of the drain parasitic resistance Rd.
The source parasitic resistance Rs varies in a linear relationship with the adjustable distance d0, thus: rm is rch +2 k x, k being the slope value of the characteristic L11 and x being the distance value of the adjustable distance d 0. When the distance value x of the adjustable distance d0 is 0, the source-drain series resistance Rm of the MOS transistor is equal to the channel parasitic resistance Rch, and therefore the resistance value Rch of the channel parasitic resistance Rch is a vertical coordinate value corresponding to the intersection point of the characteristic curve L11 and the Y axis.
The minimum source parasitic resistance of the MOS transistor can be tested by using the test structure of the MOS transistor of this embodiment, and the minimum source parasitic resistance of the MOS transistor refers to the source parasitic resistance Rs when the distance from the second conductive plug (T21-T24) to the gate 403 is the minimum safety distance. The minimum safety distance is the minimum distance for keeping insulation between two conductors, i.e. the minimum distance for keeping the second conductive plug (T21-T24) insulated from the gate 403. Specifically, testing the minimum source parasitic resistance of the MOS transistor includes:
the distance from the second conductive plugs (T21-T24) to the grid 403 is set as a minimum safety distance, and the distance from the fourth conductive plugs (T41-T44) to the grid 403 is set as an adjustable distance d 0.
And executing a resistance obtaining step to obtain a source-drain series resistance Rm of the MOS transistor. The resistance obtaining step includes: applying a source voltage Vs to the first driving electrode FS, a drain voltage Vd to the second driving electrode FD, and a gate voltage Vg to the third driving electrode FG; testing the potential of the first sensing electrode SS and the potential of the second sensing electrode SD to obtain a drain-source voltage Vds, and testing the FS current flowing from the second driving electrode FD to the first driving electrode to obtain a drain current Id; and obtaining the source-drain series resistance Rm of the MOS transistor according to the fact that the source-drain series resistance Rm of the MOS transistor is equal to the drain-source voltage Vds in comparison with the drain current Id. The resistance obtaining step is similar to the steps S11 to S13, and the detailed operations can refer to the description of the steps S11 to S13, which are not repeated herein.
Changing the distance value of the adjustable distance d0, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance Rm of the MOS transistor changing along with the adjustable distance d 0. Specifically, referring to fig. 9, a two-dimensional coordinate system is established with the X axis as the adjustable distance d0 and the Y axis as the source-drain series resistance Rm of the MOS transistor; discrete points are made in the two-dimensional coordinate system according to different distance values of the adjustable distance d0 and the resistance value of the source-drain series resistance Rm of the MOS transistor corresponding to the different distance values; and performing linear fitting on the discrete points to obtain a characteristic curve L12 of the source-drain series resistance Rm of the MOS transistor changing along with the adjustable distance. The specific method for obtaining the characteristic curve L12 is similar to the method for obtaining the characteristic curve L11, and is not repeated here.
Since the distance from the second conductive plugs (T21-T24) to the gate 403 is the minimum safety distance, the distance from the fourth conductive plugs (T41-T44) to the gate 403 is the adjustable distance d0, the resistance value of the source parasitic resistor Rs is fixed, and the resistance value of the drain parasitic resistor Rd varies with the adjustable distance d0, therefore: and Rm is Rch + rsm + Rd, where Rm is a resistance value of a source-drain series resistance Rm of the MOS transistor, Rch is a resistance value of the channel parasitic resistance Rch, rsm is a resistance value of the minimum source parasitic resistance, and Rd is a resistance value of the drain parasitic resistance Rd.
The drain parasitic resistance Rd varies in a linear relationship with the adjustable distance d0, thus: rm is rch + rsm + k x, k is the slope value of the characteristic curve L12, x is the distance value of the adjustable distance d 0. When the distance value x of the adjustable distance d0 is 0, the source-drain series resistance Rm of the MOS transistor is equal to the channel parasitic resistance Rch plus the minimum source parasitic resistance, and therefore the resistance value Rch of the channel parasitic resistance Rch plus the resistance value rsm of the minimum source parasitic resistance is a vertical coordinate value corresponding to the intersection point of the characteristic curve L12 and the Y axis. The resistance value Rch of the channel parasitic resistance Rch can be obtained according to the foregoing embodiment, and therefore, the resistance value rsm of the minimum source resistance can be obtained by the test method provided by this embodiment.
Based on the same principle as the test of the minimum source parasitic resistance of the MOS transistor, the test structure of the MOS transistor according to this embodiment may further test the minimum drain parasitic resistance of the MOS transistor, where the minimum drain parasitic resistance of the MOS transistor refers to the drain parasitic resistance Rd when the distance from the fourth conductive plug (T41-T44) to the gate 403 is the minimum safe distance. The minimum safety distance is the minimum distance for keeping insulation between two conductors, i.e. the minimum distance for keeping the fourth conductive plug (T41-T44) insulated from the gate 403. Specifically, the testing of the minimum source-drain parasitic resistance of the MOS transistor includes:
setting the distance from the fourth conductive plugs (T41-T44) to the grid 403 to be a minimum safety distance, and setting the distance from the second conductive plugs (T21-T24) to the grid 403 to be an adjustable distance d 0.
And executing a resistance obtaining step to obtain a source-drain series resistance Rm of the MOS transistor. The resistance obtaining step includes: applying a source voltage Vs to the first driving electrode FS, a drain voltage Vd to the second driving electrode FD, and a gate voltage Vg to the third driving electrode FG; testing the potential of the first sensing electrode SS and the potential of the second sensing electrode SD to obtain a drain-source voltage Vds, and testing the FS current flowing from the second driving electrode FD to the first driving electrode to obtain a drain current Id; and obtaining the source-drain series resistance Rm of the MOS transistor according to the fact that the source-drain series resistance Rm of the MOS transistor is equal to the drain-source voltage Vds in comparison with the drain current Id. The resistance obtaining step is similar to the steps S11 to S13, and the detailed operations can refer to the description of the steps S11 to S13, which are not repeated herein.
Changing the distance value of the adjustable distance d0, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance Rm of the MOS transistor changing along with the adjustable distance d 0. Specifically, referring to fig. 10, a two-dimensional coordinate system is established with the X axis as the adjustable distance and the Y axis as the source-drain series resistance Rm of the MOS transistor; discrete points are made in the two-dimensional coordinate system according to different distance values of the adjustable distance d0 and the resistance value of the source-drain series resistance Rm of the MOS transistor corresponding to the different distance values; and performing linear fitting on the discrete points to obtain a characteristic curve L13 of the source-drain series resistance Rm of the MOS transistor changing along with the adjustable distance. The specific method for obtaining the characteristic curve L13 is similar to the method for obtaining the characteristic curve L11, and is not repeated here.
Since the distance from the fourth conductive plugs (T41-T44) to the gate 403 is the minimum safety distance, the distances from the second conductive plugs (T21-T24) to the gate 403 are all adjustable distances d0, the resistance value of the drain parasitic resistance Rs is fixed, and the resistance value of the source parasitic resistance Rs varies with the adjustable distance d0, therefore: rm is Rch + rdm + Rs, where Rm is the resistance of the source-drain series resistance Rm of the MOS transistor, Rch is the resistance of the channel parasitic resistance Rch, rdm is the resistance of the minimum drain parasitic resistance, and Rs is the resistance of the source parasitic resistance Rs.
The source parasitic resistance Rs varies in a linear relationship with the adjustable distance d0, thus: rm is rch + rdm + k x, k being the slope value of the characteristic L13 and x being the distance value of the adjustable distance d 0. When the distance value x of the adjustable distance d0 is 0, the source-drain series resistance Rm of the MOS transistor is equal to the channel parasitic resistance Rch plus the minimum drain parasitic resistance, and therefore, the resistance value Rch of the channel parasitic resistance Rch plus the resistance value rdm of the minimum drain parasitic resistance is a vertical coordinate value corresponding to the intersection point of the characteristic curve L13 and the Y axis. The resistance Rch of the channel parasitic resistance Rch can be obtained according to the previous embodiments, and therefore, the resistance rdm of the minimum drain resistance can be obtained by the test method provided by the present embodiment.
Fig. 11 to fig. 13 are a schematic cross-sectional structure diagram, a schematic layout diagram, and a schematic perspective structure diagram of another MOS transistor and its test structure according to an embodiment of the present invention. Referring to fig. 11 to 13, the MOS transistor includes: a substrate 400; a source 401 and a drain 402 within the substrate 400; a gate 403 over the substrate 400. And the source-drain series resistance Rm of the MOS transistor is the sum of the source parasitic resistance Rs, the drain parasitic resistance Rd and the channel parasitic resistance Rch.
The test structure of the MOS transistor includes a first driving electrode FS, a first sensing electrode SS, a second driving electrode FD, a second sensing electrode SD, a third driving electrode FG, a third sensing electrode SG, a fourth sensing electrode SS ', and a fifth sensing electrode SD'. Wherein the first driving electrode FS is connected to the source electrode 401 through a first conductive plug (T11-T14); the first sensing electrode SS is connected to the source electrode 401 through a second conductive plug (T21-T24); the second driving electrode FD is connected to the drain electrode 402 through a fourth conductive plug (T41-T44); the second sensing electrode SD is connected to the drain 402 through a third conductive plug (T31-T34); the third driving electrode FG is connected to the gate 403 through a fifth conductive plug T5; the third sensing electrode SG is connected to the gate electrode 403 through a sixth conductive plug T6.
The specific structures of the first driving electrode FS, the first sensing electrode SS, the second driving electrode FD, the second sensing electrode SD, the third driving electrode FG, the third sensing electrode SG and each conductive plug may refer to the description of the embodiment corresponding to fig. 4 to 6, and are not described herein again. The fourth sensing electrode SS 'is connected to the first driving electrode FS, and the fifth sensing electrode SD' is connected to the second driving electrode FD.
The sum of the parasitic resistances of the first conductive plugs (T11 to T14) and the parasitic resistances of the third conductive plugs (T31 to T34) can be tested by using the test structure of the MOS transistor of the present embodiment. Specifically, testing the sum of the parasitic resistance of the first conductive plugs (T11-T14) and the parasitic resistance of the third conductive plugs (T31-T34) includes:
a source voltage Vs is applied to the first driving electrode FS, a drain voltage Vd is applied to the second driving electrode FD, and a gate voltage Vg is applied to the third driving electrode FG.
The potential of the first sensing electrode SS, the potential of the second sensing electrode SD, the potential of the fourth sensing electrode SS ', and the potential of the fifth sensing electrode SD' are tested to obtain a first drain-source voltage Vds1 and a second drain-source voltage Vds2, and the current flowing from the second driving electrode FD to the first driving electrode FS is tested to obtain a drain electrode Id. Wherein the first drain-source voltage Vds1 is equal to the potential of the second sensing electrode SD minus the potential of the first sensing electrode SS, and the second drain-source voltage Vds2 is equal to the potential of the fifth sensing electrode SD 'minus the potential of the fourth sensing electrode SS'. The first drain-source voltage Vds1 is a voltage between the drain 402 and the source 401, and the second drain-source voltage Vds2 is a sum of a voltage between the drain 402 and the source 401, a voltage of the first conductive plugs (T11 to T14), and a voltage of the third conductive plugs (T31 to T34).
And obtaining the source-drain series resistance Rm of the MOS transistor according to the fact that the source-drain series resistance Rm of the MOS transistor is equal to the first drain-source voltage Vds1 and is larger than the drain current Id. And obtaining the sum of the parasitic resistance of the first conductive plugs (T11-T14) and the parasitic resistance of the third conductive plugs (T31-T34) according to the fact that the sum of the source-drain series resistance Rm of the MOS transistor, the parasitic resistance of the first conductive plugs (T11-T14) and the parasitic resistance of the third conductive plugs (T31-T34) is equal to the ratio of the second drain-source voltage Vds2 to the drain current Id.
In the present embodiment, the parasitic resistances of the first conductive plugs (T11 to T14) and the third conductive plugs (T31 to T34) are equal in number, and thus the parasitic resistance of each conductive plug can be obtained according to the sum of the parasitic resistances of the first conductive plugs (T11 to T14) and the parasitic resistances of the third conductive plugs (T31 to T34).
In summary, the test structure and the test method of the MOS transistor provided by the present invention eliminate the influence of the parasitic resistance of the test electrode and the parasitic resistance of the conductive plug on the test result, and improve the accuracy of testing the resistance of the MOS transistor.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A test structure of a MOS transistor, the MOS transistor comprising a substrate, a source, a drain and a gate, the test structure of the MOS transistor comprising:
a first driving electrode connected to the source electrode through a first conductive plug;
the first induction electrode is connected to the source electrode through a second conductive plug;
a second driving electrode connected to the drain electrode through a third conductive plug;
the second induction electrode is connected to the drain electrode through a fourth conductive plug;
a third driving electrode connected to the gate electrode through a fifth conductive plug;
the third induction electrode is connected to the grid electrode through a sixth conductive plug;
the distance from the second conductive plug to the grid electrode and the distance from the fourth conductive plug to the grid electrode are adjustable; or,
one of the second conductive plug and the fourth conductive plug is arranged at a minimum safety distance from the grid electrode, and the other conductive plug is arranged at an adjustable distance from the grid electrode.
2. The test structure of the MOS transistor according to claim 1, wherein the number of the first conductive plugs, the number of the second conductive plugs, the number of the third conductive plugs, and the number of the fourth conductive plugs are each at least two; each first conductive plug is equidistant from the grid; each second conductive plug is equidistant from the grid; each third conductive plug is equidistant from the grid; and the distance from each fourth conductive plug to the grid is equal.
3. The test structure of the MOS transistor of claim 1 or 2, wherein a distance from the first conductive plug to the gate is greater than a distance from the second conductive plug to the gate, and a distance from the third conductive plug to the gate is greater than a distance from the fourth conductive plug to the gate.
4. The test structure of the MOS transistor according to claim 1, wherein a connection end of the fifth conductive plug to the gate and a connection end of the sixth conductive plug to the gate are located on a same side of the gate.
5. The test structure of the MOS transistor according to claim 4, wherein a distance from a connection end of the fifth conductive plug to the gate to a center of the gate is larger than a distance from a connection end of the sixth conductive plug to the gate to the center of the gate.
6. The test structure of the MOS transistor of claim 1, further comprising a fourth sense electrode and a fifth sense electrode; the fourth sensing electrode is connected to the first driving electrode, and the fifth sensing electrode is connected to the second driving electrode.
7. A method for testing a MOS transistor based on the test structure of the MOS transistor according to any one of claims 1 to 5, comprising:
executing a voltage and current obtaining step to obtain a gate-source voltage, a drain-source voltage and a drain current of the MOS transistor;
wherein the voltage and current obtaining step comprises:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
and testing the potential of the first sensing electrode, the potential of the second sensing electrode and the potential of the third sensing electrode to obtain the gate-source voltage and the drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain the drain current.
8. The method for testing an MOS transistor according to claim 7, further comprising: and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
9. The method for testing an MOS transistor according to claim 7, further comprising: and changing the voltage values of the source voltage, the drain voltage and the gate voltage, and repeatedly executing the voltage and current obtaining step to obtain a transfer characteristic curve and an output characteristic curve of the MOS transistor.
10. A method for testing a MOS transistor based on the test structure of the MOS transistor according to any one of claims 1 to 5, comprising:
setting the distance from the second conductive plug to the grid and the distance from the fourth conductive plug to the grid to be adjustable distances;
executing a resistance obtaining step to obtain a source-drain series resistance of the MOS transistor;
changing the distance value of the adjustable distance, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance of the MOS transistor along with the change of the adjustable distance;
according to a characteristic curve that the source-drain series resistance of the MOS transistor changes along with the adjustable distance, the channel parasitic resistance of the MOS transistor is equal to the source-drain series resistance of the corresponding MOS transistor when the distance value of the adjustable distance is zero;
wherein the resistance obtaining step includes:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode and the potential of the second sensing electrode to obtain drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain drain current;
and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
11. The method for testing the MOS transistor according to claim 10, wherein the obtaining of the characteristic curve of the source-drain series resistance of the MOS transistor, which varies with the adjustable distance, includes:
establishing a two-dimensional coordinate system by taking the X axis as the adjustable distance and the Y axis as the source-drain series resistance of the MOS transistor;
discrete points are made in the two-dimensional coordinate system according to different distance values of the adjustable distance and the resistance values of the source-drain series resistors of the MOS transistors corresponding to the different distance values;
and performing linear fitting on the discrete points to obtain a characteristic curve of the source-drain series resistance of the MOS transistor changing along with the adjustable distance.
12. A method for testing a MOS transistor based on the test structure of the MOS transistor according to any one of claims 1 to 5, comprising:
setting the distance from the second conductive plug to the grid electrode as a minimum safety distance, and setting the distance from the fourth conductive plug to the grid electrode as an adjustable distance;
executing a resistance obtaining step to obtain a source-drain series resistance of the MOS transistor;
changing the distance value of the adjustable distance, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance of the MOS transistor along with the change of the adjustable distance;
according to a characteristic curve that the source-drain series resistance of the MOS transistor changes along with the adjustable distance, the sum of the minimum source parasitic resistance and the channel parasitic resistance of the MOS transistor is equal to the source-drain series resistance of the corresponding MOS transistor when the distance value of the adjustable distance is zero;
wherein the resistance obtaining step includes:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode and the potential of the second sensing electrode to obtain drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain drain current;
and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
13. The method for testing the MOS transistor according to claim 12, wherein the obtaining of the characteristic curve of the source-drain series resistance of the MOS transistor, which varies with the adjustable distance, includes:
establishing a two-dimensional coordinate system by taking the X axis as the adjustable distance and the Y axis as the source-drain series resistance of the MOS transistor;
discrete points are made in the two-dimensional coordinate system according to different distance values of the adjustable distance and the resistance values of the source-drain series resistors of the MOS transistors corresponding to the different distance values;
and performing linear fitting on the discrete points to obtain a characteristic curve of the source-drain series resistance of the MOS transistor changing along with the adjustable distance.
14. A method for testing a MOS transistor based on the test structure of the MOS transistor according to any one of claims 1 to 5, comprising:
setting the distance from the fourth conductive plug to the grid electrode as a minimum safety distance, and setting the distance from the second conductive plug to the grid electrode as an adjustable distance;
executing a resistance obtaining step to obtain a source-drain series resistance of the MOS transistor;
changing the distance value of the adjustable distance, and repeatedly executing the resistance obtaining step to obtain a characteristic curve of the source-drain series resistance of the MOS transistor along with the change of the adjustable distance;
according to a characteristic curve that the source-drain series resistance of the MOS transistor changes along with the adjustable distance, the sum of the minimum drain parasitic resistance and the channel parasitic resistance of the MOS transistor is equal to the source-drain series resistance of the corresponding MOS transistor when the distance value of the adjustable distance is zero;
wherein the resistance obtaining step includes:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode and the potential of the second sensing electrode to obtain drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain drain current;
and obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the drain-source voltage compared with the drain current.
15. The method for testing the MOS transistor according to claim 14, wherein the obtaining of the characteristic curve of the source-drain series resistance of the MOS transistor, which varies with the adjustable distance, includes:
establishing a two-dimensional coordinate system by taking the X axis as the adjustable distance and the Y axis as the source-drain series resistance of the MOS transistor;
discrete points are made in the two-dimensional coordinate system according to different distance values of the adjustable distance and the resistance values of the source-drain series resistors of the MOS transistors corresponding to the different distance values;
and performing linear fitting on the discrete points to obtain a characteristic curve of the source-drain series resistance of the MOS transistor changing along with the adjustable distance.
16. A method for testing a MOS transistor, based on the MOS transistor testing structure of claim 6, comprising:
applying a source voltage to the first driving electrode, a drain voltage to the second driving electrode, and a gate voltage to the third driving electrode;
testing the potential of the first sensing electrode, the potential of the second sensing electrode, the potential of the fourth sensing electrode and the potential of the fifth sensing electrode to obtain a first drain-source voltage and a second drain-source voltage, and testing the current flowing from the second driving electrode to the first driving electrode to obtain a drain current, wherein the first drain-source voltage is equal to the potential of the second sensing electrode minus the potential of the first sensing electrode, and the second drain-source voltage is equal to the potential of the fifth sensing electrode minus the potential of the fourth sensing electrode;
obtaining the source-drain series resistance of the MOS transistor according to the fact that the source-drain series resistance of the MOS transistor is equal to the first drain-source voltage compared with the drain current;
and obtaining the sum of the parasitic resistance of the first conductive plug and the parasitic resistance of the third conductive plug according to the fact that the sum of the source-drain series resistance of the MOS transistor, the parasitic resistance of the first conductive plug and the parasitic resistance of the third conductive plug is equal to the ratio of the second drain-source voltage to the drain current.
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