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CN104795397B - Storage unit, memory and its layout structure - Google Patents

Storage unit, memory and its layout structure Download PDF

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Publication number
CN104795397B
CN104795397B CN201410027725.XA CN201410027725A CN104795397B CN 104795397 B CN104795397 B CN 104795397B CN 201410027725 A CN201410027725 A CN 201410027725A CN 104795397 B CN104795397 B CN 104795397B
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Prior art keywords
schottky
memory
schottky diode
fuse element
contact electrode
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CN104795397A (en
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甘正浩
黄威森
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

A kind of storage unit, memory and its layout structure, the storage unit include input terminal, fuse element and Schottky diode;The input terminal connects one end of the fuse element, and the other end of the fuse element connects the anode of the Schottky diode, the minus earth of the Schottky diode.Storage unit, memory and its layout structure that technical solution of the present invention provides, provide program current by Schottky diode for fuse element, improve the stability to fuse element programming.

Description

Storage unit, memory and its layout structure
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of storage unit, memory and its layout structure.
Background technique
Electric fuse(E-fuse)Technology is a kind of technology to be grown up according to polysilicon fuse characteristic.Electric fuse it is initial Resistance value very little, when there is high current by electric fuse, electric fuse is blown, resistance value multiplication.The electric fuse being blown will The electric fuse for for good and all remaining off, and not being blown is then still on state.Therefore, the storage being made of electric fuse Unit is to judge whether electric fuse is blown the data to learn its internal reservoir.
Fig. 1 is a kind of electrical block diagram of existing storage unit.With reference to Fig. 1, the storage unit includes input Hold Pad, fuse element F1 and transistor M1.The input terminal Pad connects one end of the fuse element F1 and is suitable for input the One program voltage;The other end of the fuse element F1 connects the drain electrode of the transistor M1;The grid of the transistor M1 Gate is suitable for the second program voltage of input, the source electrode ground connection of the transistor M1.
Before to storage unit programming, the fuse element F1 is not blown, resistance value very little.When to described defeated When entering to hold Pad to apply the first program voltage, apply the second program voltage to the grid G ate of the transistor M1, the transistor M1 conducting, has program current to flow through the fuse element F1, and the fuse element F1 is blown, and resistance value increases, realization pair The programming of the storage unit.If the program current is too small, the fuse element F1 can not be fused;If the program current It is too big, it is easy to damage the fuse element F1.Therefore, the program current current value need control a certain range it It is interior.The program current is the drain current of the transistor M1, by adjusting first program voltage and described second The voltage value of program voltage can change the current value of the program current.
Since the characteristics such as the carrier mobility of transistor and gap state are influenced by temperature, in grid voltage and source electrode When voltage is identical and temperature difference, the drain current of transistor is simultaneously unequal.Fig. 2 is gate source voltage-drain current of transistor Characteristic curve schematic diagram.With reference to Fig. 2, abscissa indicates the grid voltage of transistor and the voltage difference of source voltage(Abbreviation grid Source voltage), unit:Volt(V);Ordinate indicates the drain current of transistor, unit:Ampere(A);Discrete point curve in figure It is gate source voltage-drain current characteristic curve of the transistor when temperature is -40 DEG C, 25 DEG C and 125 DEG C respectively.From Fig. 2 As can be seen that the drain current of transistor be affected by temperature it is larger.
For storage unit shown in FIG. 1, since the drain current of the transistor M1 is influenced by temperature, institute It is not identical to state the program current of storage unit at different temperatures.Fig. 3 is temperature-program current spy of the storage unit Linearity curve schematic diagram.With reference to Fig. 3, abscissa indicates temperature, unit:Degree Celsius(℃);Ordinate indicates the storage unit Program current, unit:Ampere(A);Curve in figure indicates temperature-program current characteristic curve of the storage unit, point A, point b and point c respectively indicates the storage unit corresponding program current when temperature is -40 DEG C, 25 DEG C and 125 DEG C. In temperature from when being increased to 125 DEG C for -40 DEG C, the program current of the storage unit reduces about 44%, is affected by temperature very Greatly.
Summary of the invention
Being affected by temperature the invention solves the program current of existing storage unit leads to programming stability is low asks Topic.
To solve the above problems, the present invention provides a kind of storage unit, including input terminal, fuse element and Schottky two Pole pipe;The input terminal connects one end of the fuse element, and the other end of the fuse element connects two pole of Schottky The anode of pipe, the minus earth of the Schottky diode.
Optionally, the input terminal is suitable for input program voltage, the resistance of the program voltage and the fuse element and The forward conduction voltage of the Schottky diode is related.
Optionally, the forward conduction voltage of the Schottky diode is 0.57V to 0.7V.
Optionally, the forward conduction voltage of the Schottky diode is 0.6V.
Based on said memory cells, the present invention also provides a kind of memories, including several said memory cells.
Optionally, the memory includes:
P type substrate;
N-type well region in the P type substrate;
Several first N-doped zones in the N-type well region;
Several Ohm contact electrodes for respectively corresponding first N-doped zone in the N-type well region;
Several Schottky contact electrodes in the N-type well region, the Ohm contact electrode and the schottky junctions Touched electrode is alternatively arranged;
Positioned at the P type substrate surface, the insulating layer of the isolation Ohm contact electrode and the Schottky contact electrode.
Optionally, the memory further includes:
In the P type substrate, the P-doped zone of N-type well region periphery;
Positioned at the P type substrate surface, the ohmic contact regions of the corresponding P-doped zone.
Optionally, the memory further includes:
The second N-doped zone in the N-type well region;
In the N-type well region, the first metal layer of corresponding second N-doped zone.
Optionally, the Ohm contact electrode is tungsten or nickel, and the Schottky contact electrode is titanium, cobalt or nickel.
Optionally, the insulating layer is silicon nitride, silica or silicon oxynitride.
Based on said memory cells, the present invention also provides a kind of layout structures of memory, including by several above-mentioned storages The Schottky array that the Schottky diode of unit is constituted, the Schottky diode includes Ohm contact electrode and schottky junctions Touched electrode, Ohm contact electrode is alternatively arranged with Schottky contact electrode in the Schottky array.
Optionally, the layout structure of the memory further includes the Ohmic contact for being laid in the Schottky array periphery Area.
Optionally, the Schottky array further includes the first metal layer.
Optionally, the layout structure of the memory further includes being made of the fuse element of several storage units Array of fuses.
Compared with prior art, technical solution of the present invention has the following advantages that:
Storage unit provided by the invention includes fuse element and Schottky diode, and uses transistor in the prior art Program current difference is provided for fuse element, the present invention is that the Schottky diode is used to provide programming for the fuse element Electric current.It is identical in program voltage due to the characteristic that there is the Schottky diode forward bias current to be affected by temperature very little And when temperature difference, the program current that the Schottky diode provides is highly stable, improves and programs to the storage unit Stability.
In optinal plan of the invention, the forward conduction voltage of the Schottky diode is 0.57V to 0.7V.It is electric herein It presses in range, further improves the stability for the program current that the Schottky diode provides.
Based on storage unit provided by the invention, the present invention also provides a kind of memory and its layout structures.It is deposited described In reservoir and its layout structure, the Ohm contact electrode and Schottky contact electrode of the Schottky diode are alternatively arranged, and are subtracted The small series resistance of the Schottky diode, to effectively increase the current density of the Schottky diode.
Detailed description of the invention
Fig. 1 is a kind of electrical block diagram of existing storage unit;
Fig. 2 is gate source voltage-drain current characteristic curve schematic diagram of transistor;
Fig. 3 is temperature-program current characteristic curve schematic diagram of storage unit shown in FIG. 1;
Fig. 4 is the electrical block diagram of the storage unit of the embodiment of the present invention;
Fig. 5 is the characteristic curve schematic diagram that the electric current of Schottky diode varies with temperature;
Fig. 6 is the VA characteristic curve schematic diagram of Schottky diode;
Fig. 7 is the partial structure diagram of the memory of the embodiment of the present invention;
Fig. 8 is the partial schematic diagram of the layout structure of the memory of the embodiment of the present invention.
Specific embodiment
Just as described in the background art, the volume for the storage unit being made of in the prior art fuse element and transistor Journey electric current is unstable because being affected by temperature, and influences the programming to the storage unit.Technical solution of the present invention provides one kind and deposits Storage unit uses Schottky diode to provide stable program current for fuse element.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Fig. 4 is the electrical block diagram of the storage unit of the embodiment of the present invention.With reference to Fig. 4, the storage unit includes Input terminal Pad, fuse element F0 and Schottky diode D0.The input terminal Pad connects one end of the fuse element F0, The other end of the fuse element F0 connects the anode of the Schottky diode D0, and the cathode of the Schottky diode D0 connects Ground.
The input terminal Pad is suitable for input program voltage.Due to the fuse element F0 and the Schottky diode D0 Cascaded structure is constituted, therefore is had:Vp=Id*Rf+Vd, wherein Vp is the voltage value of the program voltage, and Id is the Schottky The current value of the current value of the forward bias current of diode D0 namely the program current of the storage unit, Rf are described molten The resistance value of the resistance of silk element F0, Vd are the voltage value of the forward conduction voltage of the Schottky diode D0.The storage The program current of unit is determined by the characteristic of the fuse element F0, after the fuse element F0 is selected, the program current Current value fix, therefore, the resistance and the Schottky diode D0 of the program voltage and the fuse element F0 are just To conducting voltage correlation.
The forward bias current of the Schottky diode D0 is also related with temperature:Id=Is*[exp(q*Vd/n*k*T)- 1], wherein Is is the current value of the reverse saturation current of the Schottky diode D0, and q is the unit quantity of electric charge, and n is ideal line Number, k is Boltzmann constant, and T is temperature value.The reverse saturation current of the Schottky diode D0 calculates according to the following formula:Is= A*A’*T2*exp(-ФB/k*T), wherein A is the area of the Schottky diode D0, and A ' is Richardson constant, ФB For the barrier value of the Schottky diode D0.
Fig. 5 is the characteristic curve schematic diagram that the electric current of the Schottky diode D0 varies with temperature.With reference to Fig. 5, horizontal seat Mark indicates temperature, unit:Kelvin(K);Ordinate indicates the electric current of the Schottky diode D0, unit:Ampere(A);Figure In curve L1 indicate the forward current of the Schottky diode D0 than the upper Schottky diode D0 reversed saturation electricity The curve that stream varies with temperature, the i.e. corresponding ordinate value of curve L1 are exp(q*Vd/n*k*T)- 1, the curve L2 in figure is indicated The curve that the reverse saturation current of the Schottky diode D0 varies with temperature, the i.e. corresponding ordinate value of curve L2 are A* A’*T2*exp(-ФB/k*T), the curve L3 in figure indicates that the forward current of the Schottky diode D0, i.e. curve L3 are corresponding Ordinate value be A*A ' * T2*exp(-ФB/k*T)*[exp(q*Vd/n*k*T)-1].From fig. 5, it can be seen that curve L1 is indicated Electric current and the negatively correlated variation of temperature, the electric current and temperature that curve L2 is indicated are positively correlated variation, and curve L3 is curve L1 With the product of curve L2, therefore, the electric current that curve L3 is indicated varies with temperature very little.
Fig. 6 is the VA characteristic curve schematic diagram of the Schottky diode D0.With reference to Fig. 6, abscissa indicates Xiao The forward conduction voltage of special based diode D0, unit:Volt(V);Ordinate indicates the forward bias of the Schottky diode D0 Set electric current, unit:Ampere(A);Diamond shape in figure(◆)It is -40 DEG C that discrete point curve, which is the Schottky diode D0 in temperature, When VA characteristic curve, the square in figure(■)Discrete point curve is the Schottky diode D0 when temperature is 25 DEG C VA characteristic curve, the triangle in figure(▲)Discrete point curve is the Schottky diode D0 when temperature is 125 DEG C VA characteristic curve.From fig. 6, it can be seen that the forward bias current of the Schottky diode D0 is affected by temperature very It is small.Especially in the range of the forward conduction voltage of the Schottky diode D0 is in 0.57V to 0.7V, in different temperatures Under, the forward bias current of the Schottky diode D0 is almost equal, therefore, can be by institute when programming to the storage unit The forward conduction voltage for stating Schottky diode D0 is set as 0.57V to 0.7V, preferably 0.6V.
Storage unit provided by the invention provides programming electricity by the Schottky diode D0 for the fuse element F0 Stream is identical in program voltage due to the characteristic that there is the Schottky diode D0 forward bias current to be affected by temperature very little And when temperature difference, the program current that the Schottky diode D0 is provided is highly stable, improves and compiles to the storage unit The stability of journey.
The present invention also provides a kind of memory, the memory includes several storage units, the circuit of the storage unit Structure can be as shown in Figure 4.In the memory, the structure and Schottky two of the fuse element in several storage units The structure of pole pipe can be arranged independently of each other, and the embodiment of the present invention provides two pole of Schottky in one kind several storage units Pipe uses the memory of interconnection structure.
Fig. 7 is the partial structure diagram of the memory of the embodiment of the present invention.With reference to Fig. 7, the memory includes:P-type Substrate 70;N-type well region 71 in the P type substrate 70;Several first N-doped zones in the N-type well region 71, In the present embodiment, with 4 the first N-doped zones(First N-doped zone, 721 to the first N-doped zone 724)For said It is bright;Several Ohm contact electrodes for respectively corresponding first N-doped zone in the N-type well region 71(Ohmic contact Electrode 731 is to Ohm contact electrode 734), the Ohm contact electrode and first N-doped zone correspond, i.e., and one Corresponding first N-doped zone of the Ohm contact electrode;Several Schottky contacts in the N-type well region 71 Electrode(Schottky contact electrode 741 is to Schottky contact electrode 744), the Ohm contact electrode and the schottky junctions are got an electric shock Pole is alternatively arranged;Positioned at the exhausted of 70 surface of P type substrate, the isolation Ohm contact electrode and the Schottky contact electrode Edge layer.
Cathode of the Ohm contact electrode as the Schottky diode can be tungsten or nickel;The schottky junctions Anode of the touched electrode as the Schottky diode can be titanium, cobalt or nickel;The insulating layer can be silicon nitride, oxidation Silicon or silicon oxynitride.
In the embodiment of the present invention, the Ohm contact electrode is alternatively arranged with the Schottky contact electrode, shortens institute The distance between Ohm contact electrode and the Schottky contact electrode are stated, therefore, the series resistance of the Schottky diode (Series resistance Rs1 to series resistance Rs4)Reduce, increases the current density of the Schottky diode.
With continued reference to Fig. 7, the memory further includes in the P type substrate 70, the P of 71 periphery of the N-type well region Type doped region 75 and positioned at 70 surface of P type substrate, the ohmic contact regions 76 of the corresponding P-doped zone 75, the Europe Nurse contact zone 76 and the ohmic contact resistance 73 are also by the insulator separation.The ohmic contact regions 76 are suitable for will be described P type substrate 70 is connect with other circuit structures, is usually grounded the P type substrate 70.
The memory further includes the second N-doped zone 77 in the N-type well region 71 and is located at the N-type trap In area 71, the first metal layer 78 of corresponding second N-doped zone 77, a metal layer 78 gets an electric shock with the schottky junctions A between pole 47 and metal layer 78 and the ohmic contact regions are also by the insulator separation.The first metal layer 78 are suitable for for the N-type well region 71 connecting with other circuit structures.
The present invention also provides a kind of layout structure of memory, Fig. 8 is the layout structure of the memory of the embodiment of the present invention Partial schematic diagram.With reference to Fig. 8, the layout structure of the memory includes Schottky array 81 and array of fuses(It is not shown), The Schottky array 81 is made of the Schottky diode in several storage units as shown in Figure 4, the array of fuses by Fuse element in several storage units as shown in Figure 4 is constituted.
The Schottky diode includes Ohm contact electrode and Schottky contact electrode, and the Ohm contact electrode is institute The cathode of diode is stated, the Schottky contact electrode is the anode of the diode.In the Schottky array 81 of the present embodiment In, Ohm contact electrode(Ohm contact electrode 831 is to Ohm contact electrode 834)With Schottky contact electrode(Schottky contacts Electrode 841 is to Schottky contact electrode 844)It is alternatively arranged.The embodiment of the present invention is by by the Ohm contact electrode and Xiao Te Base contacts electrode gap arrangement, shortens the distance between the Ohm contact electrode and Schottky contact electrode, therefore, described The series resistance of Schottky diode reduces, and improves the current density of the Schottky diode.The layout of the memory Structure further includes being laid in the ohmic contact regions 86 of 81 periphery of Schottky array, and the Schottky array 81 further includes first Metal layer 88.
In conclusion storage unit, memory and its layout structure that technical solution of the present invention provides, pass through Schottky two Pole pipe provides for fuse element is affected by temperature minimum program current, improves the stability to fuse element programming.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (15)

1. a kind of memory, which is characterized in that including several storage units, the storage unit includes input terminal, fuse element And Schottky diode;The input terminal connects one end of the fuse element, and the other end of the fuse element connects institute State the anode of Schottky diode, the minus earth of the Schottky diode;Schottky two in several storage units Pole pipe includes:
P type substrate;
N-type well region in the P type substrate;
Several first N-doped zones in the N-type well region;
Several Ohm contact electrodes for respectively corresponding first N-doped zone in the N-type well region;
Several Schottky contact electrodes in the N-type well region, the Ohm contact electrode and the schottky junctions are got an electric shock Pole is alternatively arranged;
Positioned at the P type substrate surface, the insulating layer of the isolation Ohm contact electrode and the Schottky contact electrode;
The Ohm contact electrode is the cathode of Schottky diode;
The Schottky contact electrode is the anode of Schottky diode.
2. memory as described in claim 1, which is characterized in that further include:
In the P type substrate, the P-doped zone of N-type well region periphery;
Positioned at the P type substrate surface, the ohmic contact regions of the corresponding P-doped zone.
3. memory as described in claim 1, which is characterized in that further include:
The second N-doped zone in the N-type well region;
In the N-type well region, the first metal layer of corresponding second N-doped zone.
4. memory as described in claim 1, which is characterized in that the Ohm contact electrode is tungsten or nickel, the Schottky Contact electrode is titanium, cobalt or nickel.
5. memory as described in claim 1, which is characterized in that the insulating layer is silicon nitride, silica or silicon oxynitride.
6. memory as described in claim 1, which is characterized in that the input terminal is suitable for input program voltage, the programming Voltage is related to the forward conduction voltage of the resistance of the fuse element and the Schottky diode.
7. memory as described in claim 1, which is characterized in that the forward conduction voltage of the Schottky diode is 0.57V to 0.7V.
8. memory as claimed in claim 7, which is characterized in that the forward conduction voltage of the Schottky diode is 0.6V。
9. a kind of layout structure of memory, which is characterized in that including what is be made of the Schottky diode of several storage units Schottky array, the storage unit include input terminal, fuse element and Schottky diode;Described in the input terminal connection One end of fuse element, the other end of the fuse element connect the anode of the Schottky diode, two pole of Schottky The minus earth of pipe;The Schottky diode includes Ohm contact electrode and Schottky contact electrode, the Schottky array Middle Ohm contact electrode is alternatively arranged with Schottky contact electrode.
10. the layout structure of memory as claimed in claim 9, which is characterized in that further include being laid in the Schottky battle array Arrange the ohmic contact regions of periphery.
11. the layout structure of memory as claimed in claim 9, which is characterized in that the Schottky array further includes first Metal layer.
12. the layout structure of memory as claimed in claim 9, which is characterized in that further include by several storage lists The array of fuses that the fuse element of member is constituted.
13. the layout structure of memory as claimed in claim 9, which is characterized in that the input terminal is suitable for input programming electricity Pressure, the program voltage are related to the forward conduction voltage of the resistance of the fuse element and the Schottky diode.
14. the layout structure of memory as claimed in claim 9, which is characterized in that the positive guide of the Schottky diode The pressure that is powered is 0.57V to 0.7V.
15. the layout structure of memory as claimed in claim 14, which is characterized in that the positive guide of the Schottky diode The pressure that is powered is 0.6V.
CN201410027725.XA 2014-01-21 2014-01-21 Storage unit, memory and its layout structure Active CN104795397B (en)

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CN111161782A (en) * 2019-11-22 2020-05-15 浙江大学 Novel anti-fuse unit

Citations (2)

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CN1450561A (en) * 2002-04-09 2003-10-22 惠普公司 Non-volatile, multi-level memory device
TW201023345A (en) * 2008-12-11 2010-06-16 Macronix Int Co Ltd Aluminum copper oxide based memory devices and methods for manufacture

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JP2004319587A (en) * 2003-04-11 2004-11-11 Sharp Corp Memory cell, memory, and method of manufacturing memory cell
CN100391002C (en) * 2005-03-29 2008-05-28 旺宏电子股份有限公司 One time programmable read only memory and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1450561A (en) * 2002-04-09 2003-10-22 惠普公司 Non-volatile, multi-level memory device
TW201023345A (en) * 2008-12-11 2010-06-16 Macronix Int Co Ltd Aluminum copper oxide based memory devices and methods for manufacture

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