CN104779959A - Conversion device with offset value added and method - Google Patents
Conversion device with offset value added and method Download PDFInfo
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- CN104779959A CN104779959A CN201410010335.1A CN201410010335A CN104779959A CN 104779959 A CN104779959 A CN 104779959A CN 201410010335 A CN201410010335 A CN 201410010335A CN 104779959 A CN104779959 A CN 104779959A
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Abstract
The invention discloses a conversion device with an offset value added and a method. The conversion device comprises a switch circuit, a first capacitor, multiple additional capacitor units and an operational amplifier, wherein the switch circuit comprises multiple switches; the first capacitor is used for storing a first charge value according to switching of the switch circuit; the multiple additional capacitor units comprise a first multiple additional capacitor unit with a capacitance difference and a second additional capacitor unit for respectively storing a second charge value and a third charge value with different polar sizes according to switching of the switch circuit; the operational amplifier generates a DC bias according to the first charge value; the DC bias comprises a DC offset value; and the operational amplifier generates a reverse-phase DC offset value according to the difference between the second charge value and the third charge value to compensate the DC offset value.
Description
Technical field
The present invention relates to a kind of electronic installation; Particularly, a kind of D/A conversion device and analog/digital conversion device of additional offset value is related to
Background technology
The skew (offset) of general circuit signal often causes many problems.Such as in voice applications, the direct current offset (DC offset) that voicefrequency circuit exports often causes people's ear to hear plosive (pop-noise).This direct current offset of current solution causes plosive method, is to add single anti-phase direct current offset to reduce this direct current offset, but because of technique and environment variation and have it to limit.
Said method can be applicable to analog/digital converter (Analog-to-Digital Converter, ADC) and digital/analog converter (Digital-to-Analog Converter, DAC), but direct current offset or plosive elimination still limited.Adopt the analog/digital converter 100a of switching capacity (switch-cap) form as shown in Figure 1A.Analog/digital converter 100a includes primary Ioops filter (Loop Filter) 100a1, N position quantizer (N-bit Quantizer) 100a2, a N position internal digital/analog converter (N-bit Internal DAC) 100a3.Said method also can be applicable to the digital/analog converter 100b of employing switching capacity (switch-cap) form as shown in Figure 1B.Digital/analog converter 100b includes an operational amplifier 100b1, paired electric capacity C1 and C2, paired switch S 1, S2, S3, S4.
For existing three increment accumulations (Three bits Sigma-Delta DAC) digital/analog converter explanation.Please refer to Figure 1B, Fig. 2 A, as shown in Figure 2 A, the electric capacity C1 of digital/analog converter 100b includes seven capacitor cell (Cell)-capacitor cells 1 ~ 7.These seven capacitor cells 1 ~ 7 determine to provide reference voltage VRP or negative reference voltage VRN to capacitor cell 1 ~ 7, to produce eight kinds of corresponding different conditions according to the numerical value 000,001,010,011,100,101,110,111 of the input code of three.When digital/analog converter 100b is according to frequency signal CK1 and CK2 diverter switch S1, S2, S3, S4, eight numerical value of digital/analog converter 100b foundation digital code can produce the charge value of following eight kinds of sizes:
（+1 +1 +1 +1 +1 +1 +1）*（C1/C2） =>+7*（C1/C2）
（+1 +1 +1 +1 +1 +1 -1）*（C1/C2） =>+5*（C1/C2）
（+1 +1 +1 +1 +1 -1 -1）*（C1/C2） =>+3*（C1/C2）
（+1 +1 +1 +1 -1 -1 -1）*（C1/C2） =>+1*（C1/C2）
（+1 +1 +1 -1 -1 -1 -1）*（C1/C2） =>-1*（C1/C2）
（+1 +1 -1 -1 -1 -1 -1）*（C1/C2） =>-3*（C1/C2）
（+1 -1 -1 -1 -1 -1 -1）*（C1/C2） =>-5*（C1/C2）
（-1 -1 -1 -1 -1 -1 -1）*（C1/C2） =>-7*（C1/C2）
For charge value (+1+1+1-1-1-1-1) * (C1/C2)=>-1*(C1/C2) illustrate.Suppose reference voltage VRP for+1V, negative reference voltage VRN be-1V.Then, charge value-1*(C1/C2) allow capacitor cell 7,6,5 receive reference voltage VRP according to input code 100 and obtain numerical value+1(white circle), and allow capacitor cell 4,3,2,1 receive negative reference voltage VRN and to obtain numerical value-1(black circle).Therefore, can obtain charge value is (+1+1+1-1-1-1-1) * (C1/C2)=-1*(C1/C2), if hypothesis C1=C2, then can obtain charge value and equal-1.The rest may be inferred for the charge value that other input codes obtain.Mode according to this, can produce by operational amplifier 100b1 direct current (DC) bias Vop or the Von that charge value is+7 ,+5 ,+3 ,+1 ,-1 ,-3 ,-5 ,-7.
But, may because process drift, environmental modification or the factor such as asymmetric between the electric capacity of general digital/analog converter or analog/digital converter, cause electric capacity that size occurs each other and do not mate phenomenon (capacitor mismatch) and the direct current offset that causes direct current (DC) bias Vop or Von.As shown in Figure 2 B, suppose that capacitor cell 7 does not mate with the capacitance size of other capacitor cells 1 ~ 6.As shown in the drawing, the capacitance actual size of such as capacitor cell 7 is solid line circle place; The dotted line circle place of capacitor cell 7 is then used for representing the size when capacitance of capacitor cell 7 mates with other capacitor cells.Prior art at this moment, a single minimum electric capacity can be adopted, capacitor cell 0 as shown in Figure 2 B, attempt the electric capacity vacancy (difference in areas of dotted line and solid line) filling up capacitor cell 7, do not mate caused direct current offset (DC offset) to produce a minimum single anti-phase DC offset value to the capacitance eliminating capacitor cell 7.But often because the drift of technique, and accurately cannot predict and produce this minimum capacitance (or variation value of capacitor cell).Therefore prior art still cannot solve the DC offset problem of D/A conversion device and analog/digital conversion device.
Summary of the invention
For the problems referred to above, one of object of embodiment of the present invention is providing a kind of conversion equipment that can add the opposite phase shift value of multiple default size.
For the problems referred to above, one of object of embodiment of the present invention is providing a kind of conversion equipment utilizing the difference of multiple additional capacitor unit to produce the opposite phase shift value presetting size, to compensate the DC offset value that conversion equipment produces.
The conversion equipment of embodiment of the present invention can be D/A conversion device or the analog/digital conversion device of a trigonometric integral kenel.
According to one embodiment of the present invention, provide a kind of conversion equipment.Conversion equipment includes a switching circuit, one first electric capacity, multiple additional capacitor unit and an operational amplifier.Switching circuit, includes multiple switch.First electric capacity is in order to store one first charge value according to the switching of switching circuit.Multiple additional capacitor unit comprises the one first additional capacitor unit and one second additional capacitor unit with a capacitive differential, in order to store one second charge value and a tricharged value that polarity varies in size respectively according to the switching of switching circuit.Operational amplifier produces a direct current (DC) bias according to the first charge value, and direct current (DC) bias includes a DC offset value, and operational amplifier also produces an anti-phase DC offset value, with compensating DC offset value according to the difference of the second charge value and tricharged.
According to another embodiment of the present invention, provide a kind of conversion equipment, include an operational amplifier, one first electric capacity, one first additional capacitor unit, one second additional capacitor unit.Operational amplifier is in order to produce a direct current (DC) bias.First electric capacity, includes multiple first capacitor cell, and in order to produce one first charge value, the first charge value has a charge error value, and wherein at least one first capacitor cell has a capacitance error value, and charge error value is relevant with capacitance error value.First additional capacitor unit is in order to store a positive charge values.Second additional capacitor unit is in order to store a negative electricity charge values, and wherein positive charge values and negative electricity charge values have a charge difference.Wherein, operational amplifier produces direct current (DC) bias according to the first charge value, positive charge values, negative electricity charge values, and charge difference is in order to compensation charge error amount.
According to another embodiment of the present invention, provide a kind of method compensating conversion equipment deviant, include the following step: first, provide a switching circuit, it comprises multiple switch.Utilize one first capacitance stores one first charge value to produce a direct current (DC) bias according to the switching of switching circuit, wherein the first electric capacity includes multiple first capacitor cell, direct current (DC) bias includes a DC offset value, and DC offset value produces owing to not mating between multiple first capacitor cell.Compensating DC offset value is carried out according to the switching of switching circuit and the capacitive differential between one first additional capacitor unit and one second additional capacitor unit.
The conversion equipment of embodiment of the present invention and method, the difference between multiple additional capacitor unit is utilized to produce the combination of multiple minimum opposite phase shift value, to produce the DC offset value compensating circuit direct bias voltage originally, and the unmatched problem of prior art conversion equipment electric capacity can be solved.
Accompanying drawing explanation
Figure 1A shows the schematic diagram of the analog/digital converter of existing employing switching capacity (switch-cap) form.
Figure 1B shows the schematic diagram of the digital/analog converter of existing employing switching capacity (switch-cap) form.
Fig. 2 A shows the schematic diagram of the capacitor array of existing digital/analog converter electric capacity.
Fig. 2 B shows another schematic diagram of the capacitor array of existing digital/analog converter electric capacity.
Fig. 3 A shows a kind of schematic diagram adding the conversion equipment of deviant of an embodiment of the present invention.
The conversion equipment that Fig. 3 B shows an embodiment of the present invention is the operating state figure of the execution mode of a D/A conversion device.
The conversion equipment that Fig. 3 C shows another execution mode of the present invention is the operating state figure of the execution mode of a D/A conversion device.
The conversion equipment that Fig. 4 A shows an embodiment of the present invention is the operating state figure of the execution mode of an analog/digital conversion device.
Fig. 4 B shows the schematic diagram of an equivalent electric circuit of an embodiment of the present invention Fig. 4 A conversion equipment.
Fig. 4 C shows the schematic diagram of an equivalent electric circuit of an embodiment of the present invention Fig. 4 A conversion equipment.
The conversion equipment that Fig. 5 A shows an embodiment of the present invention is the operating state figure of the execution mode of an analog/digital conversion device.
Fig. 5 B shows the schematic diagram of an equivalent electric circuit of an embodiment of the present invention Fig. 5 A conversion equipment.
Fig. 5 C shows the schematic diagram of an equivalent electric circuit of an embodiment of the present invention Fig. 5 A conversion equipment.
Fig. 6 A shows first capacitor cell of an embodiment of the present invention and the schematic diagram of additional capacitor unit.
Fig. 6 B shows the first capacitor cell of another execution mode of the present invention and the schematic diagram of additional capacitor unit.
6C figure shows the first capacitor cell of another execution mode of the present invention and the schematic diagram of additional capacitor unit.
Fig. 7 shows a kind of deviant that provides of an embodiment of the present invention in the flow chart of the method for conversion equipment.
Embodiment
Fig. 3 A shows a kind of schematic diagram adding the conversion equipment 300 of deviant of an embodiment of the present invention.The conversion equipment 300 of present embodiment can be a D/A conversion device (Digital to Analog Converter, DAC).Conversion equipment 300 includes operational amplifier 301, an a 1 first switched-capacitor circuit 302a and second switch condenser network 302b.
Multiple switch S 1 ~ S8, one first electric capacity C1(that first switched-capacitor circuit 302a includes formation one switching circuit can be a sampling capacitor), one second electric capacity C2(can be a holding capacitor) and multiple additional capacitor unit C0a, C0b.Second switch condenser network 302b also includes multiple switch S 1 ~ S8, one first electric capacity C1, one second electric capacity C2 and multiple additional capacitor unit C0a, C0b.Wherein, the first additional capacitor unit C0a is the capacitor cell of a storage positive charge, and the second additional capacitor unit C0b is the capacitor cell of a storage negative electrical charge.
Operational amplifier 301 comprises the output of at least one direct current (DC) bias Vop or Von in order to produce, and due to the first electric capacity C1 may because technique drift, environmental modification or the factor such as asymmetric cause it to have capacitance error value, therefore the direct current (DC) bias Vop that produces according to the first electric capacity C1 and the second electric capacity C2 of operational amplifier 301 or Von also has a DC offset value (DC offset).As the example of this figure, the first switched-capacitor circuit 302a and second switch condenser network 302b couples in-phase input end and the inverting input of operational amplifier 301 respectively.Operational amplifier 301 in-phase input end and inverting input receive two charge values that the first switched-capacitor circuit 302a and second switch condenser network 302b provides respectively, produce direct current (DC) bias Vop and Von.
Because the first switched-capacitor circuit 302a is identical with operation principles with the structure of second switch condenser network 302b, only illustrate with single-ended (Single end) circuit of the first switched-capacitor circuit 302a therefore.
The control conducting (On) of multiple switch S 1 ~ S8 breaker in middle S1, S2, S6 and S8 foundation first frequency signal CK1 or disconnection (Off); And the control of switch S 3, S4, S5 and S7 foundation second frequency signal CK2 is turned on or off.The first end of switch S 1 couples reference voltage VRP or negative reference voltage VRN, and the second end couples the first end of switch S 3 and the first end of the first electric capacity C1.The first end of switch S 2 couples a low voltage level (as ground connection GND), and the second end couples second end of the first electric capacity C1 and the first end of switch S 4, forms a first node A.Second end of switch S 3 couples the first end of switch S 5 and the first end of switch S 7, forms a Section Point B.Second end of switch S 4 couples the first end of the second electric capacity C2 and the in-phase input end of operational amplifier 301.The first end of the first additional capacitor unit C0a couples the first end of first node A and the second additional capacitor unit C0b, and second end of the first additional capacitor unit C0a couples the first end of switch S 6 and the second end of switch S 5.Second end of switch S 6 couples reference voltage VRP.Second end of switch S 7 couples second end of the second additional capacitor unit C0b and the first end of switch S 8.Second end of switch S 8 couples negative reference voltage VRN.
First electric capacity C1 includes multiple first capacitor cell, and an execution mode please refer to seven capacitor cells (Capacitor cell) 1 ~ 7 that the first electric capacity C1 shown in Fig. 6 A comprises.Certainly, this is only example, the present invention is not limited thereto, and also can be the electric capacity of other kenels, number.Wherein, in electric capacity C1, at least one first capacitor cell may because the environmental factors such as technique drift have a capacitance error value, as the capacitor cell 7 of Fig. 6 A.Should be noted, the capacitance error value of the capacitor cell 7 shown in Fig. 6 A ~ Fig. 6 C is only example, and the size of its error size is not limited thereto, and is also not limited to only capacitor cell 7 and has capacitance error value, also can occur in other capacitor cells.And when operating, the first electric capacity C1 and the second electric capacity C2 produces according to reference voltage VRP or negative reference voltage VRN the first charge value that has a charge error value.
Multiple additional capacitor unit C0, this additional capacitor unit C0 each varies in size, and has a capacitive differential of a preset ratio between additional capacitor unit C0.As the example of Fig. 3 A, the first additional capacitor unit C0a is the capacitor cell of a storage positive charge, receives reference voltage VRP to store a positive charge values.Second additional capacitor unit C0b is the capacitor cell of a storage negative electrical charge, receives negative reference voltage VRN to store a negative electricity charge values.And there is between the first additional capacitor unit C0a and one second additional capacitor unit C0b a capacitive differential delta, capacitive differential delta is in order to as a building-out capacitor value (Capacitor offset).Suppose that reference voltage VRP and negative reference voltage VRN is respectively+1V and-1V, and produce a positive charge (the second charge value) when the first additional capacitor unit C0a receives reference voltage VRP, when second additional capacitor unit C0b reception negative reference voltage VRN produces a negative electrical charge (tricharged value), because additional capacitor unit C0a and C0b has the cause of capacitive differential delta, the positive charge values of generation and this negative electricity charge values have a charge difference.And operational amplifier 301 will produce an opposite phase shift value according to this charge difference, in order to compensated operational amplifier 301 because the DC offset value that causes of the capacitance error value of the first electric capacity C1.
One execution mode, please refer to Fig. 3 A, Fig. 3 B, Fig. 3 C.Fig. 3 B, Fig. 3 C show the operating state figure of conversion equipment 300.The operating state of the conversion equipment 300 of present embodiment illustrates with the function mode of single-ended (Single end), those skilled in the art should obtain the function mode of conversion equipment 300 differential (Differential) according to explanation herein, therefore repeat no more.During running, the switch S 1 of Fig. 3 A, S2, S6, S8 foundation first frequency signal CK1 conducting (On), switch S 3, S4, S5, S7 disconnect (Off) according to second frequency signal CK2, and now the first switched-capacitor circuit 302a divides into left and right two parts circuit, as shown in Figure 3 B.Positive and negative reference voltage VRP or VRN charges to the first electric capacity C1, and reference voltage VRP charges to the first additional capacitor unit C0a, negative reference voltage VRN charges to the second additional capacitor unit C0b.Then, as shown in Figure 3 C, in switch S 1, S2, S6, S8 foundation first frequency signal CK1 disconnection of switched-capacitor circuit 302a, when switch S 3, S4, S5, S7 are according to second frequency signal CK2 conducting, first electric capacity C1, the first additional capacitor unit C0a, the second additional capacitor unit C0b the second electric capacity C2 in parallel, make the electric charge of the first electric capacity C1, the first additional capacitor unit C0a, the second additional capacitor unit C0b be provided to output node, produce direct current (DC) bias with the output at amplifier 301.
The schematic diagram of the conversion equipment 400 of another execution mode of Fig. 4 A the present invention.Conversion equipment 400 is an analog/digital conversion device (ADC).The conversion equipment 400 of present embodiment is one single-ended (Single end) conversion equipment, and those skilled in the art should obtain the conversion equipment of differential (Differential end) according to explanation herein, therefore repeat no more its details.
Conversion equipment 400 includes operational amplifier 401 and a switched-capacitor circuit 402.Switched-capacitor circuit 402 includes multiple switch S 1 ~ S8, the one first electric capacity C1 of formation one switching circuit, one second electric capacity C2 and multiple additional capacitor unit C0a, C0b.Wherein, the first additional capacitor unit C0a is the capacitor cell of a storage plus or minus electric charge, and the second additional capacitor unit C0b is the capacitor cell of a storage negative or positive electric charge.The coupling mode of said modules as shown in the figure, repeats no more.
Fig. 4 B, Fig. 4 C show the operating state figure that conversion equipment 400 is the execution mode of an analog/digital conversion device.In Fig. 4 B, when the switched-capacitor circuit 402 of analog/digital conversion device 400 switches, the switch S 2 of switched-capacitor circuit 402, S3, S5, S7 is according to first frequency signal CK1 conducting, switch S 1, S4, S6, S8 disconnects according to second frequency signal CK2, now left and right two parts circuit divided into by conversion equipment 400, for for purpose of brevity as the first electric capacity C1, first additional capacitor unit C0a and the second additional capacitor unit C0b all represents with C, shown in the accompanying drawing of drawing left, the circuit of the first electric capacity C1 receives input voltage Vi to charge, the circuit of the first additional capacitor unit C0a and the circuit of the second additional capacitor unit C0b are that receiver voltage Vcm charges.Wherein, voltage Vcm is charge conversion reference voltage or common mode (Common mode) voltage.And as shown in Figure 4 C, when the switched-capacitor circuit 402 of analog/digital conversion device switches, switch S 2, S3, S5, S7 of switched-capacitor circuit 402 disconnect according to first frequency signal CK1, switch S 1, S4, S6, S8 are according to second frequency signal CK2 conducting, electric capacity C1, the first additional capacitor unit C0a, the second additional capacitor unit C0b receive reference voltage VRP or negative reference voltage VRN, store the first charge value, the second charge value and a tricharged value respectively to store.If wherein the first additional capacitor unit C0a is when receiving reference voltage VRP, the second charge value be on the occasion of, and the second additional capacitor unit C0b reception negative reference voltage VRN, tricharged value is negative value, and vice versa.
Fig. 5 A is the schematic diagram of the conversion equipment 500 of another execution mode of the present invention.Conversion equipment 400 is an analog/digital conversion device (ADC).The conversion equipment 500 of present embodiment is one single-ended (Single end) conversion equipment, and those skilled in the art should obtain the conversion equipment of differential (Differential end) according to explanation herein, therefore repeat no more its details.
Conversion equipment 500 includes operational amplifier 501 and a switched-capacitor circuit 502.Switched-capacitor circuit 502 includes multiple switch S 1 ~ S8, the one first electric capacity C1 of formation one switching circuit, one second electric capacity C2 and multiple additional capacitor unit C0a, C0b.Wherein, the first additional capacitor unit C0a is the capacitor cell of a storage plus or minus electric charge, and the second additional capacitor unit C0b is the capacitor cell of a storage negative or positive electric charge.The coupling mode of said modules as shown in the figure, repeats no more.
Fig. 5 B, Fig. 5 C show the operating state figure that conversion equipment 500 is the execution mode of an analog/digital conversion device.The switched-capacitor circuit 502 of the analog/digital conversion device 500 of Fig. 5 B, Fig. 5 C is roughly the same with the mode that the analog/digital conversion device 400 of Fig. 4 B, Fig. 4 C carries out switching, difference is that switch S 2 changes into and is controlled by second frequency signal CK2, switch S 4 changes into and being controlled by first frequency CK1, and makes Fig. 5 B, Fig. 5 C and Fig. 4 B, Fig. 4 C reverse.Its Detailed Operation mode and technical characteristic, those skilled in the art should be pushed away by above-mentioned explanation, repeats no more.
Below describe the first electric capacity C1 of embodiment of the present invention, the second electric capacity C2 in detail, the first additional capacitor unit C0a, the second additional capacitor unit C0b receive reference voltage VRP or negative reference voltage VRN, store the first charge value, the second charge value and a tricharged value respectively, utilize the capacitive differential that the 2nd tricharged value is subtracted each other, compensate the charge error value of the first charge value, reach and produce the function mode that reverse biased value complement repays the DC offset value of direct current (DC) bias.In embodiment of the present invention, an example of the first electric capacity C1 can be the capacitor array of 3 <6:0>, as shown in Figure 6A.Certainly, the present invention is not limited thereto, also can be the electric capacity of other kenels or figure place size.
Multiple additional capacitor unit C0a, C0b of embodiment of the present invention a part couples reference voltage VRP, another part additional capacitor couples VRN.As shown in Figure 6A, in this figure, the size value of arbitrary capacitor cell 1 ~ 7 of the corresponding first electric capacity C1 of the first additional capacitor unit C0a is 100%; And the size value of arbitrary capacitor cell 1 ~ 7 of the corresponding first electric capacity C1 of the second additional capacitor unit C0b is 99%, utilize the difference of two capacitor cell C0a and C0b can obtain minimum capacitive differential delta(or delta*C1), as 1%*C1.And when switched-capacitor circuit switches, the first capacitance X of the first additional capacitor unit C0a and the second capacitance Y of the second additional capacitor unit C0b is multiplied by reference voltage VRP(respectively and is assumed to be+1V) be assumed to be-1V with negative reference voltage VRN() and the voltage difference X-Y that subtracts each other can be obtained, this voltage difference is opposite phase shift value, X-Y=X*VRP+Y*VRN, wherein | X-Y|=capacitive differential <1, VRP=+1, VRN=-1.Should be noted, above-mentioned numerical value is only example, the present invention is not limited thereto.Then, when operating, after the first electric capacity C1 of the execution mode conversion equipment 300 of Fig. 6 A and the selection of the second electric capacity C2 foundation input code, the selection of seven the first capacitor cells foundation input codes is multiplied by reference voltage VRP or negative reference voltage VRN again in conjunction with the second electric capacity C2, and add first, second additional capacitor C0a, C0b and be multiplied by reference voltage VRP and negative reference voltage VRN respectively, the total charge that one includes an opposite phase shift value can be obtained, as follows:
（+1 +1 +1 +1 +1 +1 +1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（+7+delta）*（C1/C2）；
（+1 +1 +1 +1 +1 +1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（+5+delta）*（C1/C2）；
（+1 +1 +1 +1 +1 -1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（+3+delta）*（C1/C2）；
（+1 +1 +1 +1 -1 -1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（+1+delta）*（C1/C2）；
（+1 +1 +1 -1 -1 -1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（-1+delta）*（C1/C2）；
（+1 +1 -1 -1 -1 -1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（-3+delta）*（C1/C2）；
（+1 -1 -1 -1 -1 -1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（-5+delta）*（C1/C2）；
（-1 -1 -1 -1 -1 -1 -1）*（C1/C2）+（+1 -1+delta）*（C1/C2） =>（-7+delta）*（C1/C2）。
Mode according to this, can obtain total capacitance value has (+7+delta), (+5+delta), (+3+delta), (+1+delta), (-1+delta), (-3+delta), (-5+delta), (-7+delta) respectively.Wherein delta is determined by first, second additional capacitor unit C0a and C0b, such as, when the size 99% that the size of the first additional capacitor unit C0a and the first electric capacity C1 is the 100%, second additional capacitor unit C0b and the first electric capacity C1.For (+1+1+1+1+1+1+1) * (C1/C2)+(+1-1+delta) * (C1/C2)=>(+7+delta) * (C1/C2) illustrates.First, the first additional capacitor unit C0a is+1, can obtain the ratio 100% with the first capacitance size; And the second additional capacitor unit C0b is-1+delta, the ratio 99% with the first capacitance size can be obtained.In Fig. 6 A, the blank dotted line circle Dab of the second additional capacitor unit C0b represents-1, and the solid line circle Byb after reducing is-1+delta, and the solid line circle Byb after therefore reducing and the difference of dotted line circle Dab are default capacitive differential delta; And the first capacitor cell C0a is+1, as in Fig. 6 A, the circle Bya filling up hatching of the first capacitor cell C0a is+1.Then, when input code is 111, the first capacitor cell 1 ~ 7 is multiplied by reference voltage and makes the electric charge of each first capacitor cell 1 ~ 7 storage be all+1, therefore, when switched-capacitor circuit 302a operates, the total charge of (+7+delta) * (C1/C2) can be produced.Utilize this total charge (+7+delta) * (C1/C2) that direct current (DC) bias Vop or the Von that includes opposite phase shift value can be obtained, the error utilizing opposite phase shift value to carry out compensating DC offset value to cause, solve the problem of prior art.
Below illustrate the various ratio setting meanss of the capacitive differential delta that first, second additional capacitor unit C0a and C0b of embodiment of the present invention determines.
One execution mode, as shown in Figure 6B, invariably (mismatch) problem is mated between all capacitor cells of the first electric capacity C1, now do not need compensation offset value, the capacitance of first, second additional capacitor unit C0a and C0b can be set as formed objects, namely the capacitance of the first additional capacitor unit C0a equals the capacitance of arbitrary capacitor cell of the first electric capacity C1, and the capacitance of the second additional capacitor unit C0b also equals the capacitance of arbitrary capacitor cell of the first electric capacity C1.Now the first capacitance X of the first additional capacitor unit C0a and the second capacitance Y of the second additional capacitor unit C0b is multiplied by reference voltage VRP(respectively and is assumed to be+1V) be assumed to be-1V with negative reference voltage VRN() and the voltage difference X-Y=0 that subtracts each other can be obtained, equal zero to obtain opposite phase shift value.
One execution mode, as shown in Figure 6 C, the value of the first additional capacitor unit C0a equals the value+capacitive differential delta of arbitrary capacitor cell of the first electric capacity C1, equals solid line circle place Bya after dotted line circle place Daa+delta as shown in the drawing; And the value of the second additional capacitor unit C0b equals the value of arbitrary capacitor cell of the first electric capacity C1, solid line circle Byb place as shown in the drawing.When switched-capacitor circuit switches, the first capacitance X of the first additional capacitor unit C0a is multiplied by reference voltage VRP(and is assumed to be+1V) equal+1+delta, and the second capacitance Y of the second additional capacitor unit C0b is multiplied by negative reference voltage VRN(is assumed to be-1V) equal-1, and the voltage difference X-Y that subtracts each other can be obtained, be opposite phase shift value (+1+delta)-1=delta.After conversion equipment adds opposite phase shift value, operational amplifier, according to the control of input code, can produce the multiple total charge including opposite phase shift value, as follows:
（+1 +1 +1 +1 +1 +1 +1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（+7+delta）*（C1/C2）；
（+1 +1 +1 +1 +1 +1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（+5+delta）*（C1/C2）；
（+1 +1 +1 +1 +1 -1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（+3+delta）*（C1/C2）；
（+1 +1 +1 +1 -1 -1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（+1+delta）*（C1/C2）；
（+1 +1 +1 -1 -1 -1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（-1+delta）*（C1/C2）；
（+1 +1 -1 -1 -1 -1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（-3+delta）*（C1/C2）；
（+1 -1 -1 -1 -1 -1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（-5+delta）*（C1/C2）；
（-1 -1 -1 -1 -1 -1 -1）*（C1/C2）+（+1+delta -1）*（C1/C2） =>（-7+delta）*（C1/C2）。
In another execution mode, the number of the additional capacitor unit of embodiment of the present invention is not limited to two additional capacitor unit, and can be above-mentioned multiple, be such as six, then electric capacity deviant can be:
[（+1）+（-1+delta1）+（1+delta2）+（-1+delta3）+（1+delta4）+（-1+delta5）]*C1
=（delta1+delta2+delta3+delta4+delta5）*C1。
Furthermore, the deviant that the various combination of capacitive differential (delta1 ~ delta5) that electric capacity deviant or opposite phase shift value can be between multiple additional capacitor unit produces.One execution mode, the mode of compensating DC offset value can carry out compensating DC offset value according to the capacitive differential between the multiple ratio value between arbitrary capacitor cell of the switching of switching circuit and multiple additional capacitor unit and the first electric capacity C1 or multiple additional capacitor unit.Multiple ratio value can be, such as, one first ratio value of arbitrary capacitor cell of one first additional capacitor unit C0a and the first electric capacity C1, one second ratio value of this arbitrary capacitor cell of one second additional capacitor unit C0b and the first electric capacity C1, one the 3rd additional capacitor unit C0c(are not shown) with one the 3rd ratio value of this arbitrary capacitor cell of the first electric capacity C1.Should be noted that the number of additional capacitor unit can adjust according to demand.
Should be noted, the value of above-mentioned reference voltage VRP and negative reference voltage VRN can be other numerical value, is not limited to above-mentioned+1 and-1.And the ratio of additional capacitor unit also can adjust arbitrarily according to demand, as being preset as the size of arbitrary capacitor cell of the first electric capacity C1 of 102% and 98%, and be not limited to the size setting ratio according to the first electric capacity.
Fig. 7 shows a kind of deviant that provides of an embodiment of the present invention in the method for conversion equipment, includes the following step:
Step S702: start.
Step S704: provide a switching circuit, it comprises multiple switch.
Step S706: utilize one first capacitance stores one first charge value to produce a direct current (DC) bias according to the switching of switching circuit, wherein the first electric capacity includes multiple first capacitor cell, direct current (DC) bias includes a DC offset value, and DC offset value produces owing to not mating between multiple first capacitor cell.
Step S708: carry out compensating DC offset value according to the switching of switching circuit and the capacitive differential between one first additional capacitor unit and one second additional capacitor unit.
Step S710: terminate.
In sum, the conversion equipment of embodiment of the present invention, utilize the capacitive differential between multiple additional capacitor unit to produce multiple minimum opposite phase shift value, to produce the reverse compensation deviant compensating circuit direct bias voltage originally, and the unmatched problem of prior art conversion equipment electric capacity can be solved.
Though the present invention is described with execution mode above, therefore do not limit scope of the present invention, only otherwise depart from main idea of the present invention, the various distortion that these those skilled in the art carry out or change and all fall into claim of the present invention.
[symbol description]
100a, 100b, 300,300a, 300b conversion equipment
100a1 loop filter
100a2 quantizer
100a3 transducer
100b1,301 amplifiers
302a, 302b circuit
302a1,302b1 additional capacitor unit
302a2,302b2 switched-capacitor circuit
C0a, C0b, C1, C2 electric capacity
Claims (12)
1. a conversion equipment, includes:
One switching circuit, includes multiple switch;
One first electric capacity, in order to store one first charge value according to the switching of described switching circuit;
Multiple additional capacitor unit, comprises the one first additional capacitor unit and one second additional capacitor unit with a capacitive differential, in order to store one second charge value and a tricharged value that polarity varies in size respectively according to the switching of described switching circuit; And
One operational amplifier, a direct current (DC) bias is produced according to described first charge value, described direct current (DC) bias includes a DC offset value, and described operational amplifier also produces an anti-phase DC offset value, to compensate described DC offset value according to the difference of described second charge value and described tricharged.
2. device according to claim 1, wherein, described first electric capacity includes multiple first capacitor cell, wherein, the capacitance of described first additional capacitor unit is less than the capacitance of described first capacitor cell, and the capacitance of described second additional capacitor unit is not less than the capacitance of described first capacitor cell.
3. device according to claim 1, wherein, described first electric capacity includes multiple first capacitor cell, and described DC offset value produces owing to not mating between described multiple first capacitor cell.
4. device according to claim 1, wherein, described in one, described in the first additional capacitor unit and, the first capacitor cell has one first ratio value, and first capacitor cell described in second extra cell and has one second ratio value described in one, described operational amplifier compensates described DC offset value according to the difference of described first ratio value and described second ratio value.
5. a conversion equipment, includes:
One operational amplifier, in order to produce a direct current (DC) bias;
One first electric capacity, includes multiple first capacitor cell, in order to produce one first charge value, described first charge value has a charge error value, wherein, at least one described first capacitor cell has a capacitance error value, and described charge error value is relevant with described capacitance error value;
One first additional capacitor unit, in order to store a positive charge values;
One second additional capacitor unit, in order to store a negative electricity charge values, wherein, described positive charge values and described negative electricity charge values have a charge difference; And
Wherein, described operational amplifier produces described direct current (DC) bias according to described first charge value, described positive charge values, described negative electricity charge values, and described charge difference is in order to compensate described charge error value.
6. device according to claim 5, also comprise multiple switch, described multiple switch is in order to carry out discharge and recharge according to the first electric capacity, described first additional capacitor unit and described second additional capacitor unit described in a first frequency signal and a second frequency signal switching.
7. device according to claim 5, wherein, described first additional capacitor unit and described second additional capacitor unit have a capacitive differential, and described operational amplifier compensates described charge error value according to described capacitive differential.
8. device according to claim 5, wherein, described in described first additional capacitor unit and, the first capacitor cell has one first ratio value, described in described second additional capacitor unit and, the first capacitor cell has one second ratio value, described first ratio value and described second ratio value vary in size, and described operational amplifier compensates described charge error value according to the difference of described first ratio value and described second ratio value.
9. compensate a method for conversion equipment deviant, comprise:
There is provided a switching circuit, it comprises multiple switch;
Utilize one first capacitance stores one first charge value to produce a direct current (DC) bias according to the switching of described switching circuit, wherein, described first electric capacity includes multiple first capacitor cell, described direct current (DC) bias includes a DC offset value, and described DC offset value produces owing to not mating between described multiple first capacitor cell; And
Described DC offset value is compensated according to the switching of described switching circuit and the capacitive differential between one first additional capacitor unit and one second additional capacitor unit
10. method according to claim 9, wherein, the capacitance of described first additional capacitor unit is greater than the capacitance of described first capacitor cell, and the capacitance of described second additional capacitor unit is not more than the capacitance of described first capacitor cell.
11. methods according to claim 9, wherein, described in described first additional capacitor unit and, the first capacitor cell has one first ratio value, and described in described second additional capacitor unit and, first capacitor cell has one second ratio value, and the step compensating described DC offset value comprises:
Difference according to described first ratio value and described second ratio value compensates described DC offset value.
12. methods according to claim 11, wherein, the step compensating described DC offset value also comprises:
One the 3rd ratio value according to the switching of described switching circuit and one the 3rd additional capacitor unit and between the first capacitor cell compensates described DC offset value.
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| CN107452417A (en) * | 2016-06-01 | 2017-12-08 | 瑞昱半导体股份有限公司 | Data processing circuit and data processing method |
| CN107889004A (en) * | 2016-09-29 | 2018-04-06 | 联芯科技有限公司 | Suppress the circuit and method of noise of blasting |
| CN111510143A (en) * | 2020-04-03 | 2020-08-07 | 四川知微传感技术有限公司 | Front-end circuit for direct conversion from capacitance to digital quantity |
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| US7095350B2 (en) * | 2004-06-23 | 2006-08-22 | Semiconductor Technology Academic Research Center | DA converter circuit provided with DA converter of segment switched capacitor type |
| CN101282120A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | A Multiplication Digital-to-Analog Conversion Circuit and Its Application |
| CN102685050A (en) * | 2011-03-17 | 2012-09-19 | 鸿富锦精密工业（深圳）有限公司 | Direct-current offset calibration circuit |
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| US7095350B2 (en) * | 2004-06-23 | 2006-08-22 | Semiconductor Technology Academic Research Center | DA converter circuit provided with DA converter of segment switched capacitor type |
| CN101282120A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | A Multiplication Digital-to-Analog Conversion Circuit and Its Application |
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| CN107452417B (en) * | 2016-06-01 | 2021-02-19 | 瑞昱半导体股份有限公司 | Data processing circuit and data processing method |
| CN107889004A (en) * | 2016-09-29 | 2018-04-06 | 联芯科技有限公司 | Suppress the circuit and method of noise of blasting |
| CN111510143A (en) * | 2020-04-03 | 2020-08-07 | 四川知微传感技术有限公司 | Front-end circuit for direct conversion from capacitance to digital quantity |
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