CN104779921B - A kind of class-D amplifier and its control method - Google Patents
A kind of class-D amplifier and its control method Download PDFInfo
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- CN104779921B CN104779921B CN201510073003.2A CN201510073003A CN104779921B CN 104779921 B CN104779921 B CN 104779921B CN 201510073003 A CN201510073003 A CN 201510073003A CN 104779921 B CN104779921 B CN 104779921B
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Abstract
The invention discloses a kind of class-D amplifier and its control methods, suitable biasing voltage signal is exported by control error amplifier to control the gate source voltage difference of integral transistor, so that gate source voltage difference maintains on its threshold voltage, to integrate the mos capacitance of transistor always steady operation in strong inversion area, and integrating capacitor of the mos capacitance as error integrator by the way that transistor will be integrated, it can guarantee that the integrating capacitor of error integrator remains always stable, in this way in class-D amplifier, chip area can be saved, reduce the exposure mask number of plies in production, design through the invention simultaneously, improve the harmonic distortion performance and loop stability of amplifier.
Description
Technical field
The present invention relates to field of power electronics, more specifically to a kind of class-D amplifier and its control method.
Background technique
Class-D amplifier is commonly used for the power amplifier of the loudspeaker in driving audio devices, and the quality of performance is directly
The audio of loudspeaker is influenced, is as shown in Figure 1 a kind of realization circuit diagram of the class-D amplifier of the prior art comprising: error value product
Divide device, OPA and integrating capacitor C as shown in figure 1intThe error integrator of composition, for defeated to input signal and from class-D amplifier
The difference of feedback signal out is integrated, and feedback signal passes through resistance RFBFeedback obtains；PWM modulation, comparison as shown in figure 1 are electric
Road com, for generating the pulse with pulse width corresponding with the level of integration value signal exported from error integrator；
Power amplification, PWR circuit as shown in figure 1 are used for the size according to above-mentioned pulse signal modulation output power；Low-pass filtering is being schemed
It is not shown in 1, the output signal of power amplifying part is filtered.
Wherein, in the error intergal part of the prior art, an integrating capacitor usually is connected in parallel on the two of error amplifier
End, integrating capacitor C as shown in figure 1int, the stationary value of integrating capacitor capacitance produces bigger effect the performance of error integrator, existing
Have the integrating capacitor of technology usually there are two types of implementation:
1) metal (Metal) capacitor is utilized, usual metal capacitor's capacity is stablized, and it may make the linearity of amplifier high, but
It is big that additional increased capacitor will lead to chip entire area, and in device technology, will increase the number of exposure mask, manufacturing cost
Rise very much.
2) mos capacitance is used, this is a kind of mode more commonly used at present, i.e., using the mos capacitance of transistor as product
Divide capacitor, mos capacitance often shows stronger voltage control characteristic, the capacitance curve graph of NMOS capacitor as shown in Figure 2, grid
Capacitor between source is different with the variation of gate source voltage, as shown in Figure 2 at trench shape, when grid is negative voltage, MOS
Capacitor work is in accumulation area, and when grid is greater than threshold voltage, mos capacitance can work in strong inversion area, in general,
In the case where accumulation area, the capacitance of mos capacitance is very unstable for work, and capacitance can be relatively more steady in the case where strong inversion area for work
It is fixed.This mode for metal capacitance, do not need increase the exposure mask number of plies, but due to the capacitance of mos capacitance easily with
The variation of grid voltage and change, cause Amplifier linearity that can become very poor, and change capacitance make error integrator
Harmonic distortion function reduction, even can make amplifier oscillatory instability sometimes.
On the basis of above-mentioned mos capacitance, existing research staff proposes to be formed using two MOS power devices in parallel
Mos capacitance, as shown in figure 3, a capacitor job, in accumulation area, in inversion regime, this mode can increase for another work
The stability of mos capacitance, but its total area at least increases by twice, and can still reduce in subthreshold voltage area capacitance value,
Lead to Amplifier linearity difference and unstability.
Summary of the invention
In view of this, exporting suitable biased electrical by control error amplifier the invention proposes a kind of class-D amplifier
Signal is pressed, so that the gate source voltage difference of integral transistor always on its threshold voltage, guarantees the MOS electricity of integral transistor
Appearance can always work at strong inversion area, and the capacitance of mos capacitance is stablized, so that the linearity of amplifier is good, stability is high.
A kind of class-D amplifier according to the present invention, the class-D amplifier include error integrator, pwm control circuit,
Power amplification circuit, the error integrator include first order error amplifier and first order upper integral transistor, and described first
Two input terminals of grade error amplifier receive input electrical signal, and the first order upper integral transistor is connected to the first order
Between the first input end of error amplifier and the first output end, wherein the drain electrode of the first order upper integral transistor and source
Pole is connected；
The common-mode output of the first order error amplifier exports the first biasing voltage signal；
Also, first biasing voltage signal differs preset voltage value so that described with the input electrical signal
The mos capacitance of level-one upper integral transistor maintains to stablize.
Preferably, it is specially described that first biasing voltage signal, which differs preset voltage value with the input electrical signal,
The voltage difference of first biasing voltage signal and the input electrical signal is more than or equal to leading for the first order upper integral transistor
Logical threshold voltage.
Further, the error integrator further includes first order lower integral transistor, the first order lower integral crystal
Pipe is identical transistor with the first order upper integral transistor, also,
The first order lower integral transistor is connected to the second input terminal of the first order error amplifier and second defeated
Between outlet, wherein the drain electrode of the first order lower integral transistor is connected with source electrode；
Wherein, the voltage signal phase that the second output terminal of the first order error amplifier is exported with its first output end
Deng.
Preferably, the mos capacitance of the mos capacitance of the first order upper integral transistor and first order lower integral transistor is made
For the integrating capacitor of the error integrator.
Further, the error integrator further includes second level error amplifier and second level upper integral transistor, institute
Two input terminals for stating second level error amplifier pass through interlaminated resistance is connected to the first order error amplifier respectively
One output end and second output terminal；
The second level upper integral transistor is connected to the first input end of the second level error amplifier and first defeated
Between outlet, wherein the drain electrode of the second level upper integral transistor is connected with source electrode；
The common-mode output of the second level error amplifier exports the second biasing voltage signal；
Wherein, first biasing voltage signal differs preset voltage value so that described with the second biasing voltage signal
The mos capacitance of second level upper integral transistor maintains to stablize.
Preferably, it is specially institute that first biasing voltage signal, which differs preset voltage value with the second biasing voltage signal,
The voltage difference for stating the first biasing voltage signal and second offset signal is more than or equal to the second level upper integral transistor
On state threshold voltage.
Further, the error integrator further includes second level lower integral transistor, the second level lower integral crystal
Pipe is identical transistor with the second level upper integral transistor, also,
The second level lower integral transistor is connected to the second input terminal of the second level error amplifier and second defeated
Between outlet, wherein the drain electrode of the second level lower integral transistor is connected with source electrode；
The second output terminal of the second level error amplifier is equal with the voltage signal that its first output end exports.
Preferably, the mos capacitance of the mos capacitance of the second level upper integral transistor and second level lower integral transistor is made
For the integrating capacitor of the error integrator.
A kind of control method of class-D amplifier according to the present invention, the class-D amplifier include error integrator, PWM
Control circuit, power amplification circuit, using the mos capacitance of integral transistor as the integrating capacitor of the error integrator, control
The gate source voltage difference of the integral transistor is made, so that during the work time, the gate source voltage difference of the integral transistor
Stablize on the threshold voltage of transistor, so that the capacitance of the mos capacitance of the integral transistor remains always stable.
It can be seen from the above, a kind of class-D amplifier of the invention and its control method, pass through the biasing of control error amplifier
Voltage signal, and the gate source voltage difference for integrating transistor is made to differ scheduled voltage difference, so that integral transistor
Gate source voltage difference maintain on threshold voltage, guarantee integral transistor mos capacitance can always work in strong inversion
The capacitance in area, mos capacitance is stablized, so that the linearity of amplifier is good, loop stability is high；By utilizing integral transistor
Integrating capacitor of the mos capacitance as error integrator can reduce the exposure mask number of plies of technique, save cost.
Detailed description of the invention
Fig. 1 show a kind of realization circuit diagram of the class-D amplifier of the prior art；
Fig. 2 show the capacitance voltage curves figure of NMOS capacitor；
Fig. 3 show the mos capacitance that two MOS power devices in parallel are formed；
Fig. 4 A show the first implementation circuit diagram of single order class-D amplifier according to the present invention；
Fig. 4 B show second of implementation circuit diagram of single order class-D amplifier according to the present invention；
Fig. 4 C show the third implementation circuit diagram of single order class-D amplifier according to the present invention；
Fig. 4 D show the 4th kind of implementation circuit diagram of single order class-D amplifier according to the present invention；
Fig. 5 show the realization circuit diagram of second order class-D amplifier according to the present invention.
Specific embodiment
Several preferred embodiments of the invention are described in detail below in conjunction with attached drawing, but the present invention is not restricted to
These embodiments.The present invention covers any substitution made on the essence and scope of the present invention, modification, equivalent method and side
Case.In order to make the public have thorough understanding to the present invention, it is described in detail in the following preferred embodiment of the present invention specific thin
Section, and the present invention can also be understood completely in description without these details for a person skilled in the art.
The first implementation circuit diagram of single order class-D amplifier according to the present invention is shown with reference to Fig. 4 A, such as Fig. 4 A
Shown, the class-D amplifier mainly includes error integrator, PWM modulation circuit, power amplification circuit and low-pass filtering electricity
Road, (wherein low-pass filter circuit is not shown), wherein the function of various pieces be with functions described in the prior art
It is identical, and each circuit structure phase of the PWM modulation circuit, power amplification circuit and low-pass filter circuit and the prior art
Together, it repeats no more herein, the difference is that in the present invention, the error integrator includes first order error amplifier
Two input terminals of OPA1 and the first order upper integral transistor Q1, the first order error amplifier OPA1 receive input electrical signal
Vin, the first order upper integral transistor Q1 are connected to first input end and the first output of the first order error amplifier
Between end, wherein the drain electrode of the first order upper integral transistor is connected with source electrode；Specifically, in the present embodiment, described
The grid of first order upper integral transistor Q1 connects the first input end of the first order error amplifier OPA1, in the first order
The points of common connection for integrating the source electrode and drain electrode of transistor Q1 is connected to the first output of the first order error amplifier OPA1
End；
The common-mode output of the first order error amplifier OPA1 exports the first biasing voltage signal Vcm1；
Wherein, first biasing voltage signal differs preset voltage value so that described with the input electrical signal
The mos capacitance of level-one upper integral transistor Q1 maintains to stablize, in the present embodiment, the first biasing voltage signal Vcm1It is less than
The input electrical signal Vin, and, the voltage difference of first biasing voltage signal and the input electrical signal is more than or equal to institute
State the on state threshold voltage of first order upper integral transistor Q1.
Further, in the present embodiment, the error integrator further includes first order lower integral transistor Q3, the first order
The lower integral transistor Q3 and first order upper integral transistor Q1 is identical transistor, the first order lower integral transistor
Q3 is connected between the second input terminal and second output terminal of the first order error amplifier OPA1, wherein the first order
The drain electrode of lower integral transistor Q3 is connected with source electrode；Specifically, in the present embodiment, the first order lower integral transistor Q3
Grid connect the second input terminal of the first order error amplifier OPA1, the drain electrode of the first order lower integral transistor Q3 and
The points of common connection of source electrode is connected to the second output terminal of the first order error amplifier OPA1；Wherein, the first order error
The second output terminal of amplifier OPA1 is equal with the voltage signal that its first output end exports.
In embodiments of the present invention, the first order upper integral transistor Q1 and the first order lower integral transistor Q3 are equal
By taking n type field effect transistor as an example, here, first order upper integral transistor Q1 is with the first order lower integral transistor Q3
Low voltage transistor.The mos capacitance of the first order upper integral transistor and the mos capacitance of first order lower integral transistor are as institute
The integrating capacitor for stating error integrator, such as the capacitor C in Fig. 4int1With capacitor Cint3。
As can be seen that the grid of the first order upper integral transistor Q1 and first order lower integral transistor Q3 from Fig. 4 A
Voltage is the input terminal voltage of first order error amplifier OPA1, and the source voltage of the first order upper integral transistor Q1 is the
The first output end voltage of level-one error amplifier OPA1, the source voltage of the first order lower integral transistor Q3 are the first order
The second output terminal voltage of error amplifier OPA1.According to the working principle of error amplifier, when the first order error is amplified
When the voltage differential of two input terminals of device OPA1 is 0, then the first output end voltage of the first order error amplifier OPA1
It is equal with second output terminal voltage, and it is equal to the first biasing voltage signal V of its common-mode output outputcm1, herein, if
Set the first biasing voltage signal Vcm1For low voltage signal, such as it is set as 0.35V, then the first order upper integral transistor
The source voltage of Q1 and first order lower integral transistor Q3 are 0.35V, and input electrical signal is the biggish signal of voltage value, much
Greater than 0.35V, in this way, may make the gate source voltage difference of first order upper integral transistor Q1 and first order lower integral transistor Q3
Greater than its on state threshold voltage, by the capacitance voltage curves in Fig. 2 it is found that under first order upper integral transistor Q1 and the first order
The mos capacitance of integral transistor Q3 can always work in strong inversion area, and capacitance keeps stablizing.
It can be seen that in embodiments of the present invention by above-mentioned process, it is suitable by control error amplifier output
Biasing voltage signal carrys out the both end voltage of the integral transistor of biased error integrator, so that the mos capacitance one of integral transistor
In this way in class-D amplifier, the harmonic distortion performance and loop stability of amplifier can be improved in strong inversion area in straight steady operation
Property, while chip area can be saved as integrating capacitor using the mos capacitance of transistor, reduce the exposure mask number of plies in production.
The single order class-D amplifier of full bridge structure is illustrated in above-described embodiment, skilled person will appreciate that, it is above-mentioned
Class-D amplifier is not limited to above structure, can also be the class-D amplifier of half-bridge structure, such as class-D amplifier only includes in Fig. 4 A
The circuit structure of top half, the mos capacitance that invention thought through the invention also can achieve control integral transistor are stablized
Purpose, do not illustrate one by one herein.
In the above-described embodiments, the grid of the first order upper integral transistor Q1 and the first order lower integral transistor Q3
Pole tension is input electrical signal, and source voltage is the first biasing voltage signal, skilled person will appreciate that, in the first order
The connection type of the integral transistor Q1 and first order lower integral transistor Q3 is not limited to above-mentioned connection type, such as Fig. 4 B
It show second of implementation circuit diagram of single order class-D amplifier according to the present invention；The first order upper integral transistor
The points of common connection of the source electrode and drain electrode of Q1 connects the first input end of the first order error amplifier OPA1, the first order
The grid of upper integral transistor Q1 is connected to the first output end of the first order error amplifier OPA1；Product under the first order
The second input terminal for dividing the points of common connection of the source electrode and drain electrode of transistor Q3 to connect the first order error amplifier OPA1, institute
The grid for stating first order lower integral transistor Q3 is connected to the second output terminal of the first order error amplifier OPA1.Similarly
, in the present embodiment, the first biasing voltage signal for controlling the first order error amplifier OPA1 output is larger, that is, is greater than
The input electrical signal, also, the voltage difference of first biasing voltage signal and the input electrical signal is more than or equal to institute
State the on state threshold voltage of first order upper integral transistor Q1.In this way, according to by the capacitance voltage curves in Fig. 2 it is found that the
The mos capacitance of level-one upper integral transistor Q1 and first order lower integral transistor Q3 can always work in strong inversion area, and capacitance is protected
It is fixed to keep steady.
In addition, one skilled in the art will appreciate that above-mentioned first order upper integral transistor Q1 and the first order lower integral
The type of transistor Q3 is not limited to above-mentioned n type field effect transistor, can also be P-type transistor, be as shown in Figure 4 C foundation
The third implementation circuit diagram of single order class-D amplifier of the invention；Still by taking single order class-D amplifier as an example, the first order
The upper integral transistor Q1 and first order lower integral transistor Q3 is p type field effect transistor, likewise, in the first order
The grid of integral transistor Q1 connects the first input end of the first order error amplifier OPA1, the first order upper integral crystal
The points of common connection of the source electrode and drain electrode of pipe Q1 is connected to the first output end of the first order error amplifier OPA1；Described
The grid of level-one lower integral transistor Q3 connects the second input terminal of the first order error amplifier OPA1, under the first order
The points of common connection for integrating the source electrode and drain electrode of transistor Q3 is connected to the second output of the first order error amplifier OPA1
End.
According to the working principle of P-type transistor, in the present embodiment, the first order error amplifier OPA1 output is controlled
The first biasing voltage signal be greater than the input electrical signal, and, first biasing voltage signal and the input electrical signal
Voltage difference be more than or equal to the first order upper integral transistor Q1 on state threshold voltage.In this way, according to by Fig. 2
Capacitance voltage curves are it is found that the mos capacitance of first order upper integral transistor Q1 and first order lower integral transistor Q3 can works always
Make in strong inversion area, capacitance keeps stablizing.
According to the enlightenment of Fig. 4 A and 4B, one skilled in the art will appreciate that working as the first order upper integral transistor Q1 and institute
State first order lower integral transistor Q3 be p type field effect transistor when, connection type can also be other connection types, such as scheme
4D show the 4th kind of implementation circuit diagram of single order class-D amplifier according to the present invention；The first order upper integral crystal
The points of common connection of the source electrode and drain electrode of pipe Q1 connects the first input end of the first order error amplifier OPA1, the first order
The grid of upper integral transistor Q1 is connected to the first output end of the first order error amplifier OPA1；Product under the first order
The second input terminal for dividing the points of common connection of the source electrode and drain electrode of transistor Q3 to connect the first order error amplifier OPA1, institute
The grid for stating first order lower integral transistor Q3 is connected to the second output terminal of the first order error amplifier OPA1.In this reality
It applies in example, the first biasing voltage signal for controlling the first order error amplifier OPA1 output is less than the input electrical signal,
And the voltage difference of first biasing voltage signal and the input electrical signal is more than or equal to the first order upper integral crystal
The on state threshold voltage of pipe Q1.In this way, according to the capacitance voltage curves passed through in Fig. 2 it is found that first order upper integral transistor Q1
Strong inversion area can be always worked in the mos capacitance of first order lower integral transistor Q3, capacitance keeps stablizing.
Second of realization circuit diagram of class-D amplifier according to the present invention is shown with reference to Fig. 5, in the embodiment of the present invention
In, the class-D amplifier is second order amplifier, the error integrator in the embodiment of the present invention on the basis of the above embodiments,
Further comprise second level error amplifier OPA2 and second level upper integral transistor Q2, the second level error amplifier
The first input end of OPA2 passes through interlaminated resistance RmidIt is connected to the first output end of the first order error amplifier OPA2.
The control of the second level upper integral transistor Q2 terminates the first output of the second level error amplifier OPA2
End, the first power end and the second power end of the second level upper integral transistor Q2 is connected, and points of common connection is connected to
The first input end of the second level error amplifier OPA2.
The common-mode output of the second level error amplifier OPA2 exports the second biasing voltage signal Vcm2。
Wherein, the first biasing voltage signal Vcm1Less than the second biasing voltage signal Vcm2, and first biased electrical
Press signal Vcm1With the second biasing voltage signal Vcm2Preset voltage value is differed so that the second level upper integral transistor
Mos capacitance maintains to stablize, and here, the preset voltage value is the conducting more than or equal to the second level upper integral transistor Q2
Threshold voltage.
Further, in the present embodiment, the error integrator further includes second level lower integral transistor Q4, the second level
The lower integral transistor Q4 and second level upper integral transistor Q2 is identical transistor, the second level lower integral transistor
The control of Q4 terminates the second output terminal of the second level error amplifier OPA2, and the of the second level lower integral transistor Q4
One power end and the second power end are connected, and points of common connection is connected to the second input of the second level error amplifier OPA2
End；The second output terminal of the second level error amplifier OPA2 is equal with the voltage signal that its first output end exports.
In embodiments of the present invention, the second level upper integral transistor Q2 and the second level lower integral transistor Q4 are equal
By taking n type field effect transistor as an example, here, second level upper integral transistor Q2 is with the second level lower integral transistor Q4
Low voltage transistor.The mos capacitance of the second level upper integral transistor Q2 and second level lower integral transistor Q4 is as institute
The integrating capacitor for stating error integrator, such as the capacitor C in Fig. 5int2With capacitor Cint4, therefore, for second order class-D amplifier, product
Divide capacitor includes the capacitor C in Fig. 5 in totalint1, capacitor Cint2, capacitor Cint3With capacitor Cint4.One skilled in the art will appreciate that
It is brilliant that the second level upper integral transistor Q2 and the second level lower integral transistor Q4 type are not limited to above-mentioned N-type field-effect
Body pipe, as long as the transistor for meeting mos capacitance requirement can be using so far.
The first input end of the circuit according to Fig. 5, second level error amplifier OPA2 passes through interlaminated resistance RmidIt connects
First output end of the first order error amplifier, since the resistance of second level upper integral transistor is higher, intermediate electricity
Hinder RmidThere is no electric current to pass through, then the first input end of second level error amplifier OPA2 and the first order error amplifier
The voltage of the first output end of OPA1 is equal, and herein, the electricity of the first output end of first order error amplifier is still with 0.35V
Example, then the source voltage of the second level upper integral transistor Q2 and second level upper integral transistor Q4 is 0.35V.Control
Second biasing voltage signal V of second level error amplifier OPA2 outputcm2For high voltage signal, such as it is set as 2V, according to error
The working principle of amplifier, it is when the voltage differential of two input terminals of the second level error amplifier OPA2 is 0, then described
The first output end voltage and second output terminal voltage V2 of second level error amplifier OPA2 with its common-mode output output the
Two biasing voltage signal Vcm2It is equal, as 2V, then the second level upper integral transistor Q2 and the second level upper integral crystal
The grid voltage of pipe Q4 is 2V, in this way, may make the second level upper integral transistor Q2 and the second level upper integral crystal
There is the gate source voltage difference of pipe Q4 biggish difference to pass through the capacitance voltage curves in Fig. 2 to be sufficiently more than its threshold voltage
It is found that the mos capacitance of the second level upper integral transistor Q2 and the second level upper integral transistor Q4 can always work in
Strong inversion area, capacitance are stablized.
It can be seen that in embodiments of the present invention by above-mentioned process, it is defeated by controlling second level error amplifier respectively
Out suitable biasing voltage signal come bias it is at different levels integral transistors gate source voltages so that it is at different levels integral transistor MOS electricity
Appearance can steady operation be in strong inversion area always, in this way in class-D amplifier, is preferably worked, is improved using integrating capacitor
The harmonic distortion performance and stability of amplifier, while reducing the exposure mask number of plies in production.
You need to add is that the above embodiment of the present invention is explained by taking single order class-D amplifier and second order class-D amplifier as an example
Technical solution of the present invention is stated, but class-D amplifier in fact of the invention is not limited to two kinds of above-mentioned situations, can also such as apply
In three rank class-D amplifiers or high-order class-D amplifier etc., using analogizing made by invention thought of the invention and modify at this
Within the protection scope of invention.
Finally, the class-D amplifier includes error value product the invention also discloses a kind of control method of class-D amplifier
Divide device, pwm control circuit, power amplification circuit, using the mos capacitance of integral transistor as the integral of the error integrator
Capacitor controls the gate source voltage difference of the integral transistor, so that during the work time, the grid source electricity of the integral transistor
Pressure difference is stablized on the threshold voltage of integral transistor, so that the capacitance one of the mos capacitance of the integral transistor
It is straight to maintain to stablize.
Detailed retouch has been carried out to a kind of class-D amplifier of preferred embodiment according to the present invention and its control method above
It states, those of ordinary skill in the art can deduce that other technologies or structure and circuit layout, element etc. can be applied accordingly
In the embodiment.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (8)
1. a kind of class-D amplifier, the class-D amplifier includes error integrator, pwm control circuit, power amplification circuit,
It is characterized in that, the error integrator includes first order error amplifier and first order upper integral transistor, and the first order is missed
Two input terminals of poor amplifier receive input electrical signal,
The drain electrode of the first order upper integral transistor is connected with source electrode, the drain electrode of the first order upper integral transistor and source
One and the of the first order error amplifier in the grid of the total tie point of pole and the first order upper integral transistor
One input terminal is connected, another is then connected with the first output end of the first order error amplifier,
The common-mode output of the first order error amplifier exports the first biasing voltage signal, and puts in the first order error
In big device, signal that first biasing voltage signal and first output end export it is equal in magnitude；
Also, in the course of work of the class-D amplifier, the size of first biasing voltage signal is controlled, so that described
Preset voltage value is differed between first biasing voltage signal and the input electrical signal, the preset voltage value makes in institute
It states in the course of work of class-D amplifier, the gate source voltage difference of the first order upper integral transistor is consistently greater than described first
The on state threshold voltage of grade upper integral transistor, so that the mos capacitance of the first order upper integral transistor is in the D class
Strong inversion area is always worked in the course of work of amplifier, to stablize the capacitance of the mos capacitance.
2. class-D amplifier according to claim 1, which is characterized in that the error integrator further includes product under the first order
Dividing transistor, the first order lower integral transistor and the first order upper integral transistor are identical transistor, also,
The first order lower integral transistor is connected to the second input terminal and second output terminal of the first order error amplifier
Between, wherein the drain electrode of the first order lower integral transistor is connected with source electrode；
Wherein, the second output terminal of the first order error amplifier is equal with the voltage signal that its first output end exports.
3. class-D amplifier according to claim 2, which is characterized in that the mos capacitance of the first order upper integral transistor
Integrating capacitor with the mos capacitance of first order lower integral transistor as the error integrator.
4. class-D amplifier according to claim 2, which is characterized in that the error integrator further comprises second
Grade error amplifier and second level upper integral transistor, two input terminals of the second level error amplifier pass through centre respectively
Resistance is connected to the first output end and second output terminal of the first order error amplifier；
The second level upper integral transistor is connected to the first input end and the first output end of the second level error amplifier
Between, wherein the drain electrode of the second level upper integral transistor is connected with source electrode；
The common-mode output of the second level error amplifier exports the second biasing voltage signal；
Wherein, the voltage of the first output end output of the second level error amplifier and the second biasing voltage signal phase
With the second biasing voltage signal preset voltage value is differed Deng, first biasing voltage signal so that product on the second level
The mos capacitance of transistor is divided to maintain to stablize.
5. class-D amplifier according to claim 4, which is characterized in that first biasing voltage signal and the second biasing
Voltage signal differs the voltage difference that preset voltage value is specially first biasing voltage signal Yu second offset signal
Value is more than or equal to the on state threshold voltage of the second level upper integral transistor.
6. class-D amplifier according to claim 4, which is characterized in that the error integrator further includes product under the second level
Dividing transistor, the second level lower integral transistor and the second level upper integral transistor are identical transistor, also,
The second level lower integral transistor is connected to the second input terminal and second output terminal of the second level error amplifier
Between, wherein the drain electrode of the second level lower integral transistor is connected with source electrode；
The second output terminal of the second level error amplifier is equal with the voltage signal that its first output end exports.
7. class-D amplifier according to claim 6, which is characterized in that the mos capacitance of the second level upper integral transistor
Integrating capacitor with the mos capacitance of second level lower integral transistor as the error integrator.
8. a kind of control method of class-D amplifier, the class-D amplifier includes error integrator, pwm control circuit, power
Amplifying circuit, the error integrator include first order error amplifier and first order upper integral transistor, and the first order is missed
Two input terminals of poor amplifier receive input electrical signal, which is characterized in that including,
The drain electrode of the first order upper integral transistor is connected with source electrode, the drain electrode of the first order upper integral transistor and source
One and the of the first order error amplifier in the grid of the total tie point of pole and the first order upper integral transistor
One input terminal is connected, another is then connected with the first output end of the first order error amplifier；
Also, in the course of work of the class-D amplifier, the size of the first biasing voltage signal is controlled, so that described first
Preset voltage value is differed between biasing voltage signal and the input electrical signal, the preset voltage value makes in the D
In the course of work of class A amplifier A, the gate source voltage difference of the first order upper integral transistor is consistently greater than in the first order
The on state threshold voltage for integrating transistor, so that the mos capacitance of the first order upper integral transistor amplifies in the D class
Strong inversion area is always worked in the course of work of device, to stablize the capacitance of the mos capacitance,
Wherein first biasing voltage signal is the common-mode output output signal of the first order error amplifier, and in institute
It states in first order error amplifier, the size phase for the signal that first biasing voltage signal is exported with first output end
Deng.
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| JP4992189B2 (en) * | 2005-03-17 | 2012-08-08 | ヤマハ株式会社 | Class D amplifier |
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| CN101847968A (en) * | 2009-03-27 | 2010-09-29 | 杭州中科微电子有限公司 | High-performance D type audio power amplifier with high-order multipath feedback structure |
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