CN104769724A - Memory transistor with multiple charge storage layers - Google Patents

Abstract

A semiconductor device including non-volatile memones and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride- oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed.

Description

Memory transistor with multiple charge storage layers

Cross References to Related Applications

This application is a continuation-in-part of co-pending U.S. Application Serial No. 13/288,919 filed November 3, 2011, which is a U.S. Application Serial No. 13/288,919 filed May 13, 2008 12/152,518, a divisional issue dated November 22, 2011, of what is now Patent No. 8,063,434, which claims under 35 U.S.C. 119(e) filed May 25, 2007 Priority benefit of US Provisional Patent Application Serial No. 60/940,160, all of which are hereby incorporated by reference in their entirety.

technical field

The present invention relates generally to semiconductor devices, and more particularly to integrated circuits including non-volatile semiconductor memories and methods of manufacturing the semiconductor devices.

background

Nonvolatile semiconductor memory is a device that can be electrically erased and reprogrammed. One type of non-volatile memory that is widely used for general data storage and transfer in and between computers and other electronic devices is flash memory, such as split gate flash memory. Split-gate flash memory transistors have a similar architecture to that of conventional logic transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), because they also include a connection between the source and drain in the substrate. The control gate is formed over the channel. However, a memory transistor also includes a memory or charge-trapping layer between the control gate and the channel and insulated from both by an insulating or dielectric layer. A programming voltage applied to the control gate traps charge on the charge-trapping layer, partially canceling or shielding the electric field by the control gate, thereby changing the threshold voltage ( _VT ) of the transistor and programming the memory cell. During readout, such a shift in _VT is sensed by the presence or absence of current flowing through the channel upon application of a predetermined readout voltage. To erase a memory transistor, an erase voltage is applied to the control gate to restore or reverse the shift in _VT .

An important measure of the advantages of flash memory is data retention time, which is the time that a memory transistor can retain a charge, or remain programmed, without power being applied. The charge stored or trapped in the charge-trapping layer decreases over time due to the leakage current through the insulating layer, thereby reducing the difference between the programmed threshold voltage (VTP) and the erased threshold voltage (VTE), which limits the memory transistor data retention.

One problem with conventional memory transistors and methods of forming the same is that the charge-trapping layer typically has poor or diminished data retention over time, which limits effective transistor lifetime. Referring to FIG. 1A, if the charge-trapping layer is silicon (Si) rich, there is a large initial window or difference between VTP, represented by the graph or line 102, and VTE, represented by line 104, but the window is in the retention mode Crashes very quickly, with a time to end of life (EOL 106) of less than about 1.E+07 seconds.

Referring to Figure 1B, if, on the other hand, it is assumed that the charge-trapping layer is a high-quality nitride layer, i.e., a layer with a low stoichiometric concentration of Si, then the collapse rate of the window or the slope of Vt in the retention mode will be reduced, whereas the initial The program erase window was also reduced. Also, the slope of Vt in retention mode is still quite steep, and the leakage path is not minimized enough to significantly improve data retention, so EOL 106 is only modestly improved.

Another problem is that semiconductor memories increasingly combine logic transistors (such as MOSFETs) with memory transistors in integrated circuits (ICs) that are used in embedded memory or system-on-chip (SOC) applications. fabricated on common substrates. Many of the current processes used to form the performance of memory transistors are incompatible with the processes used to fabricate logic transistors.

Accordingly, there is a need for memory transistors and methods of forming the same that provide improved data retention and increased transistor lifetime. It is also desirable that the method of forming the memory device is compatible with the method used to form logic elements in the same IC formed on a common substrate.

Summary of the invention

The present invention provides solutions to these and other problems, and provides additional advantages over conventional memory cells or devices and methods of manufacturing the same.

Typically, the device contains a memory transistor comprising: a polysilicon channel region electrically connected to source and drain regions formed in a substrate; an oxide-nitride-nitride-oxide (ONNO) stack, which is arranged over the channel region; and a high work function gate electrode which is formed on the surface of the ONNO stack. In one embodiment, the ONNO stack comprises a multilayer charge-trapping region comprising an oxygen-rich first nitride layer and a second oxygen-poor nitride layer disposed over the first nitride layer . In another embodiment, the multilayer charge-trapping region further comprises an oxide anti-tunneling layer separating the first nitride layer from the second nitride layer.

Brief description of the drawings

These and various other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings and the appended claims presented hereinafter, in which:

1A is a graph showing data retention for a memory transistor using a charge storage layer formed according to a conventional method and having a large initial difference between a programming voltage and an erasing voltage, but the memory transistor rapidly loses charge;

1B is a graph showing data retention for a memory transistor using a charge storage layer formed according to a conventional method and having a smaller initial difference between programming and erasing voltages;

2A to 2D are partial cross-sectional side views of a semiconductor device according to an embodiment of the present invention, illustrating a process flow for forming the semiconductor device including logic transistors and nonvolatile memory transistors;

3 is a partial cross-sectional side view of a semiconductor device including a logic transistor having a high work function gate electrode and a non-volatile memory transistor according to an embodiment of the present invention;

4A and 4B show a cross-sectional view of a nonvolatile memory device comprising ONONO stacks;

5 depicts a flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device comprising an ONONO stack, according to an embodiment of the present invention;

Figure 6A shows a non-planar multi-gate device comprising multiple layers of charge-trapping regions;

Figure 6B shows a cross-sectional view of the non-planar multi-gate device of Figure 6A;

7A and 7B illustrate non-planar multi-gate devices comprising multilayer charge-trapping regions and horizontal nanowire channels;

Figure 7C shows a cross-sectional view of a vertical string of the non-planar multi-gate device of Figure 7A;

8A and 8B illustrate non-planar multi-gate devices comprising multilayer charge-trapping regions and vertical nanowire channels;

9A to 9F illustrate a gate-first scheme for fabricating the non-planar multi-gate device of FIG. 8A; and

10A to 10F illustrate a gate-last scheme for fabricating the non-planar multi-gate device of FIG. 8A.

specific description

The present invention generally relates to non-volatile memory transistors that include multiple charge storage layers and high work function gate electrodes to increase data retention and/or improve programming time and efficiency. The structures and methods are particularly useful for embedded memory or system-on-chip (SOC) applications where semiconductor devices include logic transistors and non-volatile memory transistors with high work function gate electrodes formed on a common substrate.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and techniques have not been shown in detail or in block diagram form in order to avoid unnecessarily obscuring the understanding of this description.

Reference in the description to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment. The term "to couple" as used herein can include both direct connection and indirect connection through one or more intervening components.

Briefly, a non-volatile memory transistor according to the present invention includes a high work function gate electrode formed on an oxide-nitride-oxide (ONO) dielectric stack. For a high work function gate electrode, it means that the minimum energy required to remove electrons from the gate electrode is increased.

In certain preferred embodiments, the high work function gate electrode comprises a doped polycrystalline silicon or polysilicon (poly) layer, the fabrication of which can be easily integrated into standard CMOS (CMOS) process flows (such as those used to fabricate metal-oxide-semiconductor (MOS) logic transistors) to enable fabrication of semiconductor memories or devices that contain both memory transistors and logic transistors. More preferably, the same doped polysilicon layer can also be patterned to form high work function gate electrodes for MOS logic transistors, thereby improving the performance of the logic transistors and increasing the efficiency of the manufacturing process. Optionally, the ONO dielectric stack includes multiple layers of charge storage or charge trapping layers to further improve memory transistor performance, and in particular to improve memory transistor data retention.

A semiconductor device including a nonvolatile memory transistor having a high work function gate electrode and a method of forming the same will now be described in detail with reference to FIGS. Partial cross-sectional side view of an intermediate structure of a semiconductor device's process flow for both logic transistors. For the sake of clarity, various details of semiconductor fabrication that are well known and not relevant to the present invention have been omitted from the following description.

Referring to FIG. 2 , the fabrication of a semiconductor device begins with the formation of an ONO dielectric stack 202 on a surface 204 of a wafer or substrate 206 . Typically, the ONO dielectric stack 202 includes a thin underlying or tunneling oxide layer 208 that transfers charge Trapping or storage layer 210 is separated or electrically insulated from the channel region (not shown) of the memory transistor in substrate 206 . Preferably, as noted above and as shown in FIGS. 2A-2D , the charge storage layer 210 is a multilayer charge storage layer comprising at least a top charge-trapping oxynitride layer 210A and an underlying substantially non-trapping oxynitride layer 210B. .

In general, substrate 206 may comprise any known silicon-based semiconductor material, including silicon, silicon germanium, silicon-on-insulator, or silicon-on-sapphire substrates. Alternatively, the substrate 206 may comprise a silicon layer formed on a non-silicon based semiconductor material such as gallium arsenide, germanium, gallium nitride or aluminum-aluminum phosphide. Preferably, substrate 206 is a doped or undoped silicon substrate.

The underlying oxide layer or tunneling oxide layer 208 of the ONO dielectric stack 202 typically comprises a relatively thin layer of silicon dioxide (SiO ₂ ), ranging from about 15 Angstroms to appointment and more preferably about Tunneling oxide layer 208 may be formed or deposited by any suitable means including, for example, deposition using chemical vapor deposition (CVD) or thermal growth. In a preferred embodiment, the tunneling dielectric layer is formed or grown using a vapor anneal. Typically, the process involves a wet oxidation process in which the substrate 206 is placed in a deposition or processing chamber, heated to a temperature from about 700°C to about 850°C, and exposed to moisture vapor for a predetermined period of time, the The predetermined time period is selected based on the desired thickness of the completed tunnel oxide layer 208 . Exemplary processing times are from about 5 minutes to about 20 minutes. Oxidation can be performed at atmospheric pressure or at reduced pressure.

In a preferred embodiment, the oxynitride layers 210A, 210B of the multilayer charge storage layer 210 are formed or deposited in separate steps using different processes and process gases or starting materials, and have a range from about to appointment and more preferably about total or combined thickness. The underlying trap-free oxynitride layer 210B may be formed or deposited by any suitable means including, for example, deposition in a low-pressure CVD process using process gases including: a silicon source such as monosilane (SiH ₄ ), chlorine Monosilane (SiH ₃ Cl), dichlorosilane (SiH ₂ Cl ₂ ), tetrachlorosilane (SiCl ₄ ); nitrogen sources such as nitrogen (N ₂ ), ammonia (NH ₃ ), nitrogen trioxide (NO ₃ ) or nitrous oxide (N ₂ O); and oxygen-containing gases such as oxygen (O ₂ ) or N ₂ O. In one embodiment, the trap-free oxynitride layer 210B is deposited in a low pressure CVD process using process gases including dichlorosilane, NH ₃ and N ₂ O while maintaining the chamber at from about 5 millitorr (mT) to A pressure of about 500 mT, and the substrate is maintained at a temperature of from about 700°C to about 850°C, and more preferably at least about 780°C, for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas may include a first gas mixture of _N2O and _NH3 mixed in a ratio of from about 8:1 to about 1:8 and DCS mixed in a ratio of from about 1:7 to about 7:1 and NH ₃ and can be introduced at a flow rate from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm per minute.

The top charge-trapping oxynitride layer 210A may be deposited over the bottom oxynitride layer 210B in a CVD process using a process gas including bis-tert-butylaminosilane (BTBAS). It has been found that the use of BTBAS increases the number of deep traps formed in the oxynitride by increasing the carbon level in the charge-trapping oxynitride layer 210A. In addition, these deep traps reduce charge loss due to thermal radiation, further improving data retention. More preferably, the process gas includes BTBAS and ammonia (NH ₃ ) mixed in a predetermined ratio to provide a narrow bandgap energy level in the nitrogen oxide charge-trapping layer. In particular, the process gas may include BTBAS and NH ₃ mixed in a ratio of from about 7:1 to about 1:7. For example, in one embodiment, at a chamber pressure of from about 5 mT to about 500 mT and a substrate temperature of from about 700° C. The charge trapping oxynitride layer 210A was deposited in a low pressure CVD process using BTBAS and ammonia NH ₃ over a period of 20 minutes.

It has been found that an oxynitride layer produced or deposited under the above conditions produces a trap-rich oxynitride layer 210A, which improves programming and erasing speeds and increases the initial difference between programming and erasing voltages (window) without compromising the charge loss rate of the memory transistors, thereby extending the lifetime (EOL) of the device. Preferably, the charge-trapping oxynitride layer 210A has a charge trap density of at least about 1E10/cm ² , and more preferably from about 1E12/cm ² to about 1E14/cm ² .

Alternatively, the charge-trapping oxynitride layer 210A may be deposited over the bottom oxynitride layer 210B in a CVD process using a process gas that includes BTBAS and substantially does not include ammonia (NH ₃ ). In this alternative embodiment of the method, the step of depositing the top charge-trapping oxynitride layer 210A is followed by a nitrogen atmosphere containing nitrous oxide ( _N2O ), _NH3 , and/or nitrogen monoxide (NO). thermal annealing step.

Preferably, the top charge-trapping oxynitride layer 210A is deposited sequentially in the same CVD tool used to form the bottom non-trapping oxynitride layer 210B, substantially without breaking the vacuum on the deposition chamber. More preferably, charge-trapping oxynitride layer 210A is deposited without substantially altering the temperature at which substrate 206 is heated during deposition of non-trapping oxynitride layer 210B.

An appropriate thickness for the underlying non-trapping oxynitride layer 210B has been found to be from about to appointment And it has been found that the ratio of thickness between the bottom layer and the top charge-trapping oxynitride layer is from about 1:6 to about 6:1, and more preferably at least about 1:4.

The top oxide layer 212 of the ONO dielectric stack 202 comprises from about to appointment and more preferably about relatively thick _SiO2 layer. The top oxide layer 212 may be formed or deposited by any suitable means including, for example, deposition using CVD or thermal growth. In a preferred embodiment, the top oxide layer 212 is a high temperature oxide (HTO) deposited using a CVD process. Typically, the deposition process includes exposing the substrate 306 to a silicon source such as monosilane, chlorosilane, or dichlorosilane and to an oxygen-containing gas such as O _or The _N2O is continued for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650°C to about 850°C.

Preferably, the top oxide layer 212 is deposited sequentially with the same tool used to form the oxynitride layers 210A, 210B. More preferably, the oxynitride layers 210A, 210B and the top oxide layer 212 are formed or deposited with the same tool used to grow the tunnel oxide layer 208 . Suitable tools include, for example, ONOAVP, commercially available from AVIZA Technologies of Scott Valley, California.

Referring to FIG. 2B, in those embodiments where the semiconductor device also includes logic transistors (such as MOS logic transistors) formed on the surface of the same substrate, the ONO dielectric stack 202 from which the logic transistors are to be formed and over which the oxide Layer 214 is removed in regions or regions of surface 204 .

Typically, the ONO dielectric stack 202 is removed from desired regions or regions of the surface 204 using standard photolithography techniques and oxide etch techniques. For example, in one embodiment, a patterned masking layer (not shown) is etched or removed from photoresist deposited on ONO dielectric stack 202 and using low-voltage radio frequency (RF) in conjunction with or plasma generation. formed in the exposed region, the plasma includes fluorinated hydrocarbons and/or fluorocarbons, such as are commonly referred to as C ₂ H ₂ F ₄ . Typically, the process gases also include argon (Ar) and nitrogen ( _N2 ) at flow rates selected to maintain a pressure in the etch chamber from about 50 mT to about 250 mT during processing.

The oxide layer 214 of the logic transistors may comprise from about to appointment thick _SiO2 layer, and can be deposited using CVD or thermally grown. In one embodiment, oxide layer 214 is thermally grown using a vapor oxidation process, for example by maintaining substrate 206 in a vapor environment at a temperature of from about 650° C. to about 850° C. for a period of from about 10 minutes to about 120 minutes. time period.

Next, a doped polysilicon layer is formed on the surface of the ONO dielectric stack 202, and more preferably on the surface of the oxide layer 214 of the logic transistors. More preferably, the substrate 206 is a silicon substrate or has a silicon surface on which an ONO dielectric stack is formed to form a SONOS gate stack of a silicon-oxide-nitride-oxide-silicon (SONOS) memory transistor.

Referring to FIG. 2C, the formation of the doped polysilicon layer begins with a to appointment A conformal polysilicon layer 216 is deposited over the ONO dielectric stack 202 and the oxide layer 214 in thickness. Polysilicon layer 216 may be formed or deposited by any suitable means including, for example, deposition by a low pressure CVD process using a silicon source or silicon precursor. In one embodiment, polysilicon layer 216 is deposited as a substantially undoped polysilicon layer in a low pressure CVD process using a silicon-containing process gas (eg, monosilane or dichlorosilane and N ₂ ) while maintaining substrate 206 The chamber is at a pressure of from about 5 mT to about 500 mT and at a temperature of from about 600°C to about 1000°C for a period of from about 20 minutes to about 100 minutes. The polysilicon layer 216 can be formed or grown directly by adding a gas such as phosphine, arsine, diborane, or difluoroborane (BF ₂ ) into the CVD chamber during the low pressure CVD process. into a doped polysilicon layer.

In one embodiment, the polysilicon layer 216 is doped using an ion implantation process after being grown or formed by an LPCVD process. For example, polysilicon layer 216 may be implanted with boron (B ⁺ ) or _BF ions at energies from about 5 kiloelectron volts (keV) to about 100 keV and doses from about 1e14 cm ⁻² to about 1e16 cm ⁻² . Doping to form N-type (NMOS) SONOS memory transistors, and preferably P-type (PMOS) logic transistors with high work function gate electrodes. More preferably, polysilicon layer 216 is doped to a concentration or dose selected such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8 electron volts (eV) to about 5.3 eV.

Alternatively, polysilicon layer 216 may be doped by ion implantation after patterning or etching the polysilicon layer and the underlying dielectric layer. It will be appreciated that this embodiment includes an additional masking step to protect the surface 204 of the substrate 206 and/or exposed regions of the dielectric layer from unwanted doping. However, generally such masking steps are included in existing process flows, whether implantation occurs before or after patterning.

Referring to FIG. 2D , polysilicon layer 216 and underlying dielectric stack 202 and oxide layer 214 are patterned or etched to form high work function gate electrode 218 of memory transistor 220 and logic transistor 222 . In one embodiment, polysilicon layer 216 may be etched or patterned using a plasma comprising hydrobromic acid (HBr), chlorine ( _CL2 ), and/or oxygen ( _O2 ) at a pressure of about 25 mTorr and a power of about 450W change. The oxide layers 208 , 212 , 214 and the oxynitride layers 210A, 210B can be etched using standard photolithography techniques and oxide etch techniques as described. For example, in one embodiment, patterned polysilicon layer 216 is used as a mask, and exposed oxide layers 208, 212, 214 and oxynitride layers 210A, 210B are etched or removed using low pressure RF plasma. Typically, the plasma is formed from a process gas comprising fluorinated hydrocarbons and/or fluorocarbons and also comprising Ar and N ₂ .

Finally, the substrate is thermally annealed at a temperature of from about 800° C. to about 1050° C. for a period of from about 1 second to about 5 minutes in a single or multiple annealing steps to drive in the ions implanted into the polysilicon layer 216 and Damage to the crystal structure of the polysilicon layer caused by ion implantation is repaired. Alternatively, advanced annealing techniques such as flash and laser can be applied at temperatures as high as 1350°C and annealing times as low as 1 millisecond.

A partial cross-sectional side view of a semiconductor device 300 including a logic transistor 302 with a high work function gate electrode and a non-volatile memory transistor 304 according to an embodiment of the invention is shown in FIG. 3 . Referring to FIG. 3 , a memory transistor 304 is formed on a silicon substrate 306 and includes a high work function gate electrode 308 formed from a doped polysilicon layer overlying a dielectric stack 310 . Dielectric stack 310 covers and controls current flow through channel region 312 , which separates heavily doped source and drain (S/D) regions 314 . Preferably, the dielectric stack 310 includes a tunneling dielectric layer 316 , multiple charge storage layers 318A, 318B and a top or blocking oxide layer 320 . More preferably, the multilayer charge storage layers 318A, 318B include at least a top charge-trapping oxynitride layer 318A and an underlying substantially free-trapping oxynitride layer 318B. Optionally, as shown in FIG. 3, the memory transistor 304 further includes one or more sidewall spacers 322 surrounding the gate stack to electrically connect the gate stack to contacts (not shown) of the S/D region 320. Insulated and electrically isolated from other transistors in the semiconductor device formed on the substrate 306 .

The logic transistor 302 includes a gate electrode 324 overlying an oxide layer 326 formed over a channel region 328 separating heavily doped source and drain regions 330, and optionally may include a surrounding gate electrode 324. One or more sidewall spacers 332 of the pole to electrically insulate the gate from the contacts (not shown) of the S/D regions. Preferably, as shown in FIG. 3, the gate electrode 324 of the logic transistor 302 further comprises a high work function gate electrode formed of a doped polysilicon layer.

Typically, the semiconductor device 300 also includes a large number of isolation structures 334 (eg, local oxidation of silicon (LOCOS) regions or structures, field oxide regions or structures (FOX) or shallow trench isolation (STI) structures) to allow formation on the substrate 306 The individual transistors are electrically isolated from each other.

Implementation and Alternatives

In one aspect, the present disclosure relates to a semiconductor device including a memory transistor having a high work function gate electrode and a multilayer charge trapping region. FIG. 4A is a block diagram illustrating a cross-sectional side view of an embodiment of one such memory transistor 400 . The memory transistor 400 includes an ONNO stack 402 including an ONNO structure 404 formed on a surface 406 of a substrate 408 . The substrate 408 includes one or more diffusion regions 410 , such as source and drain regions, aligned with the gate stack 402 and separated by a channel region 412 . Generally, ONNO stack 402 includes a high work function gate electrode 414 formed over and in contact with ONNO structure 404 . High work function gate electrode 414 is separated or electrically isolated from substrate 408 by ONNO structure 404 . ONNO structure 404 includes a thin underlying oxide or tunneling dielectric layer 416 separating or electrically isolating ONNO stack 402 from channel region 412 , a top or blocking dielectric layer 420 , and a multilayer charge trapping region 422 .

The nanowire channel region 412 may comprise polysilicon or recrystallized polysilicon to form a single crystal channel region. Optionally, where the channel region 412 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystallographic orientation relative to the long axis of the channel region.

The high work function gate electrode 414 comprises a doped polysilicon layer formed or deposited by a low pressure CVD process and having a thickness from about to appointment thickness of. As mentioned above, the polysilicon layer of the high work function gate electrode 414 can be formed by adding a gas such as phosphine, arsine, diborane or boron difluoride (BF ₂ ) to the CVD process during the low pressure CVD process. The polysilicon layer is directly formed or grown as a doped polysilicon layer in a chamber, or can be doped using an ion implantation process after being grown or formed according to a CVD process. In either embodiment, the polysilicon layer of high work function gate electrode 414 is doped at a concentration or dose selected such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8 electron volts (eV) to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 414 is implanted with boron at an energy of from about 5 kiloelectron volts (keV) to about 100 keV and at a dose of from about 1e14 cm ⁻² to about 1e16 cm ⁻² . (B ⁺ ) or BF ₂ ions are doped to form N-type (NMOS) memory transistors.

Tunneling dielectric layer 416 may be any material and have any thickness suitable to allow charge carriers to tunnel into multilayer charge-trapping region 422 under an applied gate bias while remaining resistant to leakage when memory transistor 400 is unbiased. an appropriate barrier. In one embodiment, the tunneling dielectric layer 416 is formed by a thermal oxidation process and is composed of silicon dioxide or silicon oxynitride or a combination thereof. In another embodiment, tunneling dielectric layer 416 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) and consists of a dielectric layer that may include, but is not limited to, silicon nitride, hafnium oxide, zirconium oxide , hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide. In a particular implementation, the tunneling dielectric layer 416 has a thickness in the range of 1 nanometer to 10 nanometers. In a particular embodiment, tunneling dielectric layer 416 has a thickness of approximately 2 nanometers.

In one embodiment, the blocking dielectric layer 420 includes a high temperature oxide (HTO). Higher quality HTO oxide enables blocking dielectric layer 420 to be scaled in thickness. In an exemplary embodiment, the blocking dielectric layer 420 comprising HTO oxide has a thickness between 2.5 nm and 10.0 nm.

In another embodiment, the blocking dielectric layer 420 is also modified to include nitrogen. In one such embodiment, nitrogen is included in the form of an ONO stack over the thickness of the blocking dielectric layer 420 . Such a sandwich structure instead of a conventional pure oxygen blocking dielectric layer advantageously reduces the EOT of the entire stack 402 between the channel region 412 and the high work function gate electrode 414 and enables tuning of the band offset to reduce carrier back-injection. A blocking dielectric layer 420 of the ONO stack may then be included along with the tunneling dielectric layer 416 and a multilayer charge-trapping layer 422 comprising an oxygen-rich first nitride layer 422a, an oxygen-poor second The nitride layer 422b and the anti-tunneling layer 422c.

The multilayer charge-trapping region 422 typically includes at least two nitride layers having different compositions of silicon, oxygen, and nitrogen, including an oxygen-rich first nitride layer 422a and a silicon-rich, nitrogen-rich, and oxygen-poor second nitride layer. 422b, silicon-rich. In certain embodiments, such as the embodiment shown in FIG. 4B , the multilayer charge-trapping region also includes an anti-tunneling layer 422c comprising an oxide, such as silicon dioxide, to provide an ONONO stack comprising ONONO structure 404 402, the anti-tunneling layer 422c separates the oxygen-poor second nitride layer 422b from the oxygen-rich first nitride layer 422a.

It has been found that an oxygen-rich first nitride layer 422a reduces the rate of charge loss after programming and after erasing, which manifests as a small voltage shift in retention mode, whereas a silicon-rich, nitrogen-rich, and oxygen-poor The second nitride layer 422b improves the speed and the amount of increase in the initial difference between the programming and erasing voltages without damaging memory transistors made using embodiments of the silicon-oxide-oxynitride-oxide-silicon structure The charge loss rate, thereby prolonging the service life of the device.

It has also been found that the anti-tunneling layer 422c substantially reduces the probability of electron charges accumulating at the boundary of the oxygen-lean second nitride layer 422b during programming from the tunneling layer into the first nitride layer 422a, This results in lower leakage current than for conventional non-volatile memory transistors.

The multilayer charge-trapping region can have from about to appointment a total thickness of , and in some embodiments have a thickness of less than about The total thickness, along with the thickness of the anti-tunneling layer 422c from about to appointment And the thicknesses of the nitride layers 404b and 404a are substantially equal.

A method of forming or manufacturing a semiconductor device including a memory transistor having a high work function gate electrode and a multilayer charge trapping region according to one embodiment will now be described with reference to the flowchart of FIG. 5 .

Referring to FIG. 5, the method begins by forming a tunneling dielectric layer, such as a first oxide layer, on a silicon-containing layer on a surface of a substrate (500). The tunneling dielectric layer may be formed or deposited by any suitable means, including plasma oxidation processes, in situ steam generation (ISSG) or radical oxidation processes. In one embodiment, the radical oxidation process includes flowing hydrogen ( _H2 ) and oxygen ( _O2 ) into a processing chamber or furnace to affect the growth of the tunneling dielectric layer by oxidizing a portion of the substrate.

Next, an oxygen-rich first nitride layer of the multilayer charge-trapping region is formed on the surface of the tunneling dielectric layer (502). In one embodiment, the oxygen-enriched first nitride layer is processed in a low pressure CVD process using a silicon source such as monosilane (SiH ₄ ), chlorosilane (SiH ₃ Cl), dichlorosilane or DCS (SiH ₂ Cl ₂ ), tetrachlorosilane (SiCl ₄ ) or bis-tert-butylaminosilane (BTBAS)), nitrogen source (such as nitrogen (N ₂ ), ammonia (NH ₃ ), nitrogen trioxide (NO ₃ ) or monoxide Dinitrogen (N ₂ O)) and oxygen-containing gases such as oxygen (O ₂ ) or N ₂ O) are formed or deposited. Alternatively, gases in which hydrogen has been replaced by deuterium may be used, including, for example, deuterated ammonia (ND ₃ ) in place of NH ₃ . Substituting deuterium for hydrogen advantageously passivates the Si dangling bonds at the silicon oxide interface, thereby increasing the NBTI (Negative Bias Temperature Instability) lifetime of the device.

For example, by placing the substrate in a deposition chamber and introducing process gases including _N2O , _NH3 , and DCS while maintaining the chamber at a pressure from about 5 millitorr (mT) to about 500 mT and keeping the substrate The underlying or oxygen-enriched first nitride layer may be allowed to deposited over the tunneling dielectric layer. In particular, the process gas may include a first gas mixture of _N2O and _NH3 mixed in a ratio of from about 8:1 to about 1:8 and DCS mixed in a ratio of from about 1:7 to about 7:1 and NH ₃ and can be introduced at a flow rate from about 5 standard cubic centimeters per minute (sccm) to about 200 sccm per minute. It has been found that an oxynitride layer produced or deposited under these conditions results in a silicon-rich, oxygen-rich first nitride layer.

Next, an anti-tunneling layer is formed or deposited on the surface of the first nitride layer (504). As with the tunneling dielectric layer, the anti-tunneling dielectric layer may be formed or deposited by any suitable means, including plasma oxidation processes, in situ water vapor generation (ISSG) processes, or radical oxidation processes. In one embodiment, the radical oxidation process includes flowing hydrogen ( _H2 ) and oxygen ( _O2 ) into a batch processing chamber or furnace to affect the growth of the anti-tunneling layer by oxidizing a portion of the first nitride layer .

A second or oxygen-depleted nitride layer on top of the multilayer charge-trapping region is then formed on the surface of the anti-tunneling layer (506). Using a process gas comprising _N2O , _NH3 , and DCS in a CVD process at a pressure of from about 5 mT to about 500 mT and at a temperature of from about 700 degrees Celsius to about 850 degrees Celsius, and in some embodiments at least about 760 degrees Celsius An oxygen-depleted second nitride layer may be deposited over the anti-tunneling layer at a substrate temperature of 100°C for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas may include a first gas mixture of _N2O and _NH3 mixed in a ratio of from about 8:1 to about 1:8 and DCS mixed in a ratio of from about 1:7 to about 7:1 and NH ₃ and can be introduced at a flow rate from about 5 seem to about 20 seem. It has been found that a nitride layer created or deposited under these conditions results in a silicon-rich, nitrogen-rich, and oxygen-poor second nitride layer, which improves the speed and amount of increase in the initial difference between program and erase voltages Without compromising the rate of charge loss of memory transistors made using embodiments of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the lifetime of the device.

In certain embodiments, using a process gas comprising BTBAS and ammonia (NH ₃ ) mixed in a ratio of from about 7:1 to about 1:7 in a CVD process can make the oxygen-depleted second nitride layer deposited over the tunneling layer to further include selected carbon concentrations to increase the number of traps therein. The selected carbon concentration in the second oxynitride layer may include a carbon concentration of from about 5% to about 15%.

Next, a top blocking oxide layer or top blocking dielectric layer is formed on the surface of the oxygen-lean second nitride layer of the multilayer charge-trapping region (508). As with the tunneling and anti-tunneling dielectric layers, the blocking dielectric layer may be formed or deposited by any suitable means, including plasma oxidation processes, in situ water vapor generation (ISSG) processes, or radical oxidation processes. In one embodiment, the blocking dielectric layer comprises a high temperature oxide (HTO) deposited using a CVD process. Typically, the deposition process involves exposing the substrate 306 to a silicon source (such as monosilane, chlorosilane, or dichlorosilane) and an oxygen-containing gas (such as O ₂ or N ₂ O) for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650°C to about 850°C.

Alternatively, the blocking dielectric layer is formed using an ISSG oxidation process. In one embodiment, hydrogen is heated in an RTP chamber (such as the ISSG chamber described above from Applied Materials) with an oxygen-enriched gas mixture to which from about 0.5% to about 33% hydrogen has been added. ISSG is performed at a pressure of about 8 Torr to about 12 Torr and a temperature of about 1050°C.

It will be appreciated that in either embodiment, the thickness of the second nitride layer may be adjusted or increased, since some of the oxygen-lean second nitride layer will actually be consumed or consumed during the process of forming the blocking dielectric layer. oxidation.

Finally, a high work function gate electrode is formed on and in contact with the blocking dielectric layer (510). The high work function gate electrode comprises formed or deposited according to a low pressure CVD process and has from about to appointment thickness of the doped polysilicon layer. As mentioned above, the polysilicon layer of the high work function gate electrode can be obtained by adding a gas such as phosphine, arsine, diborane or boron difluoride (BF ₂ ) to the CVD chamber during the low pressure CVD process. directly formed or grown as a doped polysilicon layer, or may be doped using an ion implantation process after growth or formation in a CVD process. In either embodiment, the polysilicon layer of the high work function gate electrode is doped at a concentration or dose selected such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8 electron volts (eV) to about 5.3 eV. In an exemplary embodiment ^{, the} polysilicon layer of the high work function gate electrode is implanted with boron ( B ⁺ ) or BF ₂ ions are doped to form N-type (NMOS) memory transistors.

With gate stack fabrication completed, additional processing may take place as known in the art to follow fabrication of a SONOS-type memory device.

In another aspect, the present disclosure also relates to a multi-gate memory transistor comprising a charge-trapping region covering two or more sides of a channel region, or a memory transistor with a multi-gate surface, and a method of fabricating the same , the channel region is formed on (on) or above (above) the substrate surface. Multi-gate devices include both planar and non-planar devices. Planar multi-gate devices (not shown) typically include dual-gate planar devices in which a substantial first layer is deposited to form a first gate beneath a subsequently formed channel region, and a substantial second layer is deposited over it. above to form a second grid. Non-planar multi-gate devices typically include a horizontal or vertical channel region formed on or above a substrate surface and surrounded on three or more sides by gates.

Figure 6A shows one embodiment of a non-planar multi-gate memory transistor comprising a high work function gate electrode. Referring to FIG. 6A, a memory transistor 600, commonly referred to as a finFET, includes a channel region 602 formed from a film or layer of semiconductor material covering a surface 604 on a substrate 606 connected to a source region 608 of the memory transistor. and drain region 610 . The channel region 602 is surrounded on three sides by fins, which form the gate 612 of the device. The thickness of the gate 612 (measured in the direction from the source region to the drain region) determines the effective channel region length of the device. As with the embodiments described above, the channel region 602 may comprise polysilicon or recrystallized polysilicon to form a single crystal channel region. Optionally, where the channel region 602 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystallographic orientation relative to the long axis of the channel region.

According to the present disclosure, the non-planar multi-gate memory transistor 600 of FIG. 6A may include a high work function gate electrode and a multi-layer charge-trapping region. 6B is a cross-sectional view of a portion of the non-planar memory transistor of FIG. 6A , including substrate 606 , channel region 602 , and a portion of gate 612 , showing high work function gate electrode 614 and multilayer charge-trapping region 616 . The gate 612 also includes a tunneling dielectric layer 618 overlying the raised channel region 602 and a blocking dielectric layer 620 overlying the blocking dielectric layer to form the control gate of the memory transistor 600 . The channel region 602 and the gate 612 may be formed directly on the substrate 606 or on an insulating or dielectric layer 622 (eg, a buried oxide layer) formed on or over the substrate.

As in the embodiments described above, the high work function gate electrode 614 comprises formed or deposited according to a low pressure CVD process and has from about to appointment thickness of the doped polysilicon layer. By adding gases such as phosphine, arsine, diborane, or _BF2 , the polysilicon layer of the high work function gate electrode 614 can be directly formed or grown as a doped polysilicon layer, and at a selected concentration or dose Doped such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 614 is doped at a concentration of from about 1e14 cm ⁻² to about 1e16 cm ⁻² .

Referring to FIG. 6B, the multilayer charge trapping region 616 includes at least one lower or bottom oxygen-rich first nitride layer 616a adjacent to the tunneling dielectric layer 618 comprising nitride and an upper surface covering the oxygen-rich first nitride layer. or on top of the oxygen-depleted second nitride layer 616b. Typically, the oxygen-poor second nitride layer 616b comprises a silicon-rich, oxygen-lean nitride layer and contains a majority of the charge traps distributed in the multilayer charge-trapping region, whereas the oxygen-rich first nitride layer 616a comprises a rich Oxygen nitride or silicon oxynitride, and oxygen-rich relative to the oxygen-poor second nitride layer to reduce the number of charge traps therein. By oxygen-rich, it is meant that the concentration of oxygen in the oxygen-rich first nitride layer 616a is from about 15% to about 40%, while the concentration of oxygen in the oxygen-lean second nitride layer 616b is less than about 5%.

In one embodiment, the blocking dielectric 620 also includes an oxide such as HTO to provide an ONNO structure. The channel region 602 and overlying ONNO structure can be formed directly on the silicon substrate 606 and capped with a high work function gate electrode 614 to provide a SONNOS structure.

In certain embodiments (such as the embodiment shown in FIG. 6B ), the multilayer charge-trapping region 616 also includes at least one thin intermediate layer or anti-tunneling layer 616c comprising a dielectric, such as an oxide, which will deplete The oxygen-rich second nitride layer 616b is separated from the oxygen-rich first nitride layer 616a. As mentioned above, the anti-tunneling layer 616c substantially reduces the probability of electron charges accumulating at the boundary of the oxygen-lean second nitride layer 616b during programming from tunneling into the first nitride layer 616a.

As with the embodiments described above, either or both of the oxygen-rich first nitride layer 616a and the oxygen-lean second nitride layer 616b may comprise silicon nitride or silicon oxynitride, and may be formed, for example, by including Formed by a CVD process of _N2O / _NH3 and DCS/ _NH3 gas mixtures at defined ratios and flow rates to provide a silicon-rich and oxygen-rich oxynitride layer. Then, a second nitride layer of the multilayer charge storage structure is formed on the intermediate oxide layer. The oxygen-lean second nitride layer 616b has a different stoichiometric composition of oxygen, nitrogen, and/or silicon than that of the oxygen-rich first nitride layer 616a, and may also be determined by a CVD process using Process gases of DCS/NH ₃ and N ₂ O/NH ₃ gas mixtures in ratios and flow rates are formed or deposited to provide a silicon-rich, oxygen-poor top nitride layer.

In those embodiments that include an oxide-containing intermediate layer or anti-tunneling layer 616c, the anti-tunneling layer may be formed by oxidizing the bottom oxynitride layer to a selected depth using radical oxidation. For example, radical oxidation can be performed at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or at a temperature of 800-900 degrees Celsius using a batch reactor tool. A mixture of _H2 gas and _O2 gas can be utilized at a pressure of 300-500 Torr for a batch process, or at a pressure of 10-15 Torr using a single vapor tool; using a single wafer tool for a period of 1-2 minutes , or use a batch process for periods of 30 minutes - 1 hour.

Finally, in those embodiments that include blocking dielectric 620 that includes an oxide, the oxide may be formed or deposited by any suitable means. In one embodiment, the oxide of blocking dielectric 620 is a high temperature oxide deposited according to a HTO CVD process. Alternatively, the blocking dielectric 620 or blocking oxide layer may be thermally grown, however, it will be appreciated that in this embodiment the top nitride thickness may be adjusted or increased since some of the top nitride is thermally grown It will actually be consumed or oxidized during the process of growing the blocking oxide layer. A third option is to oxidize the second nitride layer to a selected depth using radical oxidation.

A suitable thickness for the oxygen-enriched first nitride layer 616a may be from about to appointment (with certain permissible deviations such as ± ), of which about may be consumed by radical oxidation to form the anti-tunneling layer 616c. A suitable thickness for the oxygen-poor second nitride layer 616b may be at least In some embodiments, the oxygen-depleted second nitride layer 616b may be formed until thick, of which may be consumed by radical oxidation to form blocking dielectric 620 . In some embodiments, the thickness ratio between the oxygen-rich first nitride layer 616a and the oxygen-lean second nitride layer 616b is about 1:1, although other ratios are possible.

In other embodiments, either or both of the oxygen-lean second nitride layer 616b and the blocking dielectric 620 may comprise a high-K dielectric. Suitable high-K dielectrics include: hafnium _- based materials, such as HfSiON, HfSiO, or HfO; zirconium-based materials, such as ZrSiON, ZrSiO, or ZrO; and yttrium-based materials, such as _Y2O3 .

In another embodiment shown in Figures 7A and 7B, the memory transistor may comprise a nanowire channel region formed from a thin film of semiconductor material covering the surface of the substrate, the nanowire channel region connecting the source region of the memory transistor and the drain region. By nanowire channel region it is meant a conductive channel region formed in a thin strip of crystalline silicon material having a maximum of about 10 nanometers (nm) or less and more preferably less than about 6 nm. cross-sectional dimensions.

Referring to FIG. 7A, a memory transistor 700 includes a horizontal nanowire channel region 702 formed from a thin film or layer of semiconductor material on or overlying a surface on a substrate 706 and connected to the source of the memory transistor. region 708 and drain region 710. In the illustrated embodiment, the device has a gate-all-around (GAA) structure in which the nanowire channel region 702 is surrounded on all sides by the gate 712 of the device. The thickness of the gate 712 (measured in the direction from the source region to the drain region) determines the effective channel region length of the device. As with the embodiments described above, the nanowire channel region 702 may comprise polysilicon or recrystallized polysilicon to form a single crystal channel region. Optionally, where the channel region 702 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystallographic orientation relative to the long axis of the channel region.

According to the present disclosure, the non-planar multi-gate memory transistor 700 of FIG. 7A may include a high work function gate electrode and a multi-layer charge-trapping region. 7B is a cross-sectional view of a portion of the non-planar memory transistor of FIG. 7A including a substrate 706, a nanowire channel region 702, and a portion of a gate 712, showing a high work function gate electrode 714 and a multilayer charge-trapping region 716a-716c. Referring to FIG. 7B , the gate 712 also includes a tunneling dielectric layer 718 covering the nanowire channel region 702 and a blocking dielectric layer 720 .

As in the embodiments described above, the high work function gate electrode 714 comprises formed or deposited according to a low pressure CVD process and has from about to appointment thickness of the doped polysilicon layer. By adding gases such as phosphine, arsine, diborane, or _BF2 , the polysilicon layer of the high work function gate electrode 714 can be directly formed or grown as a doped polysilicon layer, and at a selected concentration or dose Doped such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 714 is doped at a concentration of from about 1e14 cm ⁻² to about 1e16 cm ⁻² .

The multilayer charge-trapping regions 716a-716c comprise at least one inner oxygen-rich first nitride layer 716a adjacent to the tunneling dielectric layer 718 containing a nitride and an outer oxygen-lean first nitride layer covering the oxygen-rich first nitride layer. Nitride layer 716b. Typically, the outer second oxygen-poor nitride layer 716b comprises a silicon-rich, oxygen-lean nitride layer and contains the majority of the charge traps distributed in the multilayer charge-trapping region, whereas the oxygen-rich first nitride layer 716a An oxygen-rich nitride or silicon oxynitride is included and is oxygen-rich relative to the outer oxygen-poor second nitride layer to reduce the number of charge traps therein.

In certain embodiments, such as the one shown, the multilayer charge-trapping region 716 also includes at least one thin intermediate layer or anti-tunneling layer 716c comprising a dielectric, such as an oxide, that separates the outer oxygen-poor The second nitride layer 716b is separated from the oxygen-rich first nitride layer 716a. The anti-tunneling layer 716c substantially reduces the probability of electron charges accumulating at the boundary of the outer oxygen-lean second nitride layer 716b during programming from tunneling into the oxygen-rich first nitride layer 716a, which results in less low leakage current.

As with the embodiments described above, either or both of the oxygen-rich first nitride layer 716a and the outer oxygen-poor second nitride layer 716b may comprise silicon nitride or silicon oxynitride, and may, for example Formed by a CVD process comprising _N2O / _NH3 and DCS/ _NH3 gas mixtures at defined ratios and flow rates to provide a silicon-rich and oxygen-rich oxynitride layer. Then, a second nitride layer of the multilayer charge storage structure is formed on the intermediate oxide layer. The outer oxygen-lean second nitride layer 716b has a different stoichiometric composition of oxygen, nitrogen, and/or silicon than that of the oxygen-rich first nitride layer 716a, and may also be used by a CVD process comprising: Process gases of DCS/ _NH3 and _N2O / _NH3 gas mixtures at defined ratios and flow rates are formed or deposited to provide a silicon-rich, oxygen-depleted top nitride layer.

In those embodiments that include an oxide-containing interlayer or anti-tunneling layer 716c, the anti-tunneling layer may be formed by oxidizing the oxygen-rich first nitride layer 716a to a selected depth using radical oxidation. For example, radical oxidation can be performed at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or at a temperature of 800-900 degrees Celsius using a batch reactor tool. A mixture of _H2 gas and _O2 gas can be used at a pressure of 300-500 Torr for a batch process, or at a pressure of 10-15 Torr for a single vapor tool; with a single wafer tool for a duration of 1-2 minutes, Or use a batch process for periods ranging from 30 minutes to 1 hour.

Finally, in those embodiments in which blocking dielectric 720 comprises an oxide, the oxide may be formed or deposited by any suitable means. In one embodiment, the oxide of the blocking dielectric layer 720 is a high temperature oxide deposited according to a HTO CVD process. Alternatively, the blocking dielectric layer 720 or the blocking oxide layer may be thermally grown, however, it will be appreciated that in this embodiment the thickness of the outer oxygen-poor second nitride layer 716b may need to be adjusted or increased , because some of the top nitride will actually be consumed or oxidized during the process of thermally growing the barrier oxide layer.

A suitable thickness for the oxygen-enriched first nitride layer 716a may be from about to appointment (with certain permissible deviations such as ± ), of which about It may be consumed by radical oxidation to form the anti-tunneling layer 716c. A suitable thickness for the outer oxygen-depleted second nitride layer 716b may be at least In some embodiments, the outer oxygen-depleted second nitride layer 716b may be formed until thick, of which It may be consumed by radical oxidation to form blocking dielectric layer 720 . In some embodiments, the ratio of the thicknesses between the oxygen-rich first nitride layer 716a and the outer oxygen-lean second nitride layer 716b is about 1:1, although other ratios are possible.

In other embodiments, either or both of the outer oxygen-lean second nitride layer 716b and the blocking dielectric layer 720 may comprise a high-K dielectric. Suitable high-K dielectrics include: hafnium- _based materials, such as HfSiON, HfSiO, or HfO; zirconium-based materials, such as ZrSiON, ZrSiO, or ZrO; and yttrium-based materials, such as _Y2O3 .

7C shows a cross-sectional view of a vertical string of the non-planar multi-gate device 700 of FIG. 7A arranged in a Bit-Cost scalable or BiCS architecture 726 . Architecture 726 consists of vertical strings or stacks of non-planar multi-gate devices 700, where each device or cell contains a channel region 702 that overlies a substrate 706 and connects the source and drain regions of a memory transistor (not shown in this figure) and has a gate all around (GAA) structure in which the nanowire channel region 702 is surrounded on all sides by the gate 712 . Compared to simple stacking of layers, the BiCS architecture reduces the number of critical lithography steps, resulting in reduced cost per stored bit.

In another embodiment, the memory transistor is or includes a non-planar device comprising a vertical nanowire channel region in or formed from a semiconductor material on a substrate protruding over or from the plurality of conductive semiconductor layers on the substrate. In one version of this embodiment, shown in cross-section in FIG. 8A, the memory transistor 800 comprises a vertical nanowire channel formed as a cylinder of semiconductor material connecting the source region 804 and the drain region 806 of the device. District 802. The channel region 802 is surrounded by a tunneling dielectric layer 808 , a multilayer charge trapping region 810 , a blocking dielectric layer 812 , and a high work function gate electrode 814 overlying the blocking dielectric layer to form the control gate of the memory transistor 800 . Channel region 802 may comprise an annular region in the outer layer of a substantially solid cylinder of semiconductor material, or may comprise an annular layer formed over the cylinder of dielectric fill material. As with the horizontal nanowires described above, the channel region 802 may comprise polysilicon or recrystallized polysilicon to form a single crystal channel region. Optionally, where the channel region 802 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystallographic orientation relative to the long axis of the channel region.

As in the embodiments described above, the high work function gate electrode 814 comprises formed or deposited according to a low pressure CVD process and has from about to appointment thickness of the doped polysilicon layer. By adding gases such as phosphine, arsine, diborane, or _BF2 , the polysilicon layer of the high work function gate electrode 814 can be directly formed or grown as a doped polysilicon layer, and at a selected concentration or dose Doped such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 814 is doped at a concentration of from about 1e14 cm ⁻² to about 1e16 cm ⁻² .

In certain embodiments (such as the embodiment shown in FIG. 8B ), the multilayer charge-trapping region 810 includes at least an inner or oxygen-rich first nitride layer 810 a proximate to the tunneling dielectric layer 808 and an outer or oxygen-poor first nitride layer 810 a. The second nitride layer 810b. Optionally, as in the illustrated embodiment, the oxygen-rich first nitride layer 810a and the oxygen-lean second nitride layer 810b are separated by an intermediate oxide-containing or anti-tunneling layer 810c.

Either or both of the oxygen-rich first nitride layer 810a and the oxygen-lean second nitride layer 810b may comprise silicon nitride or silicon oxynitride, and may be formed, for example, by including N at a defined ratio and flow rate. ₂ O/NH ₃ and DCS/NH ₃ gas mixture CVD process to provide silicon-rich and oxygen-rich oxynitride layer.

Finally, either or both of the oxygen-lean second nitride layer 810b and the blocking dielectric layer 812 may comprise a high-K dielectric, such as HfSiON, HfSiO, HfO, ZrSiON, ZrSiO, _ZrO , or _Y2O3 .

A suitable thickness for the oxygen-enriched first nitride layer 810a may be from about to appointment (with certain permissible deviations such as ± ), of which about The anti-tunneling layer 820 may be consumed by radical oxidation. A suitable thickness for the oxygen-poor second nitride layer 810b may be at least And a suitable thickness for the blocking dielectric layer 812 may be from about

The memory transistor 800 of FIG. 8A can be fabricated using a gate-first approach or a gate-last approach. 9A-9F illustrate a gate-first scheme for fabricating the non-planar multi-gate device of FIG. 8A. 20A-20F illustrate a gate-last scheme for fabricating the non-planar multi-gate device of FIG. 8A.

Referring to FIG. 9A, in a gate-first approach, a first or underlying dielectric layer 902 (such as an oxide) is over a first doped diffusion region 904 (such as a source or drain region) in a substrate 906. form. A high work function gate electrode 908 is formed over the first dielectric layer 902 to form the control gate of the device, and a second or upper dielectric layer 910 is formed over the high work function gate electrode 908 . As with the embodiments described above, the high work function gate electrode 908 can be formed by depositing and/or doping a polysilicon layer having a thickness from about to appointment The thickness and the doping concentration of from about 1e14cm ^-2 to about 1e16cm ^-2 , such that the minimum energy required to remove electrons from the gate electrode is from at least about 4.8eV to about 5.3eV. The polysilicon layer can be deposited as a doped polysilicon layer in a low pressure CVD process by adding gases such as phosphine, arsine, diborane or _BF2 , or can be doped after deposition using an ion implantation process.

The first dielectric layer 902 and the second dielectric layer 910 may be deposited by CVD, radical oxidation, or formed by oxidizing an underlying layer or a portion of the substrate. Typically, the thickness of the high work function gate electrode 908 is from about And the thickness of the first dielectric layer 902 and the second dielectric layer 910 is from about

Referring to FIG. 9B , a first opening 912 is etched through the overlying high work function gate electrode 908 , and the first and second dielectric layers 902 , 910 to the diffusion region 904 in the substrate 906 . Next, tunnel oxide layer 914, charge trapping region 916, and blocking dielectric layer 918 are sequentially deposited in the opening and the overlying dielectric layer 910 is planarized to produce the intermediate structure shown in FIG. 9C.

Although not shown, it will be appreciated that, as in the embodiments described above, the charge-trapping region 916 may comprise a multilayer charge-trapping region comprising at least one underlying layer adjacent to the tunneling dielectric layer 914. Or an oxygen-rich first nitride layer, and an oxygen-poor second nitride layer covering the top of the oxygen-rich first nitride layer. Typically, the oxygen-lean second nitride layer contains a silicon-rich, oxygen-lean nitride layer and contains the majority of the charge traps distributed in the multilayer charge-trapping region, whereas the oxygen-rich first nitride layer contains an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the oxygen-poor second nitride layer to reduce the number of charge traps therein. In certain embodiments, the multilayer charge-trapping region 916 further comprises at least one thin intermediate layer or layer comprising a dielectric, such as an oxide, separating the oxygen-lean second nitride layer from the oxygen-rich first nitride layer. Anti-tunneling layer.

Next, a second or channel region opening 920 is anisotropically etched through tunnel oxide 914, charge trapping region 916, and blocking dielectric 918, FIG. 9D. Referring to FIG. 9E , semiconductor material 922 is deposited in the channel region opening to form a vertical channel region 924 therein. The vertical channel region 924 may comprise an annular region within the outer layer of a substantially solid cylinder of semiconductor material, or, as shown in FIG. 9E , may comprise a separate semiconductor material surrounding a cylinder of dielectric fill material 926. Layer 922.

Referring to FIG. 9F , the surface of the upper dielectric layer 910 is planarized, and a layer 928 of semiconductor material containing a second doped diffusion region 930 (such as a source or drain region) formed therein is deposited on the upper dielectric layer 910. layer above to form the device shown.

Referring to FIG. 10A , in a gate-last scheme, a dielectric layer 1002 (such as an oxide) is formed over a sacrificial layer 1004 on a surface on a substrate 1006, and openings are etched through the dielectric layer and sacrificial layer and the vertical gates formed therein. The channel region 1008. As with the embodiments described above, the vertical channel region 1008 may comprise an annular region in the outer layer of a substantially solid cylinder of semiconductor material 1010, such as polysilicon or monocrystalline silicon, or may comprise a surrounding dielectric fill A cylinder of material (not shown) is a separate layer of semiconducting material. Dielectric layer 1002 may comprise any suitable dielectric material (such as silicon oxide) capable of electrically isolating a subsequently formed high work function gate electrode of memory transistor 800 from an overlying electrically active layer or another memory transistor.

Referring to FIG. 10B , second opening 1012 is etched through dielectric layer 1002 and sacrificial layer 1004 to substrate 1006 , and sacrificial layer 1004 is at least partially etched or removed. Sacrificial layer 1004 may comprise any suitable material that may be etched or removed with high selectivity relative to the materials of dielectric layer 1002 , substrate 1006 , and vertical channel region 1008 . In one embodiment, the sacrificial layer 1004 includes an oxide that can be removed by buffered oxide etching (BOE etching).

Referring to Figures 10C and 10D, tunneling dielectric layer 1014, multilayer charge-trapping regions 1016A-C, and blocking dielectric layer 1018 are sequentially deposited in the openings, and the surface of dielectric layer 1002 is planarized to produce the intermediate layer shown in Figure 10C. structure. As in the embodiments described above, the multilayer charge-trapping layers 1016A-C are split multilayer charge-trapping layers comprising an oxygen-rich first nitride layer 1016A closest to at least an inner portion of the tunneling dielectric layer 1014 and The outer oxygen-depleted second nitride layer 1016B. Optionally, the first and second charge-trapping layers may be separated by an intermediate oxide layer or anti-tunneling layer 1016C.

Next, a high work function gate electrode 1022 is deposited into the second opening 1012 and the surface of the overlying dielectric layer 1002 is planarized to produce the intermediate structure shown in Figure 10E. As with the embodiments described above, the high work function gate electrode 1022 comprises a doped polysilicon layer having a doping concentration of from about 1e14 ^cm to about 1e16 ^cm such that the minimum energy required to remove electrons from the gate electrode is from At least about 4.8eV to about 5.3eV. The polysilicon layer of the high work function gate electrode 1022 is directly grown as a doped polysilicon layer by adding a gas such as phosphine, arsine, diborane or _BF2 to the CVD process. Finally, openings 1024 are etched through gate layer 1022 to form control gates of separate memory devices 1026A and 1026B.

The foregoing descriptions of specific embodiments and examples of the present invention have been presented for purposes of illustration and description, and while the invention has been described and illustrated by certain foregoing examples, it should not be construed as limited thereto. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and many modifications, improvements, and variations are possible within the scope of the invention in light of the teaching set forth above. The scope of the invention is intended to include the generic scope as disclosed herein and as disclosed by the appended claims and their equivalents. The scope of the invention is defined by the claims including known equivalents and equivalents which were not foreseeable at the time of filing this application.

Claims (20)

1. a semiconductor equipment, comprising:

Memory transistor, described memory transistor comprises:

Channel region, described channel region is electrically connected the source area and drain region that are formed in the substrate, and comprises polysilicon;

Oxide-nitride-Nitride Oxide ONNO is stacking, described ONNO is stacking to be disposed on described channel region, and comprising multilayer charge trapping region, described multilayer charge trapping region comprises the first nitride layer of oxygen enrichment and is disposed in the second nitride layer of the oxygen deprivation on described first nitride layer; And

High work function gate electrode, described high work function gate electrode is formed on the surface that described ONNO is stacking.

2. semiconductor equipment as claimed in claim 1, wherein, described raceway groove comprises silicon nanowires.

3. semiconductor equipment as claimed in claim 1, wherein, described channel region comprises the polysilicon of recrystallization.

4. semiconductor equipment as claimed in claim 3, described high work function gate electrode comprises the polysilicon layer of P+ doping.

5. semiconductor equipment as claimed in claim 4, wherein, described ONNO is stacking also comprises barrier dielectric layer, described barrier dielectric layer is disposed on described multilayer charge trapping region, and wherein said barrier dielectric layer comprises dielectric, described dielectric comprises high K high-temperature oxide HTO.

6. semiconductor equipment as claimed in claim 1, also comprise metal-oxide semiconductor (MOS) MOS logic transistor over the substrate, wherein said MOS logic transistor comprises gate oxide and high work function gate electrode.

7. semiconductor equipment as claimed in claim 6, wherein, the high work function gate electrode of described memory transistor and the high work function gate electrode of described MOS logic transistor all comprise the polysilicon layer of N+ doping with the logic transistor of the silicon-oxide-nitride--oxide-silicon SONOS memory transistor and N-type (NMOS) that form P type (PMOS).

8. semiconductor equipment as claimed in claim 6, wherein, the high work function gate electrode of described memory transistor and the high work function gate electrode of described MOS logic transistor all comprise the polysilicon layer of P+ doping with the logic transistor of the silicon-oxide-nitride--oxide-silicon SONOS memory transistor and P type (NMOS) that form N-type (NMOS).

9. semiconductor equipment as claimed in claim 6, wherein, the high work function gate electrode of described memory transistor and the high work function gate electrode of described MOS logic transistor are all formed by the polysilicon layer of the doping of single patterning.

10. semiconductor equipment as claimed in claim 1, wherein, described multilayer charge trapping region also comprises anti-tunnel layer, and described anti-tunnel layer comprises the oxide separated with described second nitride layer by described first nitride layer.

11. 1 kinds of semiconductor equipments, comprising:

Memory transistor, described memory transistor comprises:

Channel region, described channel region is electrically connected the source area and drain region that are formed in the substrate, and comprises polysilicon;

Oxide-nitride-Nitride Oxide ONONO is stacking, and described ONONO is stacking to be disposed on described channel region, comprising:

Tunnel dielectric layer, described tunnel dielectric layer is arranged on described channel region;

Multilayer charge trapping region, described multilayer charge trapping region comprises the first nitride layer of the oxygen enrichment be disposed on described tunnel dielectric layer, the second nitride layer being disposed in the oxygen deprivation on described first nitride layer and anti-tunnel layer, and described anti-tunnel layer comprises the oxide separated with described second nitride layer by described first nitride layer; And

Barrier dielectric layer, described barrier dielectric layer is disposed on described multilayer charge trapping region; And

High work function gate electrode, described high work function gate electrode is disposed on the stacking surface of described ONONO.

12. semiconductor equipments as claimed in claim 11, wherein, described channel region comprises the polysilicon of recrystallization.

13. semiconductor equipments as claimed in claim 12, wherein, described high work function gate electrode comprises the polysilicon layer of P+ doping.

14. semiconductor equipments as claimed in claim 13, wherein, described barrier dielectric layer comprises dielectric, and described dielectric comprises high K high-temperature oxide HTO.

15. semiconductor equipments as claimed in claim 11, wherein, described raceway groove comprises silicon nanowires.

16. semiconductor equipments as claimed in claim 11, wherein, described high work function gate electrode comprises the polysilicon layer of P+ doping.

17. semiconductor equipments as claimed in claim 11, also comprise metal-oxide semiconductor (MOS) MOS logic transistor over the substrate, wherein said MOS logic transistor comprises gate oxide and high work function gate electrode.

18. 1 kinds of semiconductor equipments, comprising:

Memory transistor, described memory transistor comprises:

Vertical-channel, described vertical-channel comprises polysilicon, and extends to from the first diffusion region formed on a surface of the substrate the second diffusion region formed on the surface of described substrate, described vertical-channel described first diffusion region of electrical connection and described second diffusion region;

Oxide-nitride-Nitride Oxide ONNO is stacking, and described ONNO is stacking to be disposed in around described vertical-channel, comprising:

Tunnel dielectric layer, described tunnel dielectric layer adjoins described vertical-channel;

Multilayer charge trapping region, described multilayer charge trapping region comprises the first nitride layer and the second nitride layer, described first nitride layer comprises the nitride of oxygen enrichment, adjacent described tunnel dielectric layer, described second nitride layer comprise the oxygen deprivation of Silicon-rich nitride, cover described first nitride layer; And

Barrier dielectric layer, described barrier dielectric layer covers described multilayer charge trapping region; And

High work function gate electrode, described high work function gate electrode is disposed in the stacking surrounding of described ONONO, adjacent described barrier dielectric layer.

19. semiconductor equipments as claimed in claim 18, also comprise metal-oxide semiconductor (MOS) MOS logic transistor over the substrate, wherein said MOS logic transistor comprises gate oxide and high work function gate electrode.

20. semiconductor equipments as claimed in claim 18, wherein, described multilayer charge trapping region also comprises anti-tunnel layer, and described anti-tunnel layer comprises the oxide separated with described second nitride layer by described first nitride layer.