CN104766887B - Electronic circuit including MOSFET and bigrid JFET - Google Patents
Electronic circuit including MOSFET and bigrid JFET Download PDFInfo
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- CN104766887B CN104766887B CN201510002272.XA CN201510002272A CN104766887B CN 104766887 B CN104766887 B CN 104766887B CN 201510002272 A CN201510002272 A CN 201510002272A CN 104766887 B CN104766887 B CN 104766887B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
- H10D30/615—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel comprising a MOS gate electrode and at least one non-MOS gate electrode
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Provide the electronic circuit and method of the various applications for including signal amplification.A kind of example electronic circuit includes MOSFET and bigrid JFET in cascode configuration in FIG.Bigrid JFET includes the top grid and bottom grid being arranged in above and below channel.The top grid of JFET is controlled by the signal of the signal of the grid dependent on control MOSFET.The control of the bottom grid of JFET may rely on or independently of top grid control.MOSFET and JFET may be implemented as the isolated component of the size with different such as grid widths etc on the same substrate.
Description
Cross reference to related applications
The application is the U.S. Patent application No.13/803 submitted on March 13rd, 2013,792 continuation-in-part application,
U.S. Patent application No.13/803,792 be submit on April 10th, 2012 U.S. Patent application No.13/433,611 (now for
On March 19th, 2013 bulletin United States Patent (USP) No.8,400,222) continuation-in-part application, U.S. Patent application No.13/
433,611 be submit on May 13rd, 2011 U.S. Patent application No.13/107,411 (now be on May 15th, 2012 bulletin
United States Patent (USP) No.8,179,197) continuation application case, U.S. Patent application No.13/107,411 be to mention on January 13rd, 2010
The U.S. Patent application No.12/686,573 of friendship is (now for the United States Patent (USP) No.7,969,243's of bulletin on June 28th, 2011)
Divisional application, above-mentioned all name of patent application are " Electronic Circuits including a MOSFET and
a Dual-Gate JFET"；U.S. Patent application No.12/686,573 requires to submit on April 22nd, 2009 entitled
“Electronic Circuits including a MOSFET and a Dual-Gate JFET and having a
The equity of the U.S. Provisional Patent Application No.61/171,689 of High Breakdown Voltage "；Each above-mentioned patent application
It is incorporated herein by reference herein.Entitled " the Electronic Circuits that the application also requires on January 3rd, 2014 to submit
The power of the U.S. Provisional Patent Application No.61/923,578 of including a MOSFET and a Dual-Gate JFET "
Benefit, this application is also by being incorporated herein by reference.The application also on 2 13rd, the 2008 entitled " High submitted
The U.S. Patent application No.12/070 of Breakdown Voltage Double-gate Semiconductor Device ",
019 (being now the United States Patent (USP) No.7 of bulletin on January 4th, 2011,863,645) is related, is incorporated into this also by reference herein
Text.
Technical field
Present invention relates in general to semiconductor devices, and relate more specifically to the semiconductor device for being configured to power application
Part.
Background technique
Complementary metal oxide semiconductor (CMOS) device designed for radio frequency (RF) power application is traditionally
It is required that the compromise between improved RF performance and higher breakdown voltage.For example, can be by reducing grid geometric dimension (example
Such as, by using short channel length) the RF performance of Lai Gaishan cmos device.However, smaller grid geometric dimension reduces CMOS
The breakdown voltage of device.Because obtained by reduced breakdown voltage is limited at the output of the cmos device in amplifier configuration
Voltage swing, so this cmos device use in power application is smaller.
In a kind of method for handling break-down voltage problem, cmos device can be designed to have lower voltage swing
The bigger electric current driving of width.However, bigger electric current driving may it is required that the transistor in cmos device width compared with
Greatly, therefore to driving circuit unexpected capacity load is presented.
The method of another kind processing break-down voltage problem uses lateral diffusion metal oxide semiconductor (LDMOS) crystal
Pipe.Ldmos transistor has the drift region between active area and drain electrode.Drift region is lightly doped and undergoes maximum voltage
The amplitude of oscillation.Because the doping concentration in drift region is limited by breakdown voltage requirement, LDMOS device sacrifices higher breakdown voltage
And bring the higher all-in resistance (referred to as on-state resistance) of the drain current flowed between drain electrode and source terminal.
The method of another kind processing break-down voltage problem, which uses, has thicker and more high resistivity substrate device.This
A little devices can provide the performance of higher voltage, but be also introduced into higher on state loss.These devices include reducing table
Face (RESURF) device, wherein the depletion region of the depletion region and transverse diode of substrate diode interacts to reduce surface
?.In these devices, breakdown voltage is increased due to the lateral broadening of depletion region.
Accordingly, there exist the high-breakdown-voltage of improved RF performance and higher power is provided compared to traditional semiconductor devices
The needs of semiconductor devices.
Summary of the invention
The present invention provides the various electronic circuits being used as amplifying the power amplifier of input signal.Exemplary circuit includes
MOSFET and JFET, the two all include source electrode and drain electrode, and wherein the source electrode of JFET is directly coupled to the drain electrode of MOSFET.MOSFET
It also include grid, while JFET also includes both top grid and bottom grid.In some embodiments, MOSFET and JFET
Grid has different width.In various embodiments, the top of the source electrode and drain electrode of both MOSFET and JFET and JFET
Grid and bottom grid are limited in substrate, while the grid of MOSFET is arranged on substrate.In some instances, substrate
Including having the SOI wafer of the silicon layer on insulator layer, and in these embodiments, it is limited in substrate
Feature be limited in silicon layer.
In various embodiments, the top grid of JFET is coupled to the grid of MOSFET.In these embodiments one
In a little embodiments, the bottom grid of JFET is also coupled to the grid of MOSFET, and some implementations in these embodiments
In example, the top grid and bottom grid of JFET is coupled to DC bias source.
In the various embodiments of exemplary circuit, the top grid of JFET is coupled to the bottom grid of JFET, and two
A grid is independently of each the grid of MOSFET.In some of these embodiments, the top grid of JFET and bottom
Grid is coupled to DC bias source, and in some other embodiment in these embodiments, the top grid of JFET and bottom
Portion's grid be coupled to (ground).In other embodiments again in these embodiments, the top grid quilt of JFET
The bottom grid for being coupled to the first DC bias source and/or JFET is coupled to the 2nd DC bias source or ground.
The present invention also relates to various devices.Example device includes the transceiver for being coupled to power amplifier described above.
In various embodiments, transceiver is configured to produce the signal with frequency in the range of about 700MHz to about 2.5GHz
Or generate the signal with frequency in the range of about 150MHz to about 6GHz.In some embodiments, transceiver is by cloth
It sets on substrate identical with MOSFET and JFET.Various embodiments further comprise the output matching for the drain electrode for being coupled to JFET
Circuit.
Further, the present invention also provides the method for signal amplification.Exemplary method includes being controlled with the first signal
The grid of MOSFET, the top grid with second signal control JFET and the bottom grid with third signal control JFET,
Middle JFET is in be configured with the cascade (cascode) of MOSFET.In various embodiments, second signal is dependent on the first letter
Number and some of these embodiments in, third signal depend on second signal.Similarly, in various embodiments
In, for second signal independently of in the first signal and some of these embodiments, third signal depends on second
Signal.
Invention further provides the methods of production electronic circuit.Exemplary method includes providing to have in insertion chip
The SOI wafer of silicon layer on insulator layer, such as by ion implanting by the MOSFET including source electrode and drain electrode
It is limited in the silicon of chip, the JFET including source electrode, drain electrode, top grid and bottom grid is limited in the silicon of chip, with
And the grid of MOSFET is such as formed on silicon by photoetching.In various embodiments, this method further comprise to be formed with
The metal layer of drain electrode all telecommunications of the source electrode and MOSFET of JFET, so that the source electrode of JFET is directly coupled to the leakage of MOSFET
Pole.
Another exemplary circuit of the invention includes the MOS device formed in the substrate substantially.The substrate includes being limited to lining
The first trap in bottom, wherein trap is characterized in that for example being formed by top surface by planarizing substrate.It is limited in trap
Be bottom grid, the first channel being limited between bottom grid and top surface, first drain electrode, first drain electrode and source electrode it
Between second drain electrode, first drain electrode second drain electrode between first grid and source electrode and second drain electrode between
Gap.MOS device further comprises the top surface top for being arranged in the first trap and dielectric layer and arrangement with gap alignment
Square second grid on the dielectric layer.In example MOS device, first grid controls the first channel, second grid control
The second channel being arranged in the first trap.First channel and the second channel are differently adulterated, so that when a channel is doped
When for N-shaped, another channel is doped to p-type.
The various embodiments of example MOS device also include the two side walls limited in the first trap, so that two side walls
It is connected to bottom grid.Second trap is by being enclosed body between two side walls and between bottom grid and top grid
Product is limited in the first trap.In one configuration, a side wall in two side walls is disposed in first grid and second gate
Between pole, so that the first source electrode, second grid and the second drain electrode include being in third trap in the side of a side wall
MOSFET.In these embodiments, the first trap also includes being defined in therein to be arranged in one between side wall and first grid
Second source electrode.In these embodiments, the second source electrode, first grid and first drain all in the second trap, and and bottom
Grid and the first channel constitute bigrid JFET together.In these embodiments, a side wall is disposed in the second source electrode and
Between two drain electrodes, and therefore MOSFET and JFET is (all by being limited to conductive path above top surface from the second drain electrode
As arranged metal trace on substrate) it is electrically coupled to the second source electrode.In these embodiments, one or two side walls can
To have doping identical with bottom grid.At least one side wall is exposed at top surface, to allow voltage to be applied to
Bottom grid.
In another configuration, two side walls are arranged such that the first source electrode, the first drain electrode and the second drain electrode, the first grid
Pole and the first channel are all disposed in the second trap.These embodiments do not include the second source electrode, do not include third trap yet.Phase
Instead, the first channel offes telex between the second drain electrode and the first drain electrode and leads and controlled by first grid, is arranged in the second trap
The second interior channel offes telex between the first source electrode and the second drain electrode and leads and controlled by second grid.In these embodiments
In, the second channel is disposed between bottom grid and second grid.Note that the first channel and the second channel be doped so that
When a channel is doped to N-shaped, another channel is doped to p-type, therefore, in these embodiments, the second trap it is opposite
Side is doped to that side is N-shaped and the other side is p-type, at the boundary interface that they extend between the second drain electrode and bottom grid
It meets.
Detailed description of the invention
For simple and clear and in pictorial image element, and the element in figure is not to scale.Some members
The size of part may be exaggerated to help improve the understanding of various embodiments of the present invention relative to other elements.
Fig. 1 illustrates according to an embodiment of the invention including mos gate pole, junction gate and two neighbouring areas N+
Double-gate semiconductor devices illustrated section.
It includes mos gate pole, junction gate and being coupled using conductive layer that Fig. 2, which is illustrated according to an embodiment of the invention,
The area Liang Ge N+ double-gate semiconductor devices illustrated section.
Fig. 3, which is illustrated, according to an embodiment of the invention to be included mos gate pole, junction gate and is arranged in mos gate pole
The illustrated section of the double-gate semiconductor devices in the single area N+ between junction gate.
The bigrid that Fig. 4 is illustrated in Fig. 3 in this second mode of operation according to an embodiment of the invention is partly led
Body device example section.
Fig. 5 illustrates double-gate semiconductor devices of the Fig. 1 according to an embodiment of the invention into Fig. 3 and Fig. 6
Exemplary circuit figure.
Fig. 6 illustrates the double-gate semiconductor according to an embodiment of the invention including mos gate pole and junction gate
The illustrated section of device.
Fig. 7 provides the example electronic circuit according to an embodiment of the invention including MOSFET and bigrid JFET
Circuit diagram.
Fig. 8 A, 8B and 8C are the section of the example electronic circuit of three embodiments according to the present invention, each exemplary electron
Circuit includes MOSFET and bigrid JFET, and wherein MOSFET and JFET are different.
It includes that MOSFET and the several of bigrid JFET show that Fig. 9 to Figure 15, which is provided according to various embodiments of the present invention,
The circuit diagram of example electronic circuit.
Figure 16 is provided for using MOSFET in cascode configuration in FIG and bigrid JFET to carry out showing for amplified signal
The flow chart of example method indicates.
Figure 17 is the section view of MOS device according to one example embodiment.
Figure 18 is the section view of the MOS device of another example embodiment according to the present invention.
Specific embodiment
This disclosure relates to double-gate semiconductor devices, it is characterised in that allow the big drift of output voltage
(excursion) high-breakdown-voltage, making these semiconductor devices is useful for the power application of such as power amplification.?
Double-gate semiconductor devices disclosed herein include metal-oxide semiconductor (MOS) (MOS) grid and junction gate, wherein junction type
The biasing of grid can be the function of the grid voltage of mos gate pole.The breakdown voltage of this double-gate semiconductor devices is mos gate
The summation of the breakdown voltage of pole and junction gate.Because individual junction gate has inherently high breakdown voltage, double
The breakdown voltage of gate semiconductor device is higher than the breakdown voltage of individual mos gate pole.
Compared with traditional complementary metal oxide semiconductor (CMOS) device, in addition to operating in higher power level
Property except, double-gate semiconductor devices provide improved RF performance.Semiconductor fabrication techniques known in the art, base can be used
In sheet on substrate and/or middle production double-gate semiconductor devices, and can be used have it is tiny in process flow
The standard manufacture craft for CMOS and logical device of modification.
Mos gate pole may include metal-oxide-semiconductor structure.When voltage is applied to mos gate pole, which is repaired
Change distribution of charges in the semiconductor structure, therefore controls the conductive features of semiconductor structure.Therefore mos gate can extremely rise is used as
The grid or switch of electric control.The grid of the type can be found in metal oxide semiconductor field effect tube (MOSFET).
Junction gate includes the region of the channel of the semiconductor material with the doping feature opposite with remaining region of channel, so that working as
When voltage is applied to junction gate, the distribution of charges in channel is modified and thus controls the conductive features of channel.Junction type
Therefore grid can serve as the grid or switch of electric control.The grid of the type can be looked in technotron (JFET)
It arrives.The effective resistance of junction gate is by the resistance of the voltage-controlled channel of junction gate.
Double-gate semiconductor devices disclosed herein can be made as including between mos gate pole and junction gate
One or more injection region.With the embodiment for including one or more injection region between mos gate pole and junction gate
It compares, the embodiment without the injection region between mos gate pole and junction gate can provide for double-gate semiconductor devices
Higher space density configuration.The principle of the operation of these various embodiments be it is similar, in addition in mos gate pole channel and drift
Except depletion region between area is modified.
Fig. 1 illustrates the double-gate semiconductors for including mos gate pole, junction gate and two neighbouring areas N+ (i.e. injection region)
The illustrated section of device.Double-gate semiconductor devices 100 can be used semiconductor fabrication techniques known in the art by doped silicon,
Polysilicon, the area of metal and insulating layer and/or floor are formed.It will be appreciated that as used herein term " oxide skin(coating) " is this
The term in field refers to any suitable insulating layer as the barrier layer in MOS device, regardless of whether it includes oxygen.The term
Appearance is because the layer is traditionally formed by silica, but in recent years, having changed into can also be by such as low K dielectrics material
The other materials production of material etc, some of them do not include oxygen.
Double-gate semiconductor devices 100 include P- substrate 110, the N- trap 120 formed in P- substrate 110, N+ source electrode
130, grid 140, oxide skin(coating) 150, the area N+ 160, the area N+ 162, P+ grid 170 and N+ drain electrode 180.As used herein
Like that, "+" symbol indicates the strong doping (for example, N+ instruction N-type is adulterated by force) of indicated conduction type, and the instruction of "-" symbol is signified
Show the weak doping (for example, P- indicates p-type weak doping) of conduction type.
Such as Vg1With control voltage Vg2Etc electric signal can be respectively coupled to grid 140 and P+ grid 170.?
Semiconductor fabrication techniques known in the art can be used, leaked using being arranged in N+ source electrode 130, the area N+ 160, the area N+ 162 and N+
Electric signal is coupled to the source N+ by the additional polysilicon layer (not shown) or metal layer (not shown) in pole 180 on each surface
Pole 130, the area N+ 160, the area N+ 162 and N+ drain electrode 180.
Double-gate semiconductor devices 100 include by P- substrate 110, N+ source electrode 130 and the area N+ 160, grid 140 and oxidation
The N-type MOS field effect transistor (also referred to as N-channel MOS FET) that nitride layer 150 is formed.Double-gate semiconductor devices 100 also include
The N-channel junction field effect transistor formed by P- substrate 110, N- trap 120, the area N+ 162, P+ grid 170 and N+ drain electrode 180
(also referred to as N-type JFET).In this embodiment, the area N+ 160 and the area N+ 162 are neighbouring and the area N+ 162 is substantially arranged
In N- trap 120.
Alternatively, the element of double-gate semiconductor devices 100 can be configured so that double-gate semiconductor devices 100 wrap
P-type mos gate pole is included, p-type mos gate pole includes P-channel junction gate.In such an embodiment, according to known in the art
Manufacturing technology, the area of doped silicon and/or some in floor can have different doping.
Double-gate semiconductor devices 100 may be considered that operation in both of which.The first mode illustrated in Fig. 1, by Vg1>
Threshold voltage VthWith | Vg2-VPI| ≈ 0 is (that is, Vg2-VPIAbsolute value be about 0) indicate.Vg1It is the voltage at grid 140, Vg2It is P
Voltage at+grid 170, VthIt is the threshold voltage and V for grid 140PIIt is the voltage at the area N+ 162.In the first mould
In formula, it is greater than VthVoltage Vg1It is applied to grid 140, so that mos gate pole is " conducting ".Control voltage Vg2It is applied
To P+ grid 170, so that junction gate is utilized in control voltage Vg2With the voltage V in the area N+ 162PIBetween low potential difference into
Row biasing.Therefore P+ grid 170 low resistance, R is presented to electric current flowingon.In the first mode, semiconductor devices 100 is in N+
Electric current is conducted between source electrode 130 and N+ drain electrode 180.In a second mode, 100 non-conducting electric current of semiconductor devices.
Return to Fig. 1, in a second mode, negative control voltage Vg2It is applied under P+ grid 170 and P+ grid 170
Depletion region extend in the channel (not shown) in N- trap 120.As the control voltage V for being applied to P+ grid 170g2So that |
Vg2-VPI| it is greater than pinch-off voltage VoffWhen, the channel under P+ grid 170 is completely depleted and drains in the area N+ 162 and N+
There is no electric current flowing between 180.Similarly, in a second mode, there is no electric current stream between N+ source electrode 130 and N+ drain electrode 180
It is dynamic.
As control voltage Vg2Be applied to P+ grid 170 so that | Vg2-VPI| when ≈ 0 (corresponding to first mode), channel
It is open and the electric current of majority carrier can flow between the area N+ 162 and N+ drain electrode 180.Therefore, P+ grid 170
(junction gate) can equally show as variable resistance, wherein when | Vg2-VPI|>VoffWhen, there is high effective resistance
Roff, effective resistance RoffAllow seldom or flowed between N+ source electrode 130 and N+ drain electrode 180 without electric current, and work as | Vg2-
VPI| when ≈ 0, there is the low effective resistance R for allowing maximum current to flowon。
Double-gate semiconductor devices 100 may include having two grid device, wherein at P+ grid 170 (junction gate)
Control voltage Vg2It can be the voltage V at grid 140 (mos gate pole)g1Function.Mos gate pole and junction gate can be used
The control circuit device with reference to described in Fig. 5 is all by dynamically biasing is in " conducting " or " shutdown " state simultaneously.
High effective resistance R in the second operating modeoffP+ grid 170 is allowed to bear high voltage and by grid 140
Voltage potential between the area N+ 160 is restricted to be less than mos gate pole breakdown voltage.Because double-gate semiconductor devices 100 are hit
The summation that voltage is the breakdown voltage of mos gate pole and P+ grid 170 is worn, so the inherently high breakdown voltage of P+ grid 170
The high breakdown voltage of double-gate semiconductor devices 100 is provided.
Control voltage Vg2Control circuit device can be used to adjust and dependent on pinch-off voltage Voff.Control circuit device
It may include the capacitor (not shown) for being configured to for the RF signal from grid 140 being coupled to P+ grid 170.In order to limit grid
The distance between pole 140 and P+ grid 170, capacitor can be used in multiple-level stack parallel between grid 140 and P+ grid 170
Metal layer realize.
Fig. 2 illustrates the double-gate semiconductor including mos gate pole, junction gate and the area Liang Ge N+ coupled using conductive layer
The illustrated section of device.Double-gate semiconductor devices 200 can be used semiconductor fabrication techniques known in the art by doped silicon,
Polysilicon, the area of metal and insulating layer and/or floor are formed.
Double-gate semiconductor devices 200 include P- substrate 110, the N- trap 120 formed in P- substrate 110, N+ source electrode
130, grid 140, oxide skin(coating) 150, the area N+ 260, the area N+ 262, conductive layer 265, P+ grid 170 and N+ drain electrode 180.It is conductive
Layer 265 can be polysilicon layer, metal layer or another conductive layer as known in the art.As illustrated in Figure 2 like that, N+
Area 260 and the area N+ 262 are separated by the area of P- substrate 110, and the area N+ 262 is substantially disposed in N- trap 120.
As discussed herein, about double-gate semiconductor devices 200, electric signal (such as Vg1With control voltage
Vg2) grid 140 and P+ grid 170 can be respectively coupled to.Also can be used semiconductor fabrication techniques as known in the art,
Use the additional polysilicon layer being arranged on surface each in N+ source electrode 130, the area N+ 260, the area N+ 262 and N+ drain electrode 180
Electric signal is coupled to N+ source electrode 130, the area N+ 260, the area N+ 262 and N+ drain electrode 180 by (not shown) or metal layer (not shown).
Double-gate semiconductor devices 200 include by P- substrate 110, N- trap 120, N+ source electrode 130 and the area N+ 260, grid
140 and oxide skin(coating) 150 formed N-type MOSFET.Double-gate semiconductor devices 200 also include by P- substrate 110, N- trap
120, the N-channel JFET that the area N+ 262, P+ grid 170 and N+ drain electrode 180 are formed.In this embodiment, the area N+ 260 and the area N+ 262
Conductive layer 265 is used to couple.
Alternatively, the element of double-gate semiconductor devices 200 can be configured so that double-gate semiconductor devices 200 wrap
It includes: the p-type mos gate pole including P-channel junction gate or the N-type mos gate pole including P-channel junction gate or including N ditch
The p-type mos gate pole of road junction gate.In this embodiment, according to semiconductor fabrication techniques known in the art, the area of doped silicon
And/or some in layer can have different doping.
Double-gate semiconductor devices 200 may be considered that as similarly operated herein in regard to both of which described in Fig. 1.
First mode is by Vg1> threshold voltage VthWith | Vg2-VPI| ≈ 0 indicates, wherein VPIIt is the voltage at the area N+ 262.In first mode
In, it is greater than VthVoltage Vg1Grid 140 is applied to so that mos gate pole is " conducting ".Control voltage Vg2It is applied to P+
Grid 170 is so that junction gate is utilized in control voltage Vg2With the voltage V in the area N+ 262PIBetween that there is low potential difference to carry out is inclined
It sets.Therefore low resistance R is presented for electric current flowing in P+ grid 170on.In the first mode, semiconductor devices 200 is in N+ source electrode
Electric current is conducted between 130 and N+ drain electrode 180.In a second mode, 200 non-conducting electric current of semiconductor devices.
As control voltage Vg2Be applied to P+ grid 170 so that | Vg2-VPI| when ≈ 0 (corresponding to first mode), channel
It is open and the electric current of majority carrier can flow between the area N+ 262 and N+ drain electrode 180.Therefore, P+ grid 170
(junction gate) can equally show as variable resistance, when | Vg2-VPI|>VoffWhen, having allows seldom or without electricity
Flow the high effective resistance R flowed between N+ source electrode 130 and N+ drain electrode 180off, and work as | Vg2-VPI| having when ≈ 0 allows maximum
The low effective resistance R of electric current flowingon。
Double-gate semiconductor devices 200 may include having two grid device, wherein at P+ grid 170 (junction gate)
Control voltage Vg2It can be the function of the voltage at grid 140.Mos gate pole and junction gate, which can use, refers to Fig. 5 institute
The control circuit device of description is by dynamically biasing is in " conducting " status or " shutdown " state simultaneously.Control circuit device can
With include be configured to as described with reference to fig. 1 the RF signal from grid 140 is coupled to the capacitor of P+ grid 170 (not
It shows).
In this second mode of operation, high effective resistance RoffP+ grid 170 is allowed to bear high voltage and by grid 140 and N
Voltage potential between+area 260 is restricted to the breakdown voltage less than mos gate pole.Because of the breakdown of double-gate semiconductor devices 200
Voltage is the summation of the breakdown voltage of mos gate pole and P+ grid 170, so the inherently high voltage offer of P+ grid 170 is double
The high-breakdown-voltage of gate semiconductor device 200.
Fig. 3 is illustrated including mos gate pole and junction gate and the single area N+ being arranged between mos gate pole and junction gate
Double-gate semiconductor devices illustrated section.Semiconductor system known in the art can be used in double-gate semiconductor devices 300
Make technology to be formed by the area and/or floor of doped silicon, polysilicon, metal and insulating layer.Double-gate semiconductor devices 300 include P-
Substrate 110, the N- trap 120 formed in P- substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, the area N+ 360, P+ grid
Pole 170 and N+ drain electrode 180.As illustrated in Figure 3 like that, the area N+ 360 is substantially disposed in N- trap 120.
As referring to figs. 1 to described in Fig. 2, electric signal (such as Vg1With control voltage Vg2) can be coupled respectively
To grid 140 and P+ grid 170.Also semiconductor fabrication techniques known in the art can be used, using being arranged in N+ source electrode
130, the additional polysilicon layer (not shown) or metal layer (not shown) in the area N+ 360 and N+ drain electrode 180 on each surface
Electric signal is coupled to N+ source electrode 130, the area N+ 360 and N+ drain electrode 180.
Double-gate semiconductor devices 300 include the N-type MOS formed by P- substrate 110, grid 140 and oxide skin(coating) 150
Grid.Double-gate semiconductor devices 300 also include being drained by P- substrate 110, N- trap 120, the area N+ 360, P+ grid 170 and N+
The 180 N-channel JFET formed.In this embodiment, the area N+ 360 is source electrode and the adjoining N-type mos gate pole of N-channel JFET, N
Type mos gate pole includes grid 140 and oxide skin(coating) 150.
Double-gate semiconductor devices 300 may be considered that as herein in regard to both of which described in Fig. 1 to Fig. 2 similarly
Operation.First mode is by Vg1> threshold voltage VthWith | Vg2-VPI| ≈ 0 indicates, wherein VPIIt is the voltage at the area N+ 360.First
In mode, it is greater than VthVoltage Vg1It is applied to grid 140, so that mos gate pole is " conducting ".Control voltage Vg2It is applied
It is added to P+ grid 170, so that junction gate is utilized in control voltage Vg2With the voltage V in the area N+ 360PIBetween low potential it is poor
It is biased.Therefore low resistance R is presented for electric current flowing in P+ grid 170on.In the first mode, semiconductor devices 200 is in N+
Electric current is conducted between source electrode 130 and N+ drain electrode 180.In a second mode, 200 non-conducting electric current of semiconductor devices.
As control voltage Vg2Be applied to P+ grid 170 so that | Vg2-VPI| when ≈ 0 (corresponding to first mode), channel
It is open and the electric current of majority carrier can flow between the area N+ 360 and N+ drain electrode 180.Therefore, P+ grid 170
(junction gate) can equally show as variable resistance, when | Vg2-VPI|>VoffWhen, having allows seldom or without electricity
Flow the high effective resistance R flowed between N+ source electrode 130 and N+ drain electrode 180off, and work as | Vg2-VPI| allow maximum current when ≈ 0
The low effective resistance R of flowingon。
As referring to figs. 1 to described in Fig. 2, double-gate semiconductor devices 300 are considered with bigrid
Device, the wherein control voltage V at P+ grid 170 (junction gate)g2It can be the voltage V at grid 140g1Function.
Mos gate pole and junction gate can dynamically be biased to be in simultaneously using the control circuit device with reference to described in Fig. 5 " to be led
It is logical " state or " shutdown " state.Control circuit device may include be configured to as described with reference to fig. 1 will come from grid
140 RF signal is coupled to the capacitor (not shown) of P+ grid 170.
In this second mode of operation, high effective resistance RoffP+ grid 170 is allowed to bear high voltage and by grid 140 and N
Voltage potential between+area 360 is restricted to the breakdown voltage less than mos gate pole.Because of the breakdown of double-gate semiconductor devices 300
Voltage is the summation of the breakdown voltage of mos gate pole and P+ grid 170, so the inherently high voltage offer of P+ grid 170 is double
The high-breakdown-voltage of gate semiconductor device 300.
Fig. 4 illustrates the illustrated section of the double-gate semiconductor devices 300 of Fig. 3 in this second mode of operation.Second
The description herein of double-gate semiconductor devices 300 in operation mode is applied similarly to respectively referring to figs. 1 to described by Fig. 2
Double-gate semiconductor devices 100 and 200 second operator scheme.
In this second mode of operation, it is applied to the voltage V of grid 140g1Lower than threshold voltage Vth, so that mos gate pole is
" shutdown ".Control voltage Vg2It is applied to P+ grid 170, so that junction gate is by using Vg2With the voltage in the area N+ 360
VPIBetween high potential difference be biased in pinch-off voltage VoffNear.Therefore P+ grid 170 (schemes drift region in such as Fig. 4
The drift region 420 shown) electric current flowing high effective resistance R is presentedoff.High effective resistance RoffBy under P+ grid 170 and all
The depletion region (all depletion regions 410 as illustrated in Figure 4) for enclosing extension generates.
High effective resistance R in this second mode of operationoffPermission P+ grid 170 bears high voltage and will be at grid 140
Voltage swing be restricted to the breakdown voltage less than mos gate pole.Second operator scheme is effectively protected grid 140 and hits from being higher than
Wear the voltage of voltage.Because the breakdown voltage of double-gate semiconductor devices 300 is the breakdown voltage of mos gate pole and P+ grid 170
Summation, so the inherently high breakdown voltage of P+ grid provides the high-breakdown-voltage of double-gate semiconductor devices 300.
Fig. 5 illustrates the exemplary circuit figure of the double-gate semiconductor devices of Fig. 1 to Fig. 2.Circuit 500 includes N-channel JFET
510, N-channel MOS FET 530 and control circuit device 530.Control circuit device 530 will can be N-channel MOS FET 520
Voltage Vg1Function control voltage Vg2The grid of N-channel JFET 510 is provided.Control circuit device 530 works with same
When dynamically bias both N-channel MOS FET 520 and N-channel JFET 510 in " conducting " status or " shutdown " state.Control
Circuit device 530 processed can be the grid that the RF signal of the grid from N-channel MOS FET can be coupled to N-channel JFET
Capacitor.
Control circuit device 530 provides control voltage Vg2To bias N-channel JFET 510, so that working as N-channel MOS FET
(i.e. V when being " shutdown "g1<Vth), RoffEffective resistance is maximum value.In general, control voltage Vg2It is neighbouring to bias N-channel JFET 510
Pinch-off voltage Voff.(the i.e. V when N-channel MOS FET 520 is " conducting "g1>Vth), then control circuit 530 provides control voltage Vg2
To bias N-channel JFET 510, so that RonEffective resistance is the smallest and electric current is the largest.RonTo RoffEffective resistance
The big drift of voltage at the drain electrode of a wide range of permission N-channel JFET 510 of variation and for referring to figs. 1 to described by Fig. 2
Double-gate semiconductor devices corresponding high power performance.It can also referring to figs. 1 to double-gate semiconductor devices described in Fig. 2
To be expressed as the circuit diagram similar to circuit 500, wherein N-channel junction gate 510 can be by P-channel junction gate (not shown)
It substitutes and N-channel MOS grid 520 can be substituted by P-channel mos gate pole (not shown).
Fig. 6 illustrates the section of double-gate semiconductor devices according to an embodiment of the invention.In this embodiment,
Double-gate semiconductor devices 600 can be than making referring to figs. 1 to the configuration of Fig. 4 described embodiment higher space density
Make.As illustrated in Figure 6 like that, double-gate semiconductor devices 600 do not include the area N+, such as referring to figs. 1 to described in Fig. 4
The area N+ 160, the area N+ 162, the area N+ 260, the area N+ 262 and the area N+ 360.Therefore, without using the N+ between mos gate pole and junction gate
The common injection in area makes double-gate semiconductor devices 600.The principle of the operation of double-gate semiconductor devices 600 is similar to
The operation of described double-gate semiconductor devices 100,200 and 300 is (including described in reference Fig. 4 referring to figs. 1 to Fig. 3
The description of two operation modes) principle.
Double-gate semiconductor devices 600 can be used semiconductor fabrication techniques known in the art by doped silicon, polysilicon,
The area and/or floor of metal and insulating layer are formed.Double-gate semiconductor devices 600 include P- substrate 110, the shape in P- substrate 110
At N- trap 120, N+ source electrode 130, grid 140, oxide skin(coating) 150, P+ grid 170 and N+ drain electrode 180.
Such as Vg1With control voltage Vg2Electric signal can be respectively coupled to grid 140 and P+ grid 170.It can make
With semiconductor fabrication techniques known in the art, use the volume being arranged on surface each in N+ source electrode 130 and N+ drain electrode 180
Electric signal is coupled to N+ source electrode 130 and N+ drain electrode 180 by outer polysilicon layer (not shown) or metal layer (not shown).
Double-gate semiconductor devices 600, which may be considered that, to be similar to referring to figs. 1 to two operation mode behaviour described in Fig. 4
Make.In the first mode, electric current conducts between N+ source electrode 130 and N+ drain electrode 180.In a second mode, electric current non-conducting.?
In first mode, it is greater than threshold voltage VthThe voltage V of (not shown)g1It is applied to grid 140.Control voltage Vg2It is applied to P
+ grid 170, thus low effective resistance R is presented to electric current flowingon。
In this second mode of operation, it is applied to the voltage V of grid 140g1Lower than threshold voltage Vth, and control voltage
Vg2It is applied to P+ grid 170, therefore high effective resistance R is presented to electric current flowingoff.High effective resistance RoffBy depletion region
Generate, depletion region is similar to reference to depletion region 410 described in Fig. 4, under P+ grid 170 and around extension.
Fig. 7 provides the circuit diagram of the example electronic circuit 700 for amplifying such as input signal of RF signal.Electronics electricity
Road 700 includes the MOSFET 705 and bigrid JFET 710 with cascode configuration in FIG.In circuit 700, JFET 710 is used as
Variable resistance.
MOSFET 705 and bigrid JFET 710 are different transistor.It is as used herein such, in addition to crystal
Pipe shares common injection region, and two transistors are defined as different.As an example, the area N+ 260 and 262 (Fig. 2) point
It is not different drain electrode and the source electrode of transistor.As another example, the area N+ 160 and 162 (Fig. 1) is different transistor respectively
Drain electrode and source electrode because both share the injection region N+.
MOSFET 705 includes drain electrode and source electrode, and source electrode is coupled to power supply, such as V in operationDD。MOSFET
705 are controlled by grid, and grid receives input signal, such as RF input signal from the signal source of such as transceiver 715 in operation.
The various embodiments of circuit 700 include the input matching circuit 720 between transceiver 715 and the grid of MOSFET 705 with
With the impedance on its every side.A kind of example match circuit 720 includes capacitor and inductor, wherein capacitor be coupling in
Between node between transceiver 715 and the grid of MOSFET 705, and inductor is arranged in node and MOSFET 705
Grid between it is into a line.In various embodiments, the grid length of MOSFET 705, i.e., between source electrode and drain electrode
The length of grid injection, less than 1 micron.Notice that grid width is the grid in the plane of the substrate measured perpendicular to grid length
The size of pole.In various embodiments, MOSFET 705 can be NMOSFET or PMOSFET.
In some embodiments, signal source, such as transceiver 715 are disposed in and MOSFET 705 and bigrid JFET
On 710 identical substrates.In a further embodiment, signal source, which generates, has in the range of about 700MHz to about 2.5GHz
The signal of frequency.In a further embodiment, signal source, which generates, has frequency in the range of about 150MHz to about 6GHz
Signal.
Bigrid JFET 710 includes by (being arranged in the top grid 725 above and below channel by two grids
With bottom grid 730) control channel electrical connection source electrode and drain electrode.In various embodiments, bigrid JFET 710 can be with
It is NJFET or PJFET.In various embodiments, bigrid JFET 710 includes sub-micron grid length.Bigrid JFET710
Drain electrode be coupled to antenna 735 or be configured to signal transmission another device.In some embodiments, antenna 735 passes through
The output matching circuit 740 formed by passive network is coupled to the drain electrode of bigrid JFET 710, output matching circuit 740
It is provided with matching impedance.
The source electrode of bigrid JFET 710 is coupled to the drain electrode of MOSFET 705.In some embodiments, bigrid
The source electrode of JFET 710 is directly coupled to the drain electrode of MOSFET 705.As used herein such, " direct-coupling " means
There is no active parts in electrical connection between the transistor being coupled.In some embodiments, the source of bigrid JFET 710
Pole is coupled to the drain electrode of MOSFET 705 by the trace of through-hole and such as conductive layer 265 (Fig. 2).In some embodiments,
Point between bigrid JFET 710 and the drain electrode of MOSFET 705 includes common node (CN) point.As shown in fig. 7, showing some
In example, electronic circuit 700 also may include the optional common node circuit 750 coupled between common node point and ground.
As explained above, JFET 710 is controlled by top grid 725 and bottom grid 730.In various embodiments
In, top grid 725 and bottom grid 730 are complementary (such as common controlled) or independent, and can be by ground, DC
The input signal or input signal for biasing, being applied to the grid of MOSFET 705 add DC biasing control.Control top grid
725 and the various exemplary methods of bottom grid 730 be referenced Fig. 9 to Figure 15 discussion.In the example that Fig. 7 is provided, top grid
725 and the output of the optional JFET grid circuit 745 that is similar to control circuit 530 (Fig. 5) of bottom grid 730 control jointly
System.
JFET grid circuit 745 is used to improve the performance of the embodiment of the present invention as power amplifier.Bottom grid
730 biasing determines the voltage of top grid 725 with pinch off JEFT 710, and wherein the pinch-off voltage of JFET 710 is to be used for
The limits value of the drain electrode of MOSFET 705.The desired value biased for bottom grid 730 is the pinch-off voltage for allowing JFET 710
Protection MOSFET 705 is in the value in reliable area.In some embodiments, the top grid 725 of JFET 710 is maintained at 0V.
But very big grid is to source electrode and grid to capacitance of drain will drain and the very big voltage of source electrode is coupled on grid voltage,
Reduce the R of JFET 710offAnd RonThe efficiency of variation.The function of JFET grid circuit 745 is supported by applying opposite signal
These signals to disappear on top grid 725.
In some instances, as shown in fig. 7, electronic circuit 700 also may include being coupled between common node point and ground
Optional common node circuit 750.Common node circuit 750 is also used to improve the implementation of the invention as power amplifier
The performance of example.Common node circuit 750 compensates the grid of MOSFET 705 to the grid of capacitance of drain and JFET 710 to source electrode
The effect of capacitor.In some embodiments, common node circuit 750 can be single inductance or be configured to and MOSFET 705
With the illustrated capacitor of JFET 710 specific frequency resonance series inductor-capacitor (LC) network.
Fig. 8 A provides the section of the example electronic circuit 800 including MOSFET 805 and bigrid JFET 810, wherein
MOSFET 805 and JFET 810 constitute different transistors.In as in the previous embodiment, MOSFET 805 and bigrid JFET
810 can be used semiconductor fabrication techniques known in the art by doped silicon, polysilicon, various metals and various insulating layers
Area or floor are formed.In this example, the source electrode 815 of bigrid JFET 810 is directly coupled by metal layer 825 and through-hole 830
To the drain electrode 820 of MOSFET 805.As different transistors, MOSFET 805 and bigrid JFET 810 can be in identical linings
It at different location on bottom and has different sizes, such as different width is realized.
JFET 810 additionally includes drain electrode 835, top grid 840 and bottom grid 845.Top grid 840 and bottom
Grid 845 is disposed in above and below the N-channel 850 that the source electrode 815 of JFET 810 is coupled to drain electrode 820.Bottom grid
845 are defined by two p-wells 855 that offer is electrically connected to bottom grid 845.JFET 810 is disposed in including two 860 Hes of N trap
In the N well region of N separation layer 865.In these embodiments, p-well 855 is also used to for N-channel 850 being isolated with N trap 860.
As shown in Figure 8 A, the grid 870 of MOSFET 805 is by signal Vg1Control.Similarly, the top grid of JFET 810
840 and bottom grid 845 respectively by signal Vg2And Vg3Control.As explained above, signal Vg2It may rely on or solely
Stand on signal Vg1.Additionally, signal Vg3It may rely on or independently of signal Vg2。
Fig. 8 B provides the section of another example electronic circuit 875 including MOSFET 805 and bigrid JFET 810,
Wherein MOSFET 805 and JFET 810 constitute different transistors.In circuit 875, MOSFET 805 and bigrid JFET
It is disposed in individual N well region each of in 810.Here, wherein the N well region of arrangement MOSFET 805 is by two 880 Hes of N trap
N separation layer 885 defines.Advantageously MOSFET 805 is isolated with the substrate of JFET 810 for these embodiments.
Fig. 8 C provides the section of another example electronic circuit 875 including MOSFET 805 and bigrid JFET 810,
Wherein MOSFET 805 and JFET 810 constitute different transistors.Electronics electricity in electronic circuit 890 and Fig. 8 B in Fig. 8 C
875 difference of road is that N separation layer 865 across entire substrate is continuous.Here, wherein the N well region of arrangement MOSFET is by two N traps
880 and N separation layer 865 identical with the trap for defining JFET 810 define.
For example, can produce the reality of the electronic circuit of Fig. 8 C diagram since the substrate of the N separation layer 865 with insertion
Apply example.Substrate can by a surface of chip grown oxide layer, by the second bonding chip to the surface, then from
The back side of second chip is polished towards oxide skin(coating) until realizing that it is real that desired material thickness comes above N separation layer 865
It is existing；The substrate is commonly known as silicon-on-insulator (SOI) chip.The MOSFET's 805 that is limited in substrate and JFET 810 is each
Then kind feature proceeds to more shallow feature from deeper feature by ion implantation technique to be formed.Feature formed on a substrate
(as metal wire 825 and grid 870), for example, can be formed by photolithography method.For example, can by by ion implanting formed N every
Absciss layer 865 and optionally N separation layer 885 are then formed remaining feature being limited in substrate by ion implanting, are then followed by
Those features are formed on the substrate by photoetching to produce the embodiment of the illustrated electronic circuit of Fig. 8 A and Fig. 8 B.
Fig. 9 is provided including electronic circuit 700 and is further comprised being coupled to top grid 725 and bottom grid 730
The circuit diagram of the example electronic circuit 900 of DC bias source 910.In operation, DC bias voltage is added to input signal to control
Top grid 725 and bottom grid 730 processed.In various embodiments, DC bias voltage can be positive or negative.It can be
Apply negative-gate voltage on top grid 725 and bottom grid 730 to reduce common-node voltage, ensures in this way
The drain electrode of MOSFET 805 is maintained at its reliable area.On the contrary, positive grid can be applied on top grid 725 and bottom grid 730
Pole tension improves performance to use the complete drift of reliable drain voltage.In such as embodiment of electronic circuit 900, and
In some embodiments described below, MOS and JFET grid circuit 745 and common node circuit 750 are all optional.
Figure 10 provide for include electronic circuit 700 and further comprise be coupled to top grid 725 the first DC it is inclined
It sets source 1010 and is coupled to the circuit diagram of the example electronic circuit 1000 of the 2nd DC bias source 1020 of bottom grid 730.It is grasping
In work, it is every in top grid 725 and bottom grid 730 to independently control that independent DC bias voltage is added to input signal
A grid.In various embodiments, each DC bias voltage can be positive or negative.Capacitor 1030 is added to top
It is applied to each grid to allow different DC to bias between grid 725 and bottom grid 730, while applying and being applied to
The grid of MOSFET 705 is identical, be coupled to top grid 725 and bottom grid 730 in each grid RF.
Figure 11 provides the circuit diagram for example electronic circuit 1100, electronic circuit 1100 include electronic circuit 700 but
There is no MOS and JFET grid circuit 745 and wherein top grid 725 and bottom grid 730 to be coupled to ground.
Figure 12 provides the circuit diagram for example electronic circuit 1200, electronic circuit 1200 include electronic circuit 700 but
There is no MOS and JFET grid circuit 745 and wherein top grid 725 and bottom grid 730 to be coupled to DC bias source
910.In various embodiments, DC bias voltage can be positive or negative.
Figure 13 provides the circuit diagram for example electronic circuit 1300, electronic circuit 1300 include electronic circuit 700 but
There is no MOS and JFET grid circuit 745.Additionally, with Fig. 7 on the contrary, the first DC bias source 1010 is coupled to top grid
725, the 2nd DC bias source 1020 is coupled to bottom grid 730, rather than top grid 725 and bottom grid 730 mutually according to
Rely.In various embodiments, each DC bias voltage can be positive or negative.In those illustrated realities of Figure 11 to Figure 13
It applies in example, the control of top grid 725 and bottom grid 730 is independently of input signal.
Figure 14 provides the circuit diagram for example electronic circuit 1400, electronic circuit 1400 include electronic circuit 1300 simultaneously
It and further comprise MOS and JFET grid circuit 745.Figure 15 provides the circuit diagram for example electronic circuit 1500, circuit
1500 include modification so that bottom grid 730 and further comprises coupling independently of the electronic circuit 700 of top grid 725
The DC bias source 910 of top grid 725 is closed, while bottom grid 730 is coupled to ground.Those of illustrated in Figure 14 and Figure 15
In embodiment, the control of top grid 725 depends on the control of input signal while bottom grid 730 independently of input signal.
The advantages of RF signal is only applied to top grid 725 of JFET 710 is between top grid 725 and source electrode or drain terminal
Capacitor be less than capacitor between bottom grid 730 and source electrode or drain terminal, and top grid 725 is than bottom grid 730
It is more effective to control channel current flow.
Figure 16 is provided for being amplified using the MOSFET 705 of cascode configuration in FIG is in bigrid JFET 710
The flow chart of the exemplary method 1600 of signal indicates.This method includes being controlled with the first signal (i.e. by input signal to be amplified)
The step 1610 of the grid of MOSFET processed controls the step 1620 of the top grid of JFET with second signal and is believed with third
Number control JFET bottom grid step 1630.It will be recognized that the illustrated step of Figure 16 is intended to be performed simultaneously.
In various embodiments, second signal is independently of the first signal, and in some embodiments of these embodiments,
For example, two signals are identical in the place that the grid of MOSFET and the top grid of JFET are capacitively coupled.In these realities
It applies in some embodiments in example, third signal also relies on the first signal and the second signal, all as shown in fig. 7, and at other
In embodiment, third signal is independently of the first signal and the second signal, such as in figures 14 and 15.
In various embodiments, second signal is all as shown in Figure 11 to Figure 13 independently of the first signal.In these embodiments
In some embodiments in, third signal depends on second signal, and in other embodiments, third signal is independently of the second letter
Number.
In various embodiments, the first signal includes the summation of input signal and DC biasing.Also in various embodiments,
Any of binary signal and third signal all can be fixed DC biasing (positive or negative) or ground.
Figure 17 provides the section view of another example MOS device 1700 again of the invention.MOS device 1700 includes substrate
1705, substrate 1705 includes the first trap 1710 being limited in substrate 1705.First trap 1710 is characterized in that top surface 1715,
And there is the first source electrode 1720, first drain electrode 1725 wherein limited and the second drain electrode 1730, bottom grid 1735, first to push up
Portion's grid 1740.Top surface 1715 is overlapped with the top surface of substrate 1705, and can for example pass through planarization process shape
At.First trap 1710 also includes the isolation structure that the first trap 1710 is isolated with the remainder of substrate 1705.Isolation structure packet
The separation layer for being parallel to the arrangement of top surface 1715 is included, and also includes two side walls, each side wall is all connected to separation layer
Opposed end, and each side wall extends to top surface 1715.Dependent on context, term as used herein " trap " can
To refer to isolation structure or the thus whole volume that encloses, wherein structure and the volume enclosed are since different doping is in structure
It is differentiable.
First source electrode 1720 and the second drain electrode 1730 are separated by gap 1745.MOS device 1700 also includes being arranged in first
The dielectric layer 1750 being aligned above the top surface 1715 of trap 1710 and with gap 1745, and it is arranged in dielectric layer 1750
Top and the second top grid 1755 being similarly aligned with gap 1745.For example, the second top grid 1755 may include
Conductive material, such as polysilicon or metal.First trap 1710 further comprises being limited to bottom grid 1735 and top surface
The first channel 1760 between 1715.
In the embodiment of Figure 17, bottom grid 1735 is defined by two side walls 1770.Each side wall 1770 is all connected to
The opposed end of bottom grid 1735, and at least one side wall 1770 extends to top surface 1715.Side wall 1770 and bottom
Grid 1735 limits the second trap being arranged in the first trap 1710 together.First the 1725, first top grid 1740, first of drain electrode
Channel 1760 and the second source electrode 1765 are disposed in the second trap, so that the first top grid 1740 is disposed in the first leakage
Between pole 1725 and the second source electrode 1765.Bottom grid 1735 is electrically connected to top surface 1715 by side wall 1770, wherein at least
One electrical contact (not shown) can permit bias voltage and be applied to bottom grid 1735.In this embodiment, the first top
Grid 1740, the second source electrode 1765 and bottom grid 1735 and the first channel 1765 are collectively form in these embodiments
JFET。
In various embodiments, substrate 1705 can be with first doping (such as P-) silicon, the first trap 1710 every
It can have the second doping, such as N- from structure, bottom grid 1735 can have third doping, such as P+, the first source electrode
1720, first the 1725, second drain electrode 1730 of drain electrode and the second source electrode 1765 can have the 4th doping, such as N+ and top
Grid 1740 can have the 5th doping of such as P+, and optionally the 5th doping can be adulterates with the third of bottom grid 1735
Identical doping.Remaining material (including the first channel 1760) in the second trap can have the 6th doping of such as N-,
6th doping optionally can be the identical doping of the second doping with the first trap 1710.In the first trap 1710 but in the second trap
Remaining outer material includes the first source electrode 1720, second drain electrode 1730 and gap 1745.In addition to the first source electrode 1720 and second
Other than drain electrode 1730, which can be considered as being arranged in the third of the 7th doping in the first trap 1710 and with such as P-
Trap.7th doping optionally can be the identical doping of the first doping with substrate 1705.In gap 1745 and around should
Material constitutes second channel 1775 with the 7th doping.First source electrode 1720, second the 1730, second top grid of drain electrode
1755 and second channel 1775 MOSFET is collectively formed.Material in the second trap and third trap is doped so that when one
When being doped to N-shaped, another is doped to p-type.In these embodiments, third trap lack similar to first trap 1710 every
The limiting structure of bottom grid 1735 and side wall 1770 from structure and the second trap, but 1710 institute of the first trap can be defined as
The volume enclosed without the part in the second trap.
In the embodiment of Figure 17, a side wall 1770 is disposed between the second drain electrode 1730 and the second source electrode 1765.
Second source electrode 1765 is electrically insulated by the material in the second trap with the side wall 1770, while the material in third trap drains second
1730 are electrically insulated with the side wall 1770.Since the side wall 1770 and both the second drain electrode 1730 and the second source electrode 1765 all insulate,
Electric current cannot flow through wherein.On the contrary, the second drain electrode 1730 is directly coupled to the second source by metal layer 1780 and through-hole 1785
Pole 1765 is to provide current path therebetween.
The electrical contact (not shown) offer being arranged on top surface 1715 is electrically connected to grid 1735,1740, source electrode
1720,1765, drain electrode 1725,1730, and optionally the first trap 1710.Second grid 1755, which is electrically contacted, to be similarly electrically connected.
Grid 1735,1740,1755 can be controlled as described in the above embodiments.First trap 1710 can optionally lead to
Electrical contact is crossed to be biased.
Figure 18 provides the section view of another example MOS device 1800 again of the invention.MOS device 1800 includes substrate
1805, substrate 1805 includes the first trap 1810 being limited in substrate 1505.First trap 1810 is characterized in that top surface 1815,
And there is the first source electrode 1820, first drain electrode 1825 wherein limited and the second drain electrode 1830, bottom grid 1835 and first
Top grid 1840.Top surface 1815 is overlapped with the top surface of substrate 1805, and can for example pass through planarization process
It is formed.First trap 1810 also includes the isolation structure that the first trap 1810 is isolated with the remainder of substrate 1805.Isolation structure
Separation layer including being parallel to the arrangement of top surface 1815, and also include two side walls, each side wall is all connected to separation layer
Opposed end, and each side wall extends to top surface 1815.
First source electrode 1820 and the second drain electrode 1830 are separated by gap 1845.MOS device 1800 also includes being arranged in first
The dielectric layer 1850 being aligned above the top surface 1815 of trap 1810 and with gap 1845, and it is arranged in dielectric layer 1850
Top and the second top grid 1855 being similarly aligned with gap 1845.For example, the second top grid 1855 may include
Conductive material, such as polysilicon or metal.First trap 1810 further comprises being limited to bottom grid 1835 and top surface
The first channel 1860 between 1815.
In the embodiment of figure 18, bottom grid 1835 is defined by two side walls 1870.Each side wall 1870 is all connected to
The opposed end of bottom grid 1835, and at least one side wall 1870 extends to top surface 1815.Side wall 1870 and bottom
Grid 1835 limits the second trap being arranged in the first trap 1810 together.The 1830, first top of first source electrode 1820, second drain electrode
The drain electrode 1825 of grid 1840, first and the first channel 1860 are all disposed in the second trap, wherein 1840 He of the first top grid
Second drain electrode 1830 is disposed between the first source electrode 1820 and the first drain electrode 1825, and the first top grid 1840 is disposed in the
Between one drain electrode 1825 and the second drain electrode 1830.Bottom grid 1835 is electrically connected to top surface 1815 by side wall 1870, wherein
At least one electrical contact (not shown) can permit bias voltage and be applied to bottom grid 1735.
In various embodiments, substrate 1805 can be with first doping (such as P-) silicon, the first trap 1810 every
It can have the second doping, such as N- from structure, bottom grid 1835 can have third doping, such as P+, the first source electrode
1820, the first drain electrode 1825 and the second drain electrode 1830 can have the 4th doping, and such as N+ and top grid 1840 can be with
The 5th doping with such as P+, optionally the 5th doping, which can be, adulterates identical doping with the third of bottom grid 1835.
Remaining material in the second trap is divided into the area Liang Ge, with the 6th doping the first area 1875 and have the 7th
Second area 1880 of doping, wherein the 6th doping and the 7th doping are opposite types, it is intended that when a doping is n-type doping
When, another doping is p-type.6th doping optionally can it is identical as the first doping and/or the 7th doping can with second adulterate
It is identical.On the boundary between the first area 1875 and the second area 1880 in the second trap in bottom grid 1835 and the second area 1835
Between extend so that both the second drain electrode 1830 and area 1875,1880 all contact.First channel 1860 is disposed in the secondth area
It can offe telex in 1880 and between two drain electrodes 1820,1830 and lead.Second channel 1885 is disposed in the firstth area
It can offe telex in 1875 and between the first source electrode 1820 and the second drain electrode 1830 and lead.
The electrical contact (not shown) offer being arranged on top surface 1815 is electrically connected to grid 1835,1840, source electrode
1820, and drain electrode 1825,1830.Second grid 1855 is similarly electrically connected.Grid 1835,1840,1855 can be as above
Embodiment described in controlled like that.
Embodiments described herein is example of the invention.These embodiments being such as described with reference to the accompanying figures, it is described
Method or particular element various modifications or reorganization those skilled in the art can be become apparent.All dependences are originally
The introduction of invention, and by it, these instruct the such modification for having had advanced into this field, reorganization or variation, are recognized
For within the spirit and scope of the present invention.Therefore, these descriptions and attached drawing should not be considered in limiting sense, as should
What is understood is that the present invention is in no way intended to limit the embodiment only illustrated.
Claims (3)
1. a kind of MOS device, comprising:
Substrate, including the first trap being limited in the substrate, the trap is characterized in that top surface and has to be limited to
In the trap:
Bottom grid,
The first channel being limited between the bottom grid and the top surface,
First source electrode,
First drain electrode,
The second drain electrode between first drain electrode and first source electrode,
First grid between first drain electrode and second drain electrode,
Gap between first source electrode and second drain electrode, and
The first side wall and second sidewall are limited in first trap and are each connected to the bottom grid, the bottom
Portion's grid and two side walls limit the second trap in first trap, and wherein first source electrode, it is described first drain electrode and
Second drain electrode and the first grid are all disposed in second trap；
Dielectric layer, be arranged in above the top surface of first trap and with the gap alignment；And
Second grid, be arranged in above the dielectric layer and with the gap alignment.
2. MOS device according to claim 1, further comprises the second channel, two channels are all disposed within described second
In trap, first channel and second channel include different doping types.
3. MOS device according to claim 2, wherein first channel is in second drain electrode and first drain electrode
Between offe telex and lead and controlled by the first grid, second channel is in first source electrode and second drain electrode
Between offe telex and lead and controlled by the second grid.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461923578P | 2014-01-03 | 2014-01-03 | |
| US61/923,578 | 2014-01-03 | ||
| US14/531,754 | 2014-11-03 | ||
| US14/531,754 US9240402B2 (en) | 2008-02-13 | 2014-11-03 | Electronic circuits including a MOSFET and a dual-gate JFET |
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| CN102044540A (en) * | 2009-10-22 | 2011-05-04 | 联华电子股份有限公司 | Semiconductor device and method of operation thereof |
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| CN102414984A (en) * | 2009-04-22 | 2012-04-11 | Acco半导体公司 | Electronic circuits including mosfet and dual-gate jfet |
| CN102044540A (en) * | 2009-10-22 | 2011-05-04 | 联华电子股份有限公司 | Semiconductor device and method of operation thereof |
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