CN104753684B - A kind of method for realizing digital signature and sign test - Google Patents

Abstract

The invention discloses a method for realizing digital signature and signature verification, which belongs to the field of information security. The method includes: the CPU performs modulo calculation on the hash result and the data in the first preset memory, and saves the result in the third register ;Operate the data in the first random number memory, the fourth and fifth registers, and the first preset memory, and store the result in the seventh register; read the signature private key, the seventh register, the third register and The data in the first random access memory is processed, and the result is stored in the eighth register; the data in the seventh and eighth registers are output as the signature result. Adopting the technical scheme of the present invention can realize identity authentication, ensure the integrity and non-repudiation of data, and initialize the modulus operation parameters and elliptic curve parameters, which improves the operation efficiency. The verification of the public key further improves the security of the signature.

Description

A Method for Realizing Digital Signature and Signature Verification

technical field

The invention relates to the field of information security, in particular to a method for realizing digital signature and signature verification.

Background technique

A digital signature is some data attached to a data unit or a cryptographic change made to a data unit. This data or change only allows the receiver of the data unit to confirm the source of the data unit and the integrity of the data unit, protecting the data from forged by others. Digital signature is realized based on public key cryptosystem and private key cryptosystem.

Contents of the invention

The present invention provides a method for realizing digital signature and signature verification. The adopted technical solution is: a method for realizing digital signature, comprising:

Step S1: The CPU reads the hash result, reads the data in the first preset memory, performs a modulo operation on the hash result and the data in the first preset memory, and saves the result to the second register middle;

Step S2: CPU reads the data in the first random number memory, the second preset memory and the third preset memory, and combines the data in the first random number memory with the second preset memory and the third preset memory Dot multiplication operation is performed on the data in the three preset memories, and the operation result is saved in the third register;

Step S3: The CPU performs a modulo operation on the data in the third register and the data in the first preset memory, and saves the result in the fourth register;

Step S4: The CPU reads the signature private key, and performs preset operations on the signature private key, the data in the second register, the data in the fourth register, and the data in the first random number memory, Save the result to the fifth register;

Step S5: The CPU outputs the data in the fourth register and the data in the fifth register as a signature result.

Before the step S1, the method further includes: the CPU receives the data to be signed from outside, performs a preset hash operation on the data to be signed, and saves the hash result obtained from the operation.

Before the step S1, it also includes: the CPU sets the modulo operation parameter as the first preset value and saves it in the first preset memory, and sets the elliptic curve parameter as the second preset value and the third preset value , saving the second preset value into the second preset memory, and saving the third preset value into the third preset memory.

Between the step S1 and the step S2, it also includes: the CPU judges whether the data in the second register is the fourth preset value, and if yes, sets the data in the second register to the fifth preset value. Set the value, execute step S2, otherwise directly execute step S2.

Also include before the step S2:

Step a: the CPU generates a random number, judges whether the random number is greater than the fourth preset value and smaller than the first preset value, if yes, saves the random number into the first random number memory, and executes the step S2, otherwise proceed to step a.

Between the step S3 and the step S4, it further includes: judging whether the data in the fourth register is the fourth preset value, and if so, executing step S4, otherwise returning to step a.

In the step S4, the preset operation is performed on the signature private key, the data in the second register, the data in the fourth register and the data in the first random number memory, and the result Save to the fifth register, specifically:

Step a1: The CPU multiplies the data in the fourth register by the signature private key, saves the result in the first intermediate value memory, and multiplies the data in the first random number memory by the second register The data in is multiplied, and the result is stored in the second intermediate value memory;

Step a2: The CPU adds the data in the first intermediate value memory to the data in the second intermediate value memory, and saves the result in the third intermediate value memory;

Step a3: The CPU performs a modulo operation on the data in the third intermediate value memory and the data in the first preset memory, and saves the result in the fifth register.

Between the step S4 and the step S5, it further includes: the CPU judges whether the data in the fifth register is the fourth preset value, and if yes, returns to step a, otherwise executes step S5.

The step S5 specifically includes: the CPU combines the data in the fourth register and the data in the fifth register, and outputs the combined data.

The combination of the data in the fourth register and the data in the fifth register to obtain a signature result is specifically: splicing the data in the fourth register and the data in the fifth register , get the signature result.

A method for realizing digital signature verification, comprising:

Step T1: The CPU reads the signature result, processes the signature result, saves the obtained two results into the eighth register and the ninth register respectively, reads the data to be signed, and hashes the data to be signed Calculate and save the result to the tenth register;

Step T2: the CPU reads the data in the first preset memory, performs a modulo operation on the data in the tenth register and the data in the first preset memory, and saves the result in the eleventh register;

Step T3: The CPU calculates the inverse of the modulo between the data in the eleventh register and the data in the first preset memory, and saves the result in the twelfth register;

Step T4: The CPU processes the data in the ninth register, the data in the twelfth register, and the data in the first preset memory, saves the result to the thirteenth register, and performs processing on the Processing the data in the eighth register, the data in the twelfth register and the data in the first preset memory, and storing the result in the fourteenth register;

Step T5: The CPU reads the signature public key, performs preset operations on the data in the thirteenth register, the data in the fourteenth register, and the signature public key, and saves the result in the fifteenth register ;

Step T6: The CPU performs a modulo operation on the data in the fifteenth register and the data in the first preset memory, and saves the result in the sixteenth register;

Step T7: The CPU judges whether the data in the sixteenth register is equal to the data in the eighth register, and if so, outputs signature verification success information, otherwise outputs signature verification failure information.

Before the step T2, it also includes: the CPU sets the modulo operation parameter to the first preset value and saves it in the first preset memory; the CPU sets the elliptic curve parameter to the second preset value and the third preset value, saving the second preset value into the second preset memory, and saving the third preset value into the third preset memory.

Between the step T1 and the step T2, further comprising: CPU judging whether the data in the eighth register and the data in the ninth register are both larger than the fourth preset value and smaller than the first preset value, If yes, execute step T2, otherwise report an error and end.

Between the step T2 and the step T3, it also includes: the CPU judges whether the data in the eleventh register is the fourth preset value, and if yes, sets the data in the eleventh register to The fifth preset value, execute step T3, otherwise directly execute step T3.

In the step T4, the data in the ninth register, the data in the twelfth register and the data in the first preset memory are processed, and the result is saved in the thirteenth register , specifically: the CPU calculates the product of the data in the ninth register and the data in the twelfth register, performs a modulo operation on the product result and the data in the first preset memory, and saves the result of the modulo operation to the thirteenth register.

In the step T4, the data in the eighth register, the data in the twelfth register and the data in the first preset memory are processed, and the result is saved in the fourteenth register , specifically: the CPU calculates the product of the data in the eighth register and the data in the twelfth register, performs a modulo operation on the product result and the data in the first preset memory, and saves the result of the modulo operation to the fourteenth register.

The step T5 specifically includes:

Step b1: CPU reads the data in the second preset memory and the third preset memory, and reads the signature public key;

Step b2: The CPU performs a dot multiplication operation on the data in the thirteenth register, the data in the second preset memory and the data in the third preset memory, and saves the two results obtained by the operation respectively to the fourth intermediate value memory and the fifth intermediate value memory;

Step b3: The CPU multiplies the data in the fourteenth register by the signature public key, and saves the two results obtained by the operation into the sixth intermediate value memory and the seventh intermediate value memory;

Step b4: The CPU calculates the data in the fourth intermediate value memory, the fifth intermediate value memory, the sixth intermediate value memory and the seventh intermediate value memory, and saves the calculation result in the first Fifteen registers.

The beneficial effects obtained by the present invention are: adopting the technical scheme of the present invention, identity authentication can be realized, data integrity and non-repudiation can be guaranteed, and the modulo operation parameters and elliptic curve parameters can be initialized to improve the operation efficiency, and the signature verification The verification of the public key in the process further improves the security of the signature.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a flow chart of a method for realizing a digital signature provided by Embodiment 1 of the present invention;

FIG. 2 is a flow chart of a method for implementing a digital signature provided by Embodiment 2 of the present invention;

Figure 3 is a flow chart of a method for realizing digital signature verification provided by Embodiment 3 of the present invention

Fig. 4 is a flow chart of a method for implementing digital signature verification provided by Embodiment 4 of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Example 1

Embodiment 1 of the present invention provides a method for realizing a digital signature, as shown in Figure 1, including:

Step S1: The CPU reads the hash result, and reads the data in the first preset memory, performs a modulo operation on the hash result and the data in the first preset memory, and saves the result in the second register;

Step S2: CPU reads the data in the first random number memory, the second preset memory and the third preset memory, and compares the data in the first random number memory with the data in the second preset memory and the third preset memory The data is multiplied by dot, and the operation result is saved in the third register;

Step S3: The CPU performs a modulo operation on the data in the third register and the data in the first preset memory, and saves the result in the fourth register;

Step S4: The CPU reads the signature private key, performs preset operations on the signature private key, the data in the fourth register, the data in the second register and the data in the first random number memory, and saves the result in the fifth register ;

Step S5: The CPU outputs the data in the fourth register and the data in the fifth register as a signature result.

Example 2

Embodiment 2 of the present invention provides a method for implementing a digital signature, as shown in Figure 2, including:

Step 101: the CPU reads the hash result in the first register;

In this embodiment, the CPU performs a preset hash operation on the data to be signed externally, obtains the hash result, and saves it in the first register;

For example, the data to be signed is 0x499602D2;

The first hash data in the first register obtained after the preset hash operation is:

0x1785EC310767F81A8D9FD076D39074261C13EA788B9311DEE3CAFF2ECF00670D;

Step 102: CPU initializes the modulo operation parameters, sets the modulo operation parameters as the first preset value, and saves them in the first preset memory, sets the elliptic curve parameters as the second preset value and the third preset value, and sets saving the second preset value into the second preset memory, and saving the third preset value into the third preset memory;

In this embodiment, preferably, the first preset value is:

0x8000000000000000000000000000000150FE8A1892976154C59CFC193ACCF5B3;

Step 103: The CPU reads the data in the first preset memory, performs a modulo operation on the hash result in the first register and the first preset value in the first preset memory, and saves the result of the modulo operation in the second register middle;

For example, the CPU calculates the hash data 0x1785EC310767F81A8D9FD076D39074261C13EA788B9311DEE3CAFF2ECF00670D in the first register and the first preset value 0x8000000000000000000000000000000150CFB to obtain ACFC53C modulo 8A1892976154C3C.

0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6672B043EE5, store the data in the second register;

Step 104: CPU judges whether the data in the second register is the fourth preset value, if yes, then sets the data in the second register to the fifth preset value, and executes step 105, otherwise directly executes step 105;

Preferably, the fourth preset value is 0, and the fifth preset value is 1;

Step 105: The CPU generates a random number and saves it in the first random number memory, and judges whether the random number in the first random number memory is greater than the fourth preset value and smaller than the first preset value, and if so, executes step 106, Otherwise, proceed to step 105;

For example, the random number generated by the CPU, that is, the data in the first random number memory is:

0x77105C9B20BCD3122823C8CF6FCC7B956DE33814E95B7FE64FED924594DCEAB3; if it is greater than the fourth preset value and less than the first preset value, go to step 106;

Step 106: CPU reads the data in the first random number memory, the second preset memory and the third preset memory, and compares the data in the first random number memory with the data in the second preset memory and the third preset memory The data is multiplied by dot, and the operation result is saved in the third register;

Preferably, the data in the second preset memory is: 0x2

The data in the third preset memory is:

0x8E2A8A0E65147D4BD6316030E16D19C85C97F0A9CA267122B96ABBCEA7E8FC8;

The data in the first random number memory is:

0x77105C9B20BCD3122823C8CF6FCC7B956DE33814E95B7FE64FED924594DCEAB3;

The CPU performs a dot multiplication operation on the data in the first random number memory and the data in the second preset memory and the third preset memory, and the obtained operation result is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493, save this data to the third register.

Step 107: The CPU performs a modulo operation on the data in the third register and the data in the first preset memory, and saves the result in the fourth register;

For example, the data in the third register is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493;

The CPU performs a modulo operation on the data in the third register and the data in the first preset memory, and the calculated data is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493, save this data to the fourth register;

Step 108: the CPU judges whether the data in the fourth register is the fourth preset value, if yes, returns to step 105, otherwise executes step 109;

Preferably, the fourth preset value is 0;

Step 109: The CPU reads the signature private key, multiplies the data in the fourth register with the signature private key, saves the result in the first intermediate value memory, and multiplies the data in the first random number memory with the data in the second register The data is multiplied, and the result is stored in the second intermediate value memory;

For example, the read signature private key is:

0x7A929ADE789BB9BE10ED359DD39A72C11B60961F49397EEE1D19CE9891EC3B28;

The CPU multiplies the data in the fourth register and the signature private key to obtain the data in the first intermediate value memory as follows:

0x1F70B2393C875C74B1A479D9F7971E8DA54B116F1A1D872B5E15035BC1DE2B9EF18B59F89A2CE73B4E87980453EEB0084809CEE08C64296CCB18F29A39F297F8;

CPU将第一随机数存储器中的随机数0x77105C9B20BCD3122823C8CF6FCC7B956DE33814E95B7FE64FED924594DCEAB3与第二寄存器中的数据0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6672B043EE5做乘法，计算得到的第二中间值存储器中的数据为：

0x1562F768DC86051699E15ED2B82E87498C7035EE2FAA123ED4B2D512D4E848270A434EC3C8B6DBC95A088D4F9ADE41B1E36C0B2EE5002CC6C3CB613066414C1F;

Step 110: The CPU adds the data in the first intermediate value memory to the data in the second intermediate value memory, saves the result in the third intermediate value memory, and combines the data in the third intermediate value memory with the first preset The data in the memory is subjected to a modulo operation, and the result is stored in the fifth register;

For example, the data in the third intermediate value memory obtained by adding the data in the first intermediate value memory and the data in the second intermediate value memory by the CPU is:

0x34D3A9A2190D618B4B85D8ACAFC5A5D731BB475D49C7996A32C7D86E96C673C5FBCEA8BC62E3C304A8902553EECCF1BA2B75DA0F716456338EE453CAA033E417;

The data in the fifth register obtained by the CPU performing modulo operation on the data in the third intermediate value memory and the data in the first preset memory is:

0x1456C64BA4642A1653C235A98A60249BCD6D3F746B631DF928014F6C5BF9C40;

Step 111: the CPU judges whether the data in the fifth register is the fourth preset value, if yes, returns to step 105, otherwise executes step 112;

Step 112: The CPU outputs the data in the fourth register and the data in the fifth register as a signature result;

In this embodiment, preferably, the data in the fourth register and the data in the fifth register are spliced to obtain a signature result;

For example, the CPU concatenates the data 0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493 in the fourth register and the data 0x1456C64BA4642A1653C235A98A60249BCD6D3F746B631D F928019F in the fifth register.

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC04931456C64BA4642A1653C235A98A60249BCD6D3F746B631DF928014F6C5BF9C40.

Example 3

Embodiment 3 of the present invention provides a method for realizing digital signature verification, as shown in Figure 3, including:

Step T1: The CPU reads the signature result, processes the signature result, saves the result to the eighth register and the ninth register, reads the data to be signed, performs hash calculation on the data to be signed, and saves the result to the tenth register ;

Step T2: The CPU reads the data in the first preset memory, performs a modulo operation on the data in the tenth register and the data in the first preset memory, and saves the result in the eleventh register;

Step T3: The CPU calculates the inverse of the modulo between the data in the eleventh register and the data in the first preset memory, and saves the result in the twelfth register;

Step T4: The CPU processes the data in the ninth register, the data in the twelfth register and the data in the first preset memory, saves the result in the thirteenth register, and processes the data in the eighth register, the data in the first preset memory The data in the twelve registers and the data in the first preset memory are processed, and the result is stored in the fourteenth register;

Step T5: The CPU reads the signature public key, performs preset operations on the data in the thirteenth register, the data in the fourteenth register, and the signature public key, and saves the result in the fifteenth register;

Step T6: The CPU performs a modulo operation on the data in the fifteenth register and the data in the first preset memory, and saves the result in the sixteenth register;

Step T7: The CPU judges whether the data in the sixteenth register is equal to the data in the eighth register, and if so, outputs a signature verification success message, otherwise outputs a signature verification failure message.

Example 4

Embodiment 4 of the present invention provides a method for realizing digital signature verification. As shown in FIG. 4, when receiving the signature result and the data to be signed that need to be The data is saved to the seventh register, and the CPU performs the following operations:

Step 201: The CPU initializes the elliptic curve parameters, sets the modulo calculation parameters as the first preset value, and saves them in the first preset memory, sets the elliptic curve parameters as the second preset value and the third preset value, and sets saving the second preset value into the second preset memory, and saving the third preset value into the third preset memory;

In this embodiment, the first preset value in the first preset memory is:

0x8000000000000000000000000000000150FE8A1892976154C59CFC193ACCF5B3;

The second preset value in the second preset memory is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493;

The third preset value in the third preset memory is:

0x489C375A9941A3049E33B34361DD204172AD98C3E5916DE27695D22A61FAE46E;

Step 202: the CPU acquires the second data and the third data from the sixth register, saves the second data into the eighth register, and saves the third data into the ninth register;

For example, the second data obtained by the CPU from the signature result, that is, the data stored in the eighth register is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493;

The third data obtained by the CPU from the signature result, that is, the data stored in the ninth register is:

0x1456C64BA4642A1653C235A98A60249BCD6D3F746B631DF928014F6C5BF9C40;

Step 203: The CPU judges whether the data in the eighth register and the data in the ninth register are both greater than the fourth preset value and smaller than the first preset value, if yes, execute step 204, otherwise report an error and end;

Preferably, the fourth preset value is 0;

Step 204: The CPU reads the data to be signed in the seventh register, performs hash calculation on the data to be signed in the seventh register, obtains the hash result, and saves the hash result in the tenth register;

In this embodiment, the CPU performs a preset hash operation on the received data to be signed to obtain a hash result;

For example, the data to be signed received by the CPU is 0x499602D2, and the hash result obtained after performing hash calculation on the data to be signed is:

0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6672B043EE5;

Step 205: The CPU reads the data in the first preset memory, performs a modulo operation on the hash result in the tenth register and the first preset value in the first preset memory, and saves the result in the eleventh register;

For example, the CPU performs a modulo operation on the hash result and the first preset value, and the calculated data in the eleventh register is:

0x2DFBC1B372D89A1188C09C52E0EEC61FCE52032AB1022E8E67ECE6672B043EE5;

Step 206: the CPU judges whether the data in the eleventh register is the fourth preset value, if yes, sets the data in the eleventh register to the fifth preset value, and executes step 207, otherwise directly executes step 207;

Preferably, the fourth preset value is 0, and the fifth preset value is 1;

Step 207: The CPU calculates the inverse of the modulus between the data in the eleventh register and the first preset value in the first preset memory, and saves the result to the twelfth register;

For example, the data in the twelfth register calculated by the CPU is:

0x271A4EE429F84EBC423E388964555BB29D3BA53C7BF945E5FAC8F381706354C2;

Step 208: The CPU calculates the product of the data in the ninth register and the data in the twelfth register, performs a modulo operation on the result and the first preset value in the first preset memory, and saves the result to the thirteenth register middle;

In this embodiment, the data in the thirteenth register calculated by the CPU is:

0x5358F8FFB38F7C09ABC782A2DF2A3927DA4077D07205F763682F3A76C9019B4F;

Step 209: The CPU calculates the product of the data in the eighth register and the data in the twelfth register, performs a modulo operation on the result and the first preset value in the first preset memory, and saves the result in the fourteenth register ;

In this embodiment, the data in the fourteenth register calculated by the CPU is:

0x3221B4FBBF6D101074EC14AFAC2D4F7EFAC4CF9FEC1ED11BAE336D27D527665;

In this embodiment, step 208 and step 209 have no sequence and can be executed at the same time;

Step 210: The CPU reads the data in the second preset memory and the third preset memory, and compares the data in the thirteenth register with the second preset value in the second preset memory and the data in the third preset memory Dot multiplication is performed on the third preset value, and the two obtained results are respectively stored in the fourth intermediate value memory and the fifth intermediate value memory;

For example, the CPU performs dot multiplication, and the obtained data in the fourth intermediate value memory is:

0xCA4036F2B1EC00E1D9E4F789EE594C83F22987A2D9FD7844572ECB443F676E67;

At the same time, the data in the fifth intermediate value memory obtained by the CPU is:

0x55E6DD8D570DD7CE2E1C8E2DE340E2F9785E94E257E3530C074510E46CE50464;

Step 211: The CPU reads the signature public key, multiplies the data in the fourteenth register by the signature public key, and saves the two results obtained from the operation into the sixth intermediate value memory and the seventh intermediate value memory;

For example, the signature public key obtained by the CPU is:

(0x7F2B49E270DB6D90D8595BEC458B50C58585BA1D4E9B788F6689DBD8E56FD80B, 0x26F1B489D6701DD185C8413A977B3CBBAF64D1C593D26627DFFB101A87FF77DA);

The data in the sixth intermediate value memory obtained by the CPU multiplying the data in the fourteenth register and the signature public key is:

0x64A4B968FFEE6A93EC23445E47129E087F1517FA6152DD5DABC2ADBA527191DC;

At the same time, the data in the seventh intermediate value memory obtained by the CPU is:

0x1CA5EE5FC1BFC27EFC8B4E260F8FD17593A5E4E42821045B546A3DC2E2B8A290;

In this embodiment, step 210 and step 211 have no sequence and can be executed at the same time;

Step 212: CPU calculates the data in the fourth intermediate value memory, the fifth intermediate value memory, the sixth intermediate value memory and the seventh intermediate value memory, and saves the calculation result in the fifteenth register;

For example, the data in the fifteenth register calculated by the CPU is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493;

Step 213: The CPU performs a modulo operation on the data in the fifteenth register and the first preset value in the first preset memory, and saves the result in the sixteenth register;

For example, the data in the sixteenth register calculated by the CPU is:

0x41AA28D2F1AB148280CD9ED56FEDA41974053554A42767B83AD043FD39DC0493;

Step 214: the CPU judges whether the data in the sixteenth register is equal to the data in the eighth register, and if yes, then outputs signature verification success information, otherwise outputs signature verification failure information;

In this embodiment, the data in the eighth register obtained by the CPU from the received signature result is the same as the data in the sixteenth register, and the signature verification is successful.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, any changes or variations that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. A kind of 1. method for realizing digital signature, it is characterised in that including：

   Step S1：CPU read Hash result, and read the first preset memory in data, by the Hash result with it is described Data in first preset memory carry out modular arithmetic, and result is preserved into the second register；

   Step S2：CPU reads the data in the first random number memories, the second preset memory and the 3rd preset memory, will Data in first random number memories and the data in second preset memory and the 3rd preset memory Point multiplication operation is carried out, operation result is preserved into the 3rd register；

   Step S3：Data in data in 3rd register and first preset memory are carried out modular arithmetic by CPU, Result is preserved into the 4th register；

   Step S4：CPU reads signature private key, to the data in the signature private key, second register, the 4th deposit The data in data and first random number memories in device carry out default computing, and result is preserved to the 5th register In；

   Step S5：CPU is defeated as signature result using the data in the data and the 5th register in the 4th register Go out；

   Also include before the step S1：CPU receives outside incoming data to be signed, and the data to be signed are preset Hash operation, the Hash result that computing is obtained preserve；

   In the step S4, in the data in the signature private key, second register, the 4th register Data in data and first random number memories carry out default computing, result are preserved into the 5th register, specifically For：

   Step a1：Data in 4th register and the signature private key are done multiplication by CPU, and result is preserved into first Between be worth in memory, the data in the data in first random number memories and second register are done into multiplication, will As a result preserve into the second median memory；

   Step a2：CPU is by the data in the first median memory and the data phase in the second median memory Add, result is preserved into the 3rd median memory；

   Step a3：Data in data in the 3rd median memory and first preset memory are done mould by CPU Computing, result is preserved into the 5th register；

   The step S5, it is specially：CPU carries out the data in the data in the 4th register and the 5th register Splicing, obtain result of signing.
2. 2. according to the method for claim 1, it is characterised in that also include before the step S1：CPU is by modular arithmetic parameter The first preset value is arranged to, and is preserved into first preset memory, elliptic curve parameter is arranged to the second preset value With the 3rd preset value, the second preset value is preserved into second preset memory, the 3rd preset value is preserved to described In three preset memories.
3. 3. according to the method for claim 1, it is characterised in that also include between the step S1 and the step S2：CPU Judge whether the data in second register are the 4th preset value, if it is, by the data in second register The 5th preset value is arranged to, performs step S2, otherwise directly performs step S2.
4. 4. according to the method for claim 1, it is characterised in that also include before the step S2：

   Step a：CPU generates random number, judges whether the random number is more than the 4th preset value and is less than the first preset value, if It is then to preserve the random number into first random number memories, performs step S2, otherwise continue executing with step a.
5. 5. according to the method for claim 4, it is characterised in that between the step S3 and the step S4, in addition to：Sentence Whether the data broken in the 4th register are the 4th preset value, if it is, performing step S4, otherwise return to step a.
6. 6. according to the method for claim 4, it is characterised in that between the step S4 and the step S5, in addition to： CPU judges whether the data in the 5th register are the 4th preset value, performs step a if it is, returning, otherwise performs Step S5.
7. A kind of 7. method for realizing digital sign test, it is characterised in that including：

   Step T1：CPU read signature result, to it is described signature result handle, by obtain two results preserve respectively to In 8th register and the 9th register, data to be signed are read, Hash calculation is carried out to the data to be signed, result is protected Deposit into the tenth register；

   Step T2：CPU reads the data in the first preset memory, and the data in the tenth register are preset with first and deposited Data in reservoir carry out modular arithmetic, and result is preserved into the 11st register；

   Step T3：CPU calculates the data in the 11st register and the data modulus in first preset memory Inverse element, result is preserved into the 12nd register；

   Step T4：CPU is preset to the data in the 9th register, the data in the 12nd register and described first Data in memory are handled, and result is preserved into the 13rd register, to the data in the 8th register, institute The data stated in the data in the 12nd register and first preset memory are handled, and result is preserved to the 14th In register；

   Step T5：CPU reads public signature key, to the data in the 13rd register, the number in the 14th register Default computing is carried out according to the public signature key, result is preserved into the 15th register；

   Step T6：Data in data in 15th register and first preset memory are carried out mould fortune by CPU Calculate, result is preserved into the 16th register；

   Step T7：CPU judges whether the data in the 16th register and the data in the 8th register are equal, such as Fruit is then to export sign test successful information, otherwise exports sign test failure information；

   In the step T4, the data in the 9th register, data in the 12nd register and described Data in first preset memory are handled, and result is preserved into the 13rd register, are specially：Described in CPU is calculated The product of data and the data in the 12nd register in 9th register, result of product is preset with described first and deposited Data in reservoir carry out modular arithmetic, and modular arithmetic result is preserved into the 13rd register；

   In the step T4, the data in the 8th register, data in the 12nd register and described Data in first preset memory are handled, and result is preserved into the 14th register, are specially：Described in CPU is calculated The product of data and the data in the 12nd register in 8th register, result of product is preset with described first and deposited Data in reservoir carry out modular arithmetic, and modular arithmetic result is preserved into the 14th register；

   The step T5, is specifically included：

   Step b1：CPU reads the data in the second preset memory and the 3rd preset memory, and reads public signature key；

   Step b2：CPU is by the data in the data in the 13rd register and second preset memory and described the Data in three preset memories carry out point multiplication operation, and two results that computing is obtained are preserved to the 4th median and stored respectively In device and the 5th median memory；

   Step b3：Data in 14th register and the public signature key are done multiplication by CPU, two that computing is obtained As a result preserve respectively into the 6th median memory and the 7th median memory；

   Step b4：CPU stores to the 4th median memory, the 5th median memory, the 6th median Data in device and the 7th median memory are calculated, and result of calculation is preserved into the 15th register.
8. 8. according to the method for claim 7, it is characterised in that also include before the step T2：CPU is by modular arithmetic parameter The first preset value is arranged to, and is preserved into first preset memory；Elliptic curve parameter is arranged to second and preset by CPU Value and the 3rd preset value, second preset value is preserved into second preset memory, and the 3rd preset value is protected Deposit into the 3rd preset memory.
9. 9. according to the method for claim 7, it is characterised in that between the step T1 and the step T2, in addition to： CPU judges whether data in the 8th register and the data in the 9th register are all higher than the 4th preset value and small In the first preset value, if it is, performing step T2, otherwise report an error, terminate.
10. 10. according to the method for claim 7, it is characterised in that between the step T2 and the step T3, in addition to： CPU judges whether the data in the 11st register are the 4th preset value, if it is, by the 11st register Data be arranged to the 5th preset value, perform step T3, otherwise directly execution step T3.