CN104753548B - Multi-channel receiver and signal receiving method thereof - Google Patents

Abstract

A multi-channel receiver and a signal receiving method thereof. The multi-channel receiver includes a first equalizer, a second equalizer, an analog pulse data recovery circuit and a digital pulse data recovery circuit. The first equalizer is used to receive a first received signal and output a first equalized signal. The second equalizer is used to receive a second received signal and output a second equalized signal. The analog pulse data recovery circuit is used to receive the first equalized signal and output a first recovered bit stream and a first recovered pulse according to an analog control voltage. The digital pulse data recovery circuit is used to receive the second equalized signal and the first recovered pulse and output a second recovered bit stream and a second recovered pulse according to a digital phase selection signal based on the phase selection of the first recovered pulse.

Description

Multi-channel receiver and signal receiving method thereof

technical field

The invention relates to a serial data connection receiver, in particular to a multi-channel receiver and its signal receiving method.

Background technique

Binary signaling is a general signaling architecture widely used in serial data connections. Here, the serial data connection is, for example, a High Definition Multi-media interface (HDMI).

In a serial data connection, a bit stream is transmitted from a transmitter to a receiver at a certain symbol rate (f _s ) via a communication channel (eg, a cable) according to the timing of the transmitter's clock. Each symbol within the bit stream represents either logical "1" data or logical "0" data (hereinafter referred to as "1" and "0", respectively). "1" is represented by the first level voltage of the symbol period (T _s ). Here, T _s =1/f _s . And "0" is represented by the voltage of the second level of the symbol period (T _s ). Thus, the bit stream is represented by a voltage signal that toggles between a first level and a second level according to the transmitted bit stream.

In order to obtain a better transmission rate, some serial data connections (such as HDMI) use multiple communication channels to transmit multiple bit streams simultaneously.

FIG. 1 is a schematic diagram of a conventional single-channel serial data connection receiver. Referring to FIG. 1 , the receiver 100 includes an equalizer 110 and a clock-data recovery (CDR) circuit 120 . Here, the equalizer 110 receives the received signal and outputs an equalized signal. The clock data recovery circuit 120 receives the equalized signal and outputs a recovered clock and a recovered bit stream.

The clock data recovery circuit 120 includes a binary phase detector (BPD) 121 , a CDR filter 122 and a clock generation circuit 123 . The binary phase detector 121 is coupled to the equalizer 110 , and the binary phase detector 121 , the CDR filter 122 and the clock generating circuit 123 are sequentially connected in series to form a loop.

The binary phase detector 121 receives the equalized signal and the recovered clock and outputs a recovered bit stream and a phase error signal. The CDR filter 122 receives the phase error signal and outputs a clock control signal. The clock generating circuit 123 receives the clock control signal and outputs a recovered clock.

FIG. 2 is a timing diagram of the receiver 100 in FIG. 1 . Referring to FIG. 2, since the dispersion phenomenon caused by the communication channel makes the received signal dispersed, the binary nature of the signal becomes less obvious. The receiver 100 in FIG. 1 is used to equalize the received signal so that the dispersion phenomenon is corrected and the resulting equalized signal has two different levels representing the bit stream transmitted by the transmitter.

The clock data recovery circuit 120 in FIG. 1 is used to properly establish the timing of the recovery clock, so that the rising edge of the recovery clock is aligned with the middle of the data bits of the bit stream (such as time points 201, 202, 203, 204, 205, 206, 207, 208) and the falling edge of the recovery clock is aligned with the transition of the bit stream (such as time points 211, 212, 213, 214). The recovered bit stream is conveniently generated by sampling the equalized signal with the rising edge of the recovered clock. Meanwhile, edge samples obtained by sampling the equalized signal with the falling edge of the recovered clock can be used to generate the phase error signal.

Ideally, the falling edge of the recovered clock is aligned with the bit transitions of the bit stream, so the resulting edge samples should have a non-statistical relationship to the bit stream. If the edge sampling is biased toward the recovery bit before the transition, it means that the timing of the recovery clock is too early. If the edge sampling is biased toward the recovery bit after the transition, it means that the timing of the recovery clock is too late. In this way, the phase error signal is generated by the binary phase detector 121 and used to adjust the timing of the recovered clock. The phase error signal is filtered by the CDR filter 122 to generate a clock control signal. The clock generating circuit 123 generates a recovered clock according to the clock control signal. Therefore, the recovery clock is controlled in a closed loop manner so as to be aligned with the timing of the equalized signal.

Receiver 100 in FIG. 1 is suitable for a single serial data connection. For multiple serial data connections, taking 4 channels as an example, 4 such receivers are required, and each receiver is used for one channel. Here, four receivers 100 of FIG. 1 can simply be used.

The clock data recovery circuit 120 in FIG. 1 generally has two architectures: an analog architecture and a digital architecture.

On analog architectures, the intermediate signals involved are analog in nature. The phase error signal is typically a current mode signal, and the CDR filter 122 is typically a load circuit comprising a resistor and capacitor in series. The clock control signal is usually a voltage signal, and the clock generating circuit 123 is usually a voltage-controlled oscillator (VCO).

On digital architectures, the intermediate signals involved are digital in nature. The phase error signal is usually a ternary digital signal, and the CDR filter 122 is usually a digital filter including a quadratic multiplier, an accumulator and an adder. The clock control signal is usually a phase selection code specifying the clock phase to be selected. The clock generating circuit 123 generally includes a phase selection circuit, and the phase selection circuit selects a clock phase from a plurality of clock phases in the multi-phase clock according to a phase selection code. Digital architecture is attractive because of its digital nature, so it helps to simplify the design using design automation tools, such as: logic synthesis and automatic place and route.

In addition, the performance of digital architectures is more consistent, more predictable, and less susceptible to noise, supply voltage variations, and temperature variations than analog architectures. Unfortunately, for high-speed serial connections of interest (eg, HDMI), the symbol rate is too high to allow the CDR circuit to operate at the same clock rate as the serial connection's symbol rate. Therefore, one is forced to resort to block processing, ie the phase error signal is buffered and processed into blocks. This allows the CDR circuit to operate at a clock rate lower than the symbol rate of the serial link. For example, if the block size is 10, then the phase error signal is buffered and processed at a rate of 10 samples at a time which is 10 times lower than the symbol rate. However, this introduces a delay in the CDR circuit and reduces the efficiency of clock recovery. Therefore, analog architectures generally have a high upper bound on clock recovery performance. The digital architecture is more in line with the evolution of the manufacturing process of modern CMOS (complementary metal oxide semiconductor) technology, and can continuously increase the circuit speed and reduce the circuit size. In other words, analog architectures cannot keep up with manufacturing process evolution, so they generally do not have the power and size efficiencies of digital architectures.

Contents of the invention

In one embodiment, a multi-channel receiver includes a first equalizer, a second equalizer, an analog clock data recovery circuit, and a digital clock data recovery circuit. The first equalizer is used for receiving a first received signal and outputting a first equalized signal. The second equalizer is used for receiving a second received signal and outputting a second equalized signal. The analog clock data recovery circuit is used for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock according to an analog control voltage. The digital clock data recovery circuit is used for receiving the second equalization signal and the first recovered clock, and outputting a second recovered bit stream and a second recovered clock according to a digital phase selection signal based on phase selection of the first recovered clock.

In some embodiments, the first recovered clock is generated by a voltage-controlled oscillator, and the voltage-controlled oscillator is controlled by an analog control voltage established in a closed loop, so that the timing of the first recovered clock is aligned with Timing of the first equalized signal.

In some embodiments, the second recovered clock is generated according to the phase selection of the first recovered clock by the digital phase selection signal, and the digital phase selection signal is established in a closed loop, so that the timings of the two recovered clocks are aligned at the timing of the second equalization signal.

In some embodiments, the analog clock data recovery circuit includes a binary phase detector, a charge pump, an analog loop filter, and a voltage controlled oscillator. The binary phase detector is used for receiving the first equalized signal and the first restored clock and outputting a first restored bit stream and a timing error signal. The charge pump is used for receiving the timing error signal and outputting a corrected current signal. The analog loop filter is used for receiving the correction current signal and outputting an analog control voltage. The voltage controlled oscillator is used for generating the first recovery clock under the control of the analog control voltage.

In some embodiments, the digital clock data recovery circuit includes a binary phase detector, a digital loop filter, a clock phase selector, and a division circuit. The binary phase detector is used for receiving the second equalized signal and outputting the second recovered bit stream and a timing error signal according to the second recovered clock and a divided down clock. The digital loop filter is used for receiving the timing error signal and outputting the digital phase selection signal according to the divided down clock. The clock phase selector is used for selecting and outputting the second recovered clock based on the phase of the first recovered clock under the control of the digital phase selection signal. The dividing circuit is used for dividing down the second recovery clock to generate the divided down clock.

Wherein, the clock phase selector may include a multiplexer. In addition, the clock phase selector may further include a phase interpolator.

In some embodiments, the digital clock data recovery circuit includes a logic circuit, and the logic circuit operates according to a divided down clock obtained by dividing down the second recovered clock.

In another embodiment, a signal receiving method of a multi-channel receiver includes: receiving a first received signal and a second received signal, equalizing the first received signal into a first equalized signal, and equalizing the second received signal into A second equalized signal, using an analog architecture to perform clock data recovery processing on the first equalized signal to output a first restored bit stream and a first restored clock, and using a digital architecture to perform clock data on the second equalized signal The recovery process is used to output a second recovery bit stream and a second recovery clock.

Description of drawings

FIG. 1 is a schematic diagram of a conventional single-channel serial data connection receiver.

FIG. 2 is a timing diagram of the receiver in FIG. 1 .

FIG. 3 is a schematic diagram of a 4-way receiver according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an embodiment of the equalizer in FIG. 3 .

FIG. 5A is a schematic diagram of an embodiment of the analog CDR circuit in FIG. 3 .

FIG. 5B is a timing diagram of the first recovery clock in FIG. 5A .

FIG. 5C is a functional block diagram of an embodiment of the BPD in FIG. 5A.

FIG. 5D is a schematic diagram of an embodiment of the charge pump and analog loop filter in FIG. 5A .

FIG. 5E is a schematic diagram of an embodiment of the VCO shown in FIG. 5A.

FIG. 6A is a functional block diagram of an embodiment of the digital CDR circuit in FIG. 3 .

FIG. 6B is a functional block diagram of an embodiment of the BBPD in FIG. 6A.

FIG. 6C is a functional block diagram of an embodiment of the digital loop filter in FIG. 6A .

FIG. 6D is a schematic diagram of an embodiment of the clock phase selector in FIG. 6A .

FIG. 6E is a schematic diagram of another embodiment of the clock phase selector in FIG. 6A .

FIG. 7 is a flowchart of a signal receiving method of a multi-channel receiver according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100 receivers

110 equalizer

120 clock data recovery (CDR) circuit

121 binary phase detector

122 CDR filters

123 clock generator circuit

201 points in time

202 points in time

203 points in time

204 points in time

205 points in time

206 points in time

207 points in time

208 points in time

211 points in time

212 points in time

213 points in time

214 points in time

3004 channel receiver

310 First Equalizer

311 Second equalizer

312 3rd equalizer

313 4th equalizer

320 Analog CDR circuit

321 The first digital CDR circuit

322 Second digital CDR circuit

323 Third digital CDR circuit

400 equalizer

401 transistor

402 transistors

411 resistance

412 resistors

421 Current Source

422 current source

431 resistance

432 capacitance

500 Analog CDR circuit

510 Binary Phase Detector (BPD)

511 First data flip-flop (DFF)

512 Second DFF

513 Third DFF

514 Fourth DFF

515 BPD logic unit

520 charge pump

521 current source

522 First switch

523 Second switch

524 current bath

530 Analog Loop Filter

531 resistance

532 capacitance

540 Voltage Controlled Oscillator

541 Voltage Controlled Delay Unit

542 Voltage Controlled Delay Unit

543 Voltage Controlled Delay Unit

544 Voltage Controlled Delay Unit

551 rising edge

552 Rising edge

553 Rising edge

554 rising edge

600 digital CDR circuit

610 Block Binary Phase Detector

611 BPD

612 Extract logic circuits

620 Serial Parallel Converter

621 Serial Data Buffer

622 serial data buffer

623 serial data buffer

624 serial data buffer

625 parallel data buffers

626 parallel data buffers

627 parallel data buffer

628 parallel data buffers

629 parallel data buffers

630 Digital Loop Filter

631 Digital Filter

632 delta-sigma modulator

640 Clock Phase Selector

650 divide by 5 circuit

660 multiplexer

670 clock selection circuit

671 The first multiplexer

672 Second multiplexer

673 phase interpolator

R0 first received signal

R1 second received signal

R2 The third received signal

R3 The fourth received signal

S0 first equalized signal

S1 second equalization signal

S2 third equalization signal

S3 Fourth equalization signal

D0 first recovery bit stream

D1 second recovery bit stream

D2 third recovery bit stream

D3 Fourth recovery bit stream

CK0 first recovery clock

CK1 second recovery clock

CK2 Third Recovery Clock

CK3 fourth recovery clock

R0+ positive terminal receives signal

R0－ The negative terminal receives the signal

S0+ Positive balanced signal

S0－ Negative balance signal

VDD supply node

TE0 First timing error signal

TE1 Second timing error signal

CC corrected current signal

VC control voltage

CK0[7:0] First recovery clock

CK0[0] First recovery clock

CK0[1] First recovery clock

CK0[2] First recovery clock

CK0[3] First recovery clock

CK0[4] First recovery clock

CK0[5] First recovery clock

CK0[6] First recovery clock

CK0[7] First recovery clock

T _s clock period

D0d Delay signal

E0 edge sampling

E0s synchronous edge sampling

UP first logic signal

DN second logic signal

PH phase selection signal

CK1DD has been clocked down

TES serial timing error signal

TEP[0]～TEP[4] Parallel timing error signal

FTE filtered timing error signal

710 Receive a first received signal and a second received signal

720 Respectively equalize the first received signal and the second received signal into a first equalized signal and a second equalized signal

730 Perform clock data recovery processing on the first equalized signal using an analog architecture with a voltage controlled oscillator, wherein the analog architecture includes a voltage controlled oscillator to output a first restored bit stream and a first restored clock

740 performs clock data recovery processing on the second equalized signal using a digital architecture, wherein the digital architecture includes clock phase selection, and the clock phase selection is obtained from Refer to the timing of the first recovered clock

detailed description

The present invention relates to a multiple serial connection receiver. Herein, the description discloses several embodiments, but it should be understood that the present invention can be implemented in various ways, and is not limited to the specific examples described below or specific methods for implementing any features of these examples. In other instances, details known to the public are not shown or described in order to avoid obscuring technical characteristics of the present invention.

In this paper, a clock-data recovery (CDR) circuit/architecture belongs to an analog CDR circuit/architecture when a VCO controlled by an analog voltage is used to generate a recovery clock. Under the analog CDR circuit/architecture, the recovery clock is adjusted in a closed-loop manner by establishing an appropriate value of the analog voltage.

A CDR circuit/architecture is a digital CDR circuit/architecture when a recovered clock is generated (based on a multi-phase clock) using a phase selection circuit (or clock phase selector) controlled by a digital phase selection signal. Under the digital CDR circuit/architecture, the recovery clock is adjusted in a closed loop manner by establishing the appropriate value of the phase selection signal.

Take 4 serial data connections as an example, but not limited thereto. A 4-way serial data connection consists of simultaneously transmitting 4 independent bit streams from the transmitter to the receiver via the communication channel. Although four independent bit streams are transmitted, the transmitter uses a common clock source as a timing reference, and this timing reference is usually from a phase lock loop (phase lock loop) locked to the timing of the local crystal oscillator; PLL) output. Therefore, in the case of receiving at the receiver, although the 4-bit streams will have a timing skew due to the mismatch of channel lengths between the 4 communication channels, the 4-bit streams will still track each other in timing.

FIG. 3 is a schematic diagram of a 4-way receiver according to an embodiment. With reference to Fig. 3, based on above-mentioned characteristics, 4-way receiver 300 comprises a first equalizer 310, an analog CDR circuit 320, a second equalizer 311, a third equalizer 312, a fourth equalizer 313, a first A digital CDR circuit 321 , a second digital CDR circuit 322 and a third digital CDR circuit 323 .

The first equalizer 310 receives a first received signal R0 and outputs a first equalized signal S0. The analog CDR circuit 320 receives the first equalized signal S0, and outputs a first recovered clock CK0 and a first recovered bit stream D0. The second equalizer 311 receives a second received signal R1 and outputs a second equalized signal S1. The first digital CDR circuit 321 receives the second equalized signal S1 and the first restored clock CK0 , and outputs a second restored clock CK1 and a second restored bit stream D1 . The third equalizer 312 receives a third received signal R2 and outputs a third equalized signal S2. The second digital CDR circuit 322 receives the third equalized signal S2 and the first restored clock CK0 , and outputs a third restored clock CK2 and a third restored bit stream D2 . The fourth equalizer 313 receives a fourth received signal R3 and outputs a fourth equalized signal S3. The third digital CDR circuit 323 receives the fourth equalized signal S3 and the first recovered clock CK0 , and outputs a fourth recovered clock CK3 and a fourth recovered bit stream D3 .

The analog CDR circuit 320 is designed to have high performance clock recovery such that the first recovered clock CK0 successfully tracks the timing reference. Also, the timing of the first received signal R0 is initially established at the transmitter according to the timing reference.

Furthermore, using an analog architecture allows the CDR circuit to have a higher upper limit on the performance of clock recovery. In addition, although the received signals have their time offsets, the timing of the first received signal R0 can successfully track the first received signal R1 , the third received signal R2 and the fourth received signal R3 respectively. Moreover, although the received signals have their time deviations, the first recovered clock CK0 can successfully track the second received signal R1 , the third received signal R2 and the fourth received signal R3 respectively.

Therefore, when the first recovered clock CK0 is provided to the first digital CDR circuit 321, the second digital CDR circuit 322 and the third digital CDR circuit 323 as a timing reference, the three digital CDR circuits 321, 322, 323 only It is only necessary to detect timing deviations between the first received signal R0 and the other three received signals R1 , R2 , R3 . In this way, the difficulty of clock recovery of the three digital CDR circuits 321 , 322 , 323 is greatly eased, so even if a digital architecture is used, high-performance clock recovery is still possible. Therefore, the problem of insufficient performance of the digital architecture is avoided, while the advantages of the digital architecture are fully preserved. By using an analog CDR circuit 320 and three digital CDR circuits 321, 322, 323, the 4-way receiver 300 has the advantages of both the analog and digital architectures of CDR.

FIG. 4 is a schematic diagram of an embodiment of the equalizer 310 in FIG. 3 . Referring to FIG. 4, the equalizer 400 utilizes a differential signaling architecture. Wherein, the first received signal R0 includes a positive-end received signal R0+ and a negative-end received signal R0−, and the first equalized signal S0 includes a positive-end equalized signal S0+ and a negative-end equalized signal S0−. The equalizer 400 includes a differential pair, two resistors 411, 412, two current sources 421, 422, and a parallel resistor-capacitor (RC) circuit. Here, the differential pair has two transistors 401, 402 and provides a gain. In some embodiments, the transistors 401 and 402 may be N-channel metal oxide semiconductor (NMOS) transistors. Resistors 411, 412 provide a load, and current sources 421, 422 provide a bias voltage. The parallel RC circuit has a resistor 431 and a capacitor 432 in parallel and provides source degeneration. In the drawings, VDD represents a power supply node. Since the detailed circuit operation of the equalizer 400 is well known in the art, it is not repeated here. In addition, the equalizers 311 , 312 , and 313 in FIG. 3 can also be implemented using the same circuit as the equalizer 400 .

FIG. 5A is a schematic diagram of an embodiment of the analog CDR circuit 320 in FIG. 3 . 5A, the analog CDR circuit 500 includes a binary phase detector (binary phase detector; BPD) 510, a charge pump 520, an analog loop filter 530, and a voltage-controlled oscillator (voltage-controlled oscillator; VCO )540.

Take the first recovered clock CK0 as an eight-phase clock (hence marked as CK0[7:0]) as an example, but not limited thereto. The BPD 510 receives the first equalized signal S0 and the first restored clock CK0 [7:0], and outputs the first restored bit stream D0 and a first timing error signal TE0 . The charge pump 520 receives the first timing error signal TE0 and outputs a corrected current signal CC. The analog loop filter 530 receives the corrected current signal CC and outputs a control voltage VC. The VCO 540 receives the control voltage VC, and outputs the first recovery clock CK0[7:0]. Here, the control voltage VC is an analog signal.

FIG. 5B is a timing diagram of the first recovery clock CK0[7:0]. Referring to FIG. 5B , the first recovered clock CK0 [7:0] is an eight-phase clock. The eight-phase clock has eight phases (phases 0, 1, 2, 3-7), and the eight phases are uniformly shifted during the clock period T _s . As shown in the figure, the time difference between the rising edge 551 and the next rising edge 552 of the first recovered clock CK0[0] (phase 0) is the clock period T _s . The time difference between the rising edge 551 of the first recovered clock CK0[0] (phase 0) and the rising edge 553 of the first recovered clock CK0[1] (phase 1) is one-eighth of the clock period T _s /8. There are 4 phase shifts (phase steps) between the first recovered clock CK0[0] and the first recovered clock CK0[4]. Therefore, on the rising edge 551 of the first recovered clock CK0[0] (phase 0) The time difference from the rising edge 554 of the first recovery clock CK0[4] (phase 4) is one-half of the clock period T _s /2.

FIG. 5C is a functional block diagram of an embodiment of BPD 510 in FIG. 5A . Referring to FIG. 5C , the BPD 510 includes a first data flip-flop (data flip-flop; DFF) 511 , a second DFF 512 , a third DFF 513 , a fourth DFF 514 , and a BPD logic unit 515 .

The first DFF 511 is triggered on the rising edge of the first restored clock CK0[0] to receive the first equalized signal S0 and output the first restored bit stream D0. The second DFF 512 is triggered on the rising edge of the first restored clock CK0[0] to receive the first restored bit stream D0 and output a delayed signal D0d. The delay signal D0d is the unit-cycle delay of the first recovery bit stream D0. The third DFF 513 is triggered on the falling edge of the first recovery clock CK0[0] to receive the first equalization signal S0 and output an edge sample E0. The fourth DFF 514 is triggered on the rising edge of the first recovery clock CK0[0] to receive the edge sample E0 and output a synchronous edge sample E0s. The BPD logic unit 515 receives the first recovery bit stream D0, the delay signal D0d and the synchronization edge sample E0s, and outputs a first timing error signal TE0. The first timing error signal TE0 is a ternary signal having one of three possible values (ie, 0, 1, and -1).

The BPD logic unit 515 is a logic circuit that executes the logic operation described in the following C language code.

In terms of circuit implementation, the first timing error signal TE0 is represented by a first logic signal UP and a second logic signal DN. It should be noted that each logic signal has one of two possible values (ie, 1 and 0). When the first timing error signal TE0 is 0, both the first logic signal UP and the second logic signal DN are 0; when the first timing error signal TE0 is 1, the first logic signal UP is 1 and the second logic signal DN is 0; and when the first timing error signal TE0 is −1, the first logic signal UP is 0 and the second logic signal DN is 1.

FIG. 5D is a schematic diagram of an embodiment of the charge pump 520 and the analog loop filter 530 in FIG. 5A . Referring to FIG. 5D , the charge pump 520 includes a current source 521 , a first switch 522 , a second switch 523 and a current sink 524 .

The first switch 522 is controlled by a first logic signal UP, and the second switch 523 is controlled by a second logic signal DN. The generated corrected current signal CC is a current mode signal. It should be noted that, as mentioned above, the first logic signal UP and the second logic signal DN are two logic signals representing the first timing error signal TE0. When both the first logic signal UP and the second logic signal DN are 0, the first switch 522 and the second switch 523 are turned off, so the corrected current signal CC is 0. When the first logic signal UP is 1 and the second logic signal DN is 0, the corrected current signal CC is positive, that is, the current flows from the charge pump 520 to the analog loop filter 530 . When the first logic signal UP is 0 and the second logic signal DN is 1, the corrected current signal CC is negative, that is, the current flows back from the analog loop filter 530 to the charge pump 520 . The analog loop filter 530 includes a resistor 531 and a capacitor 532 connected in series, and effectively converts the corrected current signal CC into a control voltage VC.

FIG. 5E is a schematic diagram of an embodiment of the VCO 540 in FIG. 5A . Referring to FIG. 5E , the VCO 540 is a 4th-order ring oscillator, and it includes four voltage-controlled delay units 541 , 542 , 543 , 544 . The voltage-controlled delay units 541, 542, 543, 544 are configured in a ring architecture. The voltage-controlled delay units 541 , 542 , 543 , and 544 receive the control voltage VC and output eight-phase clocks (the first recovery clock CK0 [7:0]). Each of the voltage-controlled delay units 541 , 542 , 543 , 544 receives a differential output signal from a preceding circuit, and outputs a differential output signal to a subsequent circuit.

For example, the voltage-controlled delay unit 541 receives a differential input signal having a positive first recovered clock CK0[7] and a negative first recovered clock CK0[7], and outputs the first recovered clock with a positive The differential output signal of CK0[0] and the first recovered clock CK0[4] at the negative terminal.

Herein, each of the voltage-controlled delay units 541 , 542 , 543 , and 544 can be implemented as a voltage-controlled delay circuit disclosed in US Patent Application Publication No. US2013/0106515.

FIG. 6A is a functional block diagram of an embodiment of the digital CDR circuit 321 in FIG. 3 . Referring to FIG. 6A , the digital CDR circuit 600 includes a block binary phase detector (BBPD) 610 , a digital loop filter 630 , a clock phase selector 640 , and a divide-by-5 circuit 650 .

The BBPD 610 receives the second equalized signal S1, and outputs the second recovered bit stream D1 and the second timing error signal TE1 according to the second recovered clock CK1 and the divided-down clock CK1DD. The digital loop filter 630 receives the second timing error signal TE1 and outputs the phase selection signal PH according to the divided down clock CK1DD. The clock phase selector 640 receives the phase selection signal PH and the first recovered clock CK0 [7:0], and outputs the second recovered clock CK1 . The divide-by-5 circuit 650 receives the second restored clock CK1 and outputs a divided down clock CK1DD. Here, the speed of the divided down clock CK1DD is five times lower than the symbol rate of the bit stream in the second equalized signal S1. It should be noted that in this exemplary embodiment, the block size of the block processing is 5, but the invention is not limited thereto. Here, the phase selection signal PH is a digital signal.

FIG. 6B is a functional block diagram of an embodiment of the BBPD 610 in FIG. 6A. Referring to FIG. 6B , the BBPD 610 includes a BPD 611 , a serial-to-parallel converter (S/P converter) 620 , and a decimation logic circuit 612 .

The BPD 611 receives the second equalized signal S1, and outputs the second restored bit stream D1 and the serial timing error signal TES according to the second restored clock CK1. The serial-to-parallel converter 620 converts the serial timing error signal TES into parallel timing error signals TEP[4:0] (ie, TEP[0], TEP[1], TEP[2], TEP[3 ] and TEP[4]). The serial timing error signal TES is in the clock domain of the second recovered clock CK1 , and the parallel timing error signal TEP[4:0] is in the clock domain of the divided down clock CK1DD. The decimation logic circuit 612 receives the parallel timing error signal TEP[4:0], and outputs a second timing error signal TE1.

Among them, BPD611 can be realized by BPD510 in Fig. 5A. At this time, the first equalization signal S0, the first recovery clock CK0[0] and the first timing error signal TE0 are respectively used to replace the second equalization signal S1, the second recovery clock pulse CK1 and the serial timing error signal TES.

In some embodiments, the serial-to-parallel converter 620 includes 4 serial data buffers 621 , 622 , 623 , 624 and 5 parallel data buffers 625 , 626 , 627 , 628 , 629 . Here, the serial data buffers 621, 622, 623, and 624 are triggered by the rising edge of the second recovery clock CK1, while the parallel data buffers 625, 626, 627, 628, and 629 are triggered by the divided falling clock pulse. Triggered by the rising edge of CK1DD.

In one embodiment, the extraction logic circuit 612 can be a logic circuit that executes the following algorithm written in C language.

FIG. 6C is a functional block diagram of an embodiment of the digital loop filter 630 in FIG. 6A . In one embodiment, referring to FIG. 6C , the digital loop filter 630 includes a digital filter 631 and a delta-sigma modulator (DSM) 632 .

The circuit symbol of the digital filter 631 is generally H(Z), and is clocked with the divided down clock CK1DD. The digital filter 631 receives the second timing error signal TE1 and outputs a filtered timing error signal FTE. Delta-sigma modulator 632 is also clocked with the divided down clock CK1DD. The delta-sigma modulator 632 receives the filtered timing error signal FTE and outputs a phase selection signal PH.

In one embodiment, the digital filter 631 can perform a transfer function (H(z)) represented by a Z-transform as described below.

Wherein, K _p and K _i are two parameters. In one embodiment, K _i =0, thus H(z)=K _p .

In one embodiment, the digital filter 631 only includes a multiplier. The DSM 632 is used to truncate the filtered timing error signal FTE so that the generated phase selection signal PH is the same as the subsequent clock phase selector 640 in FIG. 6A . Using a DSM to truncate a signal, rather than truncating the signal directly, is a way to reduce the adverse effects of information loss due to truncation. This reduction method is well known in the art, so it will not be repeated here.

FIG. 6D is a schematic diagram of an embodiment of the clock phase selector 640 in FIG. 6A . Referring to FIG. 6D, a multiplexer 660 is adapted to implement the clock phase selector 640 in FIG. 6A, and is used to select a phase of the first recovered clock CK0[7:0] having eight phases according to the phase selection signal PH. . In order to be suitable for using the multiplexer 660 to implement the clock phase selector 640, the phase selection signal PH must be an integer (this can be satisfied by using the DSM shown in FIG. 6C to generate the phase selection signal PH.)

It should be noted that the modulo 8 (modulo8) nature of the eight-phase clock PH=8 is equal to PH=0, PH=9 is equal to PH=1, and PH=-1 is equal to PH=7, etc. Thus, the phase selection signal PH is implicitly limited to eight values: 0, 1, 2, 3, 4, 5, 6, and 7 due to the implicit modulo-8 nature.

The multiplexer 660 outputs the second recovered clock CK1 by selecting one of eight phases of the first recovered clock CK0 [7:0] according to the value of the phase selection signal PH.

For example, if the phase selection signal PH is 2, the multiplexer 660 selects the first recovered clock CK0[2] as the second recovered clock CK1. If the phase selection signal PH is 5, the multiplexer 660 selects the first restored clock CK0[5] as the second restored clock CK1.

In another embodiment, referring to FIG. 6E , a clock selection circuit 670 is used to implement the clock phase selector 640 in FIG. 6A . In order to be suitable for use with the clock selection circuit 670, the phase selection signal PH includes an integer part (labeled int(PH) in the figure, and is implicitly limited to eight values: 0, 1, 2, 3, 4, 5, 6 and 7) and the fractional part (marked as frac(PH) in the figure). The clock selection circuit 670 includes a first multiplexer 671 , a second multiplexer 672 , and a phase interpolator 673 .

The first multiplexer 671 outputs a first selected phase CKA from the first recovered clock CK0[7:0] according to the value of the integer part int(PH). The second multiplexer 672 outputs a second selected phase CKB from the first recovered clock CK0[7:0] according to the value of the integer part int(PH)+1. It should be noted that if the integer part int(PH)+1 is equal to 8, it is the same as 0 due to the modulo 8 nature of the clock phase. The phase interpolator 673 outputs the second recovered clock CK1 by performing phase interpolation between the first selected phase CKA and the second selected phase CKB.

By way of example, but not limitation, the fractional part frac(PH) is truncated by the DSM within the digital loop filter 630 to 4 possible values (i.e., 0, 1/4, 1/2, and 3/4 ) of one.

The phase interpolator 673 performs phase interpolation by combining (1-fractional part frac(PH))*100% of the first selected phase CKA and fractional part frac(PH)*100% of the second selected phase CKB. For example, if the phase selection signal PH is Since the integer part int(PH) is 3, the first recovered clock CK0[3] and the first recovered clock CK0[4] are respectively selected as the first selected phase CKA and the second selected phase CKB. And, since the fractional part frac(PH) is The second recovered clock CK1 is obtained by combining 75% of the first recovered clock CK0[3] and 25% of the first recovered clock CK0[4]. If the phase selection signal PH is Since the integer part int(PH) is 5, the first recovered clock CK0[5] and the first recovered clock CK0[6] are respectively selected as the first selected phase CKA and the second selected phase CKB. And, since the fractional part frac(PH) is The second recovered clock CK1 is obtained by combining 25% of the first recovered clock CK0[5] with 75% of the first recovered clock CK0[6]. If the phase selection signal PH is Since the integer part int(PH) is 7, the first recovered clock CK0[7] and the first recovered clock CK0[0] are respectively selected as the first selected phase CKA and the second selected phase CKB. And, since the fractional part frac(PH) is The second recovered clock CK1 is obtained by combining 50% of the first recovered clock CK0[7] with 50% of the first recovered clock CK0[0]. If the phase selection signal PH is 2, since the integer part int(PH) is 2, the first restored clock CK0[2] and the first restored clock CK0[3] are respectively selected as the first selected phase CKA and the second Selected phase CKB. And, since the fractional part frac(PH) is 0, the second recovered clock CK1 is obtained by combining 100% of the first recovered clock CK0[2] and 0% of the first recovered clock CK0[3]. The phase interpolation performed by combining two adjacent phases in a multi-phase clock with a specific percentage (or ratio) is well known in the art, and thus will not be described again.

The divide-by-5 circuit 650 in FIG. 6A can be implemented as a synchronous counter. Here, the synchronous counter is well known in the art, so details are not repeated here.

In one embodiment, the circuit structure of the CDR600 can be used to realize the digital CDR322, 323 in FIG. 3 by simply changing the interface signals correspondingly, for example: replacing the second equalized signal S1, S1, and S3 with the third equalized signal S2 and the fourth equalized signal S3. The second recovery bit stream D1 is replaced by the third recovery bit stream D2 and the fourth recovery bit stream D3 , and the second recovery clock CK1 is replaced by the third recovery clock CK2 and the fourth recovery clock CK3 .

Although it is shown in the figure that the first recovered clock CK0 is directly transmitted to the digital CDR circuits 321, 322, 323, it only uses the timing of the first recovered clock CK0 to improve the performance of the digital CDR circuits 321, 322, 323 An example of . Without departing from the scope of the present invention, as long as the digital CDR circuits 321 , 322 , and 323 use the timing referenced to the first recovered clock CK0 , other embodiments are also possible. For example, in an alternative embodiment, instead of directly transmitting to the digital CDR circuits 321, 322, 323, a phase lock loop (phase lock loop; PLL) (not shown) is provided between the analog CDR circuit 320 and each between the digital CDR circuits 321 , 322 , and 323 , and is used to generate a derived clock whose phase is locked with the first recovered clock CK0 , and then output the derived clock to the digital CDR circuits 321 , 322 , 323 . This alternate embodiment provides the flexibility to allow the use of PLLs to generate the multiphase clocks (which are the signals required by the digital CDR circuits 321 , 322 , 323 ), thereby replacing the need for the analog CDR circuit 320 to generate the multiphase clocks directly. Wherein, the PLL is well known in the art, so details are not repeated here.

Although a 4-channel receiver 300 is shown in the figure, this is not a limitation of the present invention, and the present invention can be applied to any M-channel receiver, and M is an integer greater than 1. Among the M channels of the M receivers, one channel uses an analog CDR architecture to generate the first recovered clock, and the rest uses a digital CDR architecture that refers to the timing of the first recovered clock.

FIG. 7 is a flowchart of a signal receiving method of a multi-channel receiver according to an embodiment of the present invention. Referring to Fig. 7, the signal receiving method comprises receiving a first received signal and a second received signal (step 710), respectively equalizing the first received signal and the second received signal to be a first equalized signal and a second equalized signal (step 720), using an analog architecture to perform clock data recovery processing on the first equalized signal to output a first restored bit stream and a first restored clock (step 730), and using a digital architecture to perform time pulse data recovery processing on the second equalized signal Data recovery processing to output a second recovery bit stream and a second recovery clock (step 740). Here, the analog architecture includes a voltage controlled oscillator. The digital architecture includes clock phase selection, and the clock phase selection is derived from the timing of the first recovered clock.

Although the present invention is disclosed above with the foregoing embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of patent protection shall be defined by the claims attached to this specification.

Claims (21)

1. A multi-channel receiver for simultaneously receiving multiple signals using a common clock source as a timing reference, the multi-channel receiver comprising: A first equalizer, used to receive a first received signal in the multiple signals and output a first equalized signal; A second equalizer, used to receive a second received signal in the multiple signals and output a second equalized signal; an analog clock data recovery circuit for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock according to an analog control voltage; and A digital clock data recovery circuit for receiving the second equalization signal and the first recovered clock and outputting a second recovered bit stream and a first recovered clock according to a digital phase selection signal based on phase selection of the first recovered clock Second, restore the clock. 2. The multi-channel receiver according to claim 1, wherein the first recovery clock is generated by a voltage-controlled oscillator, and the voltage-controlled oscillator is controlled by the analog control voltage established in a closed loop, so that the timing of the first recovered clock is aligned with the timing of the first equalized signal. 3. The multi-channel receiver according to claim 1, wherein the second recovered clock is generated according to the phase selection of the first recovered clock by the digital phase selection signal, and the digital phase selection signal is closed A loop is established such that the timing of the second recovered clock is aligned with the timing of the second equalized signal. 4. The multiplex receiver according to any one of claims 1 to 3, wherein the analog clock data recovery circuit comprises: a binary phase detector for receiving the first equalized signal and the first recovered clock and outputting the first recovered bit stream and a timing error signal; a charge pump for receiving the timing error signal and outputting a corrected current signal; an analog loop filter for receiving the modified current signal and outputting the analog control voltage; and A voltage-controlled oscillator is used to generate the first recovery clock under the control of the analog control voltage. 5. The multiplex receiver according to claim 4, wherein the binary phase detector comprises: a first data flip-flop, used to receive the first equalization signal and the first restored clock, and output the first restored bit stream according to the trigger of the first restored clock; a second data flip-flop, used to receive the first restored bit stream and the first restored clock, and output a delay signal according to the trigger of the first restored clock; A third data flip-flop, used to receive the first equalization signal and the first restored clock, and output an edge sampling signal according to the trigger of the first restored clock; A fourth data flip-flop, used to receive the edge sampling signal and the first recovered clock, and output a synchronous edge sampling signal according to the trigger of the first recovered clock; and A logic unit is used for receiving the first restored bit stream, the delayed signal and the synchronous edge sampling signal, and outputting the timing error signal according to the first restored bit stream, the delayed signal and the synchronous edge sampled signal. 6. The multi-channel receiver according to claim 4, wherein the charge pump comprises: a current source; A first switch, connected in series with the current source, is closed or opened according to the control of a first logic signal; a second switch, connected in series with the first switch, closed or opened according to the control of a second logic signal; and a current sink connected in series with the second switch; Wherein the first logic signal and the second logic signal are two logic signals representing the timing error signal; Wherein the output of the modified current signal is controlled according to the closing or opening of the first switch and the second switch. 7. The multi-channel receiver as claimed in claim 4, wherein the voltage controlled oscillator is a ring oscillator. 8. The multiplex receiver according to any one of claims 1 to 3, wherein the digital clock data recovery circuit comprises: a binary phase detector for receiving the second equalized signal and outputting the second recovered bit stream and a timing error signal according to the second recovered clock and a divided down clock; a digital loop filter for receiving the timing error signal and outputting the digital phase selection signal according to the divided down clock; a clock phase selector, configured to select and output the second recovered clock based on the phase of the first recovered clock under the control of the digital phase selection signal; and A dividing circuit is used for dividing down the second recovery clock to generate the divided down clock. 9. The multi-channel receiver according to claim 8, wherein the binary phase detector comprises: a second binary phase detector for receiving the second equalization signal and the second recovered clock, and outputting the second recovered bit stream and a serial timing error signal according to the second recovered clock; a serial-to-parallel converter for converting the serial timing error signal into a parallel timing error signal according to the second recovered clock and the divided down clock; and A decimation logic unit is used for receiving the parallel timing error signal and outputting the timing error signal. 10. The multiplex receiver according to claim 8, wherein the clock phase selector comprises a multiplexer. 11. The multiplex receiver according to claim 10, wherein the clock phase selector further comprises a phase interpolator for receiving the output of the multiplexer. 12. The multi-channel receiver according to claim 8, wherein the digital loop filter comprises a digital filter and a delta-sigma modulator, and the delta-sigma modulator is used to receive the output of the digital filter. 13. The multi-channel receiver as claimed in claim 8, wherein the dividing circuit is a synchronous counter. 14. The multi-channel receiver according to any one of claims 1 to 3, wherein the digital clock data recovery circuit comprises: a logic circuit, according to an already obtained by dividing and dropping the second recovery clock In addition to descending clock operation. 15. A signal receiving method of a multi-channel receiver, characterized in that, comprising: receiving a first received signal and a second received signal simultaneously through mutually independent communication channels, the first received signal and the second received signal use a common clock source as a timing reference; equalizing the first received signal into a first equalized signal; equalizing the second received signal into a second equalized signal; performing clock data recovery processing on the first equalized signal by using an analog framework to output a first recovered bit stream and a first recovered clock; and A digital architecture is used to receive the second equalized signal and the first restored clock and output a second restored bit stream and a second restored clock according to a digital phase selection signal based on phase selection of the first restored clock. 16. The signal receiving method of the multi-channel receiver according to claim 15, wherein the analog architecture includes using a voltage controlled oscillator. 17. The signal receiving method of a multi-channel receiver according to claim 16, wherein the voltage-controlled oscillator is controlled by an analog control voltage established in a closed loop so that the timing of the first recovery clock is aligned with the Timing of the first equalized signal. 18. The signal receiving method of a multi-channel receiver according to claim 17, wherein the phase selection is controlled by the digital phase selection signal established with the closed loop, so that the timing of the second recovered clock is aligned at the timing of the second equalization signal. 19. The signal receiving method of a multi-channel receiver according to claim 18, wherein the digital phase selection signal is generated by a logic circuit operating under a divided down clock, and the divided down clock is obtained by dividing the second recovery clock. 20. The signal receiving method of the multi-channel receiver according to claim 19, wherein the logic circuit comprises a delta-sigma modulator. 21. The signal receiving method of a multi-channel receiver according to claim 18, wherein the digital phase selection comprises a phase interpolation of the first recovered clock.