CN104752498A - MOS (Metal Oxide Semiconductor) structure with higher dielectric constant and preparation method thereof - Google Patents

Abstract

The invention provides an MOS (Metal Oxide Semiconductor) structure with a higher dielectric constant and a preparation method thereof. The MOS structure comprises a semiconductor substrate, a gate dielectric film deposited on a semiconductor and a metal gate electrode deposited by adopting a physical vapor deposition method, wherein the gate dielectric film is a hafnium-based multibasic oxide, namely HfLaTiOx or HfLaTaOx. The preparation method for the MOS structure comprises the following steps of (1) cleaning the semiconductor substrate and removing organic pollutants, mote, metal ions and an oxide layer on the surface of the semiconductor substrate; (2) depositing the gate dielectric film on the semiconductor substrate by adopting a physical vapor deposition method, a chemical vapor deposition method or an atomic layer deposition method; and (3) depositing the metal gate electrode on the gate dielectric film by adopting the physical vapor deposition method so as to obtain the MOS structure. In the MOS structure, the gate dielectric film is in an amorphous state and is stable in structure. The MOS structure has smaller leakage current density and higher dielectric constant. The preparation method for the MOS structure is simple and good in repeatability.

Description

A kind of MOS structure with higher dielectric constant and its preparation method

technical field

The invention relates to a MOS structure with a higher dielectric constant and a preparation method thereof, belonging to the technical field of semiconductors.

Background technique

Hf-based high dielectric constant gate dielectric materials have been widely used instead of traditional silicon dioxide in the technology node of integrated circuits 45nm and below. At present, the dielectric constant of Hf-based high-K gate dielectric materials (mainly HfSiON) widely used in the industry usually does not exceed 20. With the further development of integrated circuit technology, such a K value will not be able to meet the needs of applications in 14nm and later technology nodes. Therefore, seeking a gate dielectric material with a higher dielectric constant (K>30) has become a current research focus.

Transition metal oxides such as TiO ₂ , Ta ₂ O ₅ and rare earth oxides La ₂ O ₃ have very high dielectric constants. However, a higher dielectric constant usually leads to a too small band gap, which in turn leads to a large leakage current; at the same time, TiO ₂ is not stable on Si substrates. Doping a small amount of transition metal oxides into the composite oxide of La ₂ O ₃ and HfO ₂ , combining the excellent characteristics of the three, can improve the dielectric constant while maintaining good thermal stability and interface. characteristics and low leakage current.

Contents of the invention

The object of the present invention is to provide a MOS structure with a higher dielectric constant, which has a lower leakage current density while the MOS structure has a higher dielectric constant.

Another object of the present invention is to provide a method for preparing the MOS structure.

To achieve the above object, the present invention adopts the following technical solutions:

A MOS structure with a higher dielectric constant, including a semiconductor substrate, a gate dielectric film deposited on the semiconductor, and a metal gate electrode deposited by physical vapor deposition, wherein the gate dielectric film is hafnium-based multi-component oxide HfLaTiO _x or HfLaTaO _x .

The mass ratio of TiO ₂ or Ta ₂ O ₅ doped in the hafnium-based multi-component oxide is 2%-10%.

The gate dielectric film is amorphous.

The semiconductor substrate may be Si, InP, Ge, GaAs, InGaAs, SOI and the like.

The metal gate electrode is Pt, W, TiN, TaN or a combination thereof.

The deposition method of the gate dielectric thin film may be physical vapor deposition, chemical vapor deposition or atomic layer deposition.

The dielectric constant of the gate dielectric film is 30-56. When the physical thickness of the gate dielectric film is 6nm, the leakage current density of the MOS structure is less than or equal to 10 ^-6 A/cm at a gate voltage of -1 volt. ² .

A preparation method of the MOS structure, comprising the following steps:

(1) Clean the semiconductor substrate to remove organic pollutants, dust, metal ions and oxide layers on the surface;

(2) Depositing a gate dielectric thin film on the semiconductor substrate by physical vapor deposition, chemical vapor deposition or atomic layer deposition;

(3) A metal gate electrode is deposited on the gate dielectric film by a physical vapor deposition method to obtain a MOS structure.

The advantages of the present invention are:

(1) The gate dielectric film in the MOS structure of the present invention is amorphous and has a stable structure.

(2) MOS structure of the present invention has less leakage current density and higher dielectric constant, and the dielectric constant of gate dielectric film is about 30～56, when the physical thickness of this gate dielectric layer film is 6nm, in When the gate voltage is 1 volt, the leakage current density of the MOS structure is less than or equal to 10 ^-6 A/cm ² .

(3) The preparation method of the MOS structure of the present invention is simple and reproducible.

Description of drawings

FIG. 1 is a high-frequency capacitance-voltage (C-V) curve diagram of the MOS structure prepared in Example 1 of the present invention.

FIG. 2 is a graph of the leakage current performance (I-V) of the MOS structure prepared in Example 1 of the present invention.

3 is a high-frequency capacitance-voltage (C-V) curve diagram of the MOS structure prepared in Example 2 of the present invention.

FIG. 4 is a graph of the leakage current performance (I-V) of the MOS structure prepared in Example 2 of the present invention.

FIG. 5 is a high-frequency capacitance-voltage (C-V) curve diagram of the MOS structure prepared in Example 3 of the present invention.

FIG. 6 is a graph of the leakage current performance (I-V) of the MOS structure prepared in Example 3 of the present invention.

Detailed ways

The present invention will be further described below through embodiment.

Example 1

A method for preparing a MOS structure with a higher dielectric constant, the specific steps are as follows:

(1) Prepare the substrate: Use the standard RCA (Radio Corporation of American) cleaning process to clean the single crystal n-Si substrate with a resistivity of 2-5 Ω cm, and put it into the magnetron sputtering equipment as the substrate for depositing the film Material;

(2) Magnetron sputtering film formation: put LaHfO _x ceramic target and Ti metal target with a purity greater than 99.9% in the magnetron sputtering equipment, and pump the magnetron sputtering equipment to a high vacuum of 2×10 ^-4 pa , according to the flow ratio of O ₂ and Ar 5:20 into the mixed gas, the gas pressure is 2.5Pa, the sputtering power of LaHfO _x (La/Hf molar ratio is 1:1) and Ti is 60W and 10W respectively, the LaHfO _x ceramic target and Ti metal target were pre-sputtered for 15 minutes, and LaHfO _x ceramic target and Ti metal target were magnetron co-sputtered, and an amorphous HfLaTiO film with a thickness of 4 nm was deposited on a single crystal Si substrate; The atomic ratio of Ti/(Hf+La) was 2%.

(3) Fabrication of MOS structure: pump the magnetron sputtering equipment to a high vacuum of 10 ^-4 Pa, pass in argon gas, the pressure is 1Pa, the sputtering power of W is 60W, and the metal mask template with a diameter of 100μm is passed through the above A 150nm-thick W is deposited on the amorphous film as a metal gate electrode, thereby obtaining a MOS structure.

(4) Measurement of the electrical properties of the MOS structure: On the back of the substrate single crystal Si substrate, a metal Ag with a thickness of 100nm was deposited by radio frequency magnetron sputtering deposition technology as the back electrode of the MOS structure. Keithley4200 semiconductor tester is used for electrical performance measurement. During the test, the gate is connected to the gate terminal and the back electrode is grounded. The test adopts the voltage sweep mode, and the gate voltage ranges from -3V to +3V with a step of 0.1V. The frequency is set to 1MHz when measuring capacitance characteristics. Figure 1 is the capacitance-voltage characteristic curve of the MOS structure, and Figure 2 is the leakage current-voltage characteristic curve of the MOS structure. It can be seen from the figure that the leakage current density of the MOS structure is less than or equal to 10 ^-6 A/cm ² when the gate voltage is 1V.

Example 2

A method for preparing a MOS structure with a higher dielectric constant, the specific steps are as follows:

(1) Prepare the substrate: adopt the standard RCA cleaning process (the process flow is the same as in Example 1) to clean the single crystal n-Si substrate with a resistivity of 2 to 5 Ω cm, put it into the atomic layer deposition equipment (ALD equipment), and use it as Substrate material for depositing thin films;

(2) Film formation by atomic layer deposition: Hf source (TEMAH-Hf(NC ₂ H ₅ CH ₃ ) ₄ ), Ti source (TiCl ₄ ) and La source (La(thd) ₃ ) are introduced into the reaction chamber, The oxidant is _H2O , which is deposited layer by layer to form one or more deposition cycle layers. Each cycle layer includes 6 cycles of Hf, 4 cycles of La and 1 cycle of Ti, forming a 6nm layer on the semiconductor substrate. Thick amorphous HfLaTiO films. Among them, the atomic ratio of Ti/(Hf+La) is 9%.

(3) Fabrication of MOS structure: A Ti source (TiCl ₄ ) was introduced into the reaction chamber of another ALD equipment, and NH ₃ was used as the N source to deposit and form a TiN gate electrode on the HfLaTiO film.

(4) Measurement of the electrical properties of the MOS structure: On the back of the substrate single crystal Si substrate, use radio frequency magnetron sputtering deposition technology to deposit metal Al with a thickness of 100nm, in the mixed atmosphere of N ₂ +H ₂ at 400°C Carry out alloying treatment for 20min, as the back electrode of MOS structure. Keithley4200 semiconductor tester is used for electrical performance measurement. During the test, the gate is connected to the gate terminal and the back electrode is grounded. The test adopts the voltage sweep mode, and the gate voltage ranges from -3V to +3V with a step of 0.1V. The frequency is set to 1MHz when measuring capacitance characteristics. FIG. 3 is a capacitance-voltage characteristic curve of the MOS structure, and FIG. 4 is a leakage current-voltage characteristic curve of the MOS structure.

Example 3

A method for preparing a MOS structure with a higher dielectric constant, the specific steps are as follows:

(1) Prepare the substrate: Use the standard RCA (Radio Corporation of American) cleaning process to clean the single crystal n-Si substrate with a resistivity of 2-5 Ω cm, and put it into the magnetron sputtering equipment as the substrate for depositing the film Material;

(2) Magnetron sputtering film formation: put LaHfO _x ceramic target and Ta metal target with a purity greater than 99.9% in the magnetron sputtering equipment, and pump the magnetron sputtering equipment to a high vacuum of 2×10 ^-4 Pa , according to the flow ratio of O ₂ and Ar is 5:20 into the mixed gas, the gas pressure is 2.5Pa, the sputtering power of LaHfO _x (La/Hf molar ratio is 1:1) and Ta is 60W and 15W respectively, the LaHfO _x ceramic target and Ta metal target were pre-sputtered for 15 minutes, and LaHfO _x ceramic target and Ta metal target were magnetron co-sputtered, and an amorphous HfLaTaO film with a thickness of 4 nm was deposited on a single crystal Si substrate; The atomic ratio of Ta/(Hf+La) was 3%.

(3) Fabrication of MOS structure: pump the magnetron sputtering equipment to a high vacuum of 10 ^-4 Pa, pass in argon gas, the pressure is 1Pa, the sputtering power of W is 60W, and the metal mask template with a diameter of 100μm is passed through the above A 150nm-thick W is deposited on the amorphous film as a metal gate electrode, thereby obtaining a MOS structure.

(4) Measurement of the electrical properties of the MOS structure: On the back of the substrate single crystal Si substrate, a metal Ag with a thickness of 100nm was deposited by radio frequency magnetron sputtering deposition technology as the back electrode of the MOS structure. Keithley4200 semiconductor tester is used for electrical performance measurement. During the test, the gate is connected to the gate terminal, and the back electrode is grounded. The test adopts voltage sweep mode, and the gate voltage ranges from -3V to +3V, with a step of 0.1V. The frequency is set to 1MHz when measuring capacitance characteristics. FIG. 5 is a capacitance-voltage characteristic curve of the MOS structure, and FIG. 6 is a leakage current-voltage characteristic curve of the MOS structure.

Claims (8)

1. A MOS structure with a higher dielectric constant is characterized in that it comprises a semiconductor substrate, a gate dielectric film deposited on the semiconductor, and a metal gate electrode deposited by physical vapor deposition, wherein the gate dielectric film is Hafnium-based multiple oxides HfLaTiO _x or HfLaTaO _x . 2. The MOS structure with higher dielectric constant according to claim 1, characterized in that the mass ratio of TiO ₂ or Ta ₂ O ₅ doped in the hafnium-based multi-component oxide is 2%-10%. 3. The MOS structure with a higher dielectric constant according to claim 1 or 2, wherein the gate dielectric film is amorphous. 4. The MOS structure with higher dielectric constant according to claim 1 or 2, characterized in that the semiconductor substrate is Si, InP, Ge, GaAs, InGaAs or SOI. 5. The MOS structure with a higher dielectric constant according to claim 1 or 2, wherein the metal gate electrode is Pt, W, TiN, TaN or a combination thereof. 6. The MOS structure with a higher dielectric constant according to claim 1 or 2, characterized in that the gate dielectric thin film is deposited by physical vapor deposition, chemical vapor deposition or atomic layer deposition. 7. The MOS structure with a higher dielectric constant according to claim 1 or 2, wherein the dielectric constant of the gate dielectric film is 30-56, when the physical thickness of the gate dielectric film is 6nm When the gate voltage is -1 volt, the leakage current density of the MOS structure is less than or equal to 10 ^-6 A/cm ² . 8. A method for preparing a MOS structure with a higher dielectric constant as claimed in claim 1, characterized in that, comprising the steps of: (1) Clean the semiconductor substrate to remove organic pollutants, dust, metal ions and oxide layers on the surface; (2) Depositing a gate dielectric thin film on the semiconductor substrate by physical vapor deposition, chemical vapor deposition or atomic layer deposition; (3) A metal gate electrode is deposited on the gate dielectric film by a physical vapor deposition method to obtain a MOS structure.