CN104752353B - The forming method of sram cell - Google Patents
The forming method of sram cell Download PDFInfo
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- CN104752353B CN104752353B CN201310745628.XA CN201310745628A CN104752353B CN 104752353 B CN104752353 B CN 104752353B CN 201310745628 A CN201310745628 A CN 201310745628A CN 104752353 B CN104752353 B CN 104752353B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
A kind of forming method of sram cell, including：It is formed with：First, second, third and fourthth, five, six fin；Across the first grid of first, second and third fin, first and second fin between the second grid of first and second fin, first and second grid is the first drain electrode；Across the 3rd grid of fourth, fifth, six fins, the five, the six fins between the 4th grid of the five, the six fins, third and fourth grid are the second drain electrode；5th source electrode of the fin of first grid both sides the 3rd, the 3rd drain electrode；6th source electrode of the fin of the 3rd grid both sides the 4th, the 4th drain electrode；Form interlayer dielectric layer；First graphical formation first groove, first and second fin, the 3rd fin of the 3rd drain electrode across the first drain electrode；Second graphical formation second groove, the five, the six fins, the 4th fin of the 4th drain electrode across the second drain electrode；In first groove formation the first metal layer, second groove formation second metal layer.Sram cell is achieved in technique.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming an SRAM unit.
Background
A Static Random Access Memory (SRAM) is one of the memories, has the advantages of high speed, low power consumption, compatibility with standard processes, and the like, and is widely applied to the fields of PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players), and the like.
A static random access memory includes a plurality of static random access memory cells (SRAM cells) arranged in an array, and an SRAM cell includes six transistors (6-T). As the integration level of integrated circuits increases, the feature size of SRAM cells gradually decreases and the occupied wafer area also becomes smaller and smaller. Compared with the size of a planar MOS transistor, the size of the fin field effect transistor is smaller, and the fin field effect transistor is more suitable for the requirement of higher integration level of a future integrated circuit.
In the prior art, referring to fig. 1, a 6T structure SRAM cell including six finfets includes:
the first fin portion 11, the second fin portion 12, the third fin portion 13, the fourth fin portion 14, the fifth fin portion 15 and the sixth fin portion 16 are arranged in parallel;
a first gate 21 crossing the first fin 11, the second fin 12, and the third fin 13, and a second gate 22 crossing the first fin 11 and the second fin 12, a first fin portion and a second fin portion between the first gate 21 and the second gate 22 collectively serving as a first drain 31, a first fin portion and a second fin portion on the other side of the first gate 21 from the first drain 31 serving as a first source 41, a first fin portion and a second fin portion on the other side of the second gate 22 from the first drain 31 serving as a second source 42, a first pull-down transistor PD1, and a first drain 31 collectively constituting a first transfer transistor PG1 by crossing the first gate portion, the first source 41, and the first drain 31 of the first fin portion and the second fin;
a third gate 23 crossing the fourth fin 14, the fifth fin 15, and the sixth fin 16, and a fourth gate 24 crossing the fifth fin 15 and the sixth fin 16, where the third gate 23 and the second gate 22 are opposite in the width direction of the first fin 11, a fifth fin portion and a sixth fin portion between the third gate 23 and the fourth gate 24 collectively serve as a second drain 32, a fifth fin portion and a sixth fin portion on the other side of the third gate 23 opposite to the second drain 32 serve as a third source 43, a fifth fin portion and a sixth fin portion on the other side of the fourth gate 24 opposite to the second drain 32 serve as a fourth source 44, and a third gate portion crossing the fifth fin portion and the sixth fin, the third source electrode 43 and the second drain electrode 32 together constitute a second pull-down transistor PD2, and the fourth gate electrode 24, the fourth source electrode 44, and the second drain electrode 32 together constitute a second transfer transistor PG 2;
a fifth source 45 and a third drain 33 located on the third fin portion on both sides of the first gate 21, wherein the fifth source 45 and the first source 41 are located on the same side of the first gate 21, and the fifth source 45, the third drain 33 and the first gate portion crossing the third fin together form a first pull-up transistor PU 1;
and a sixth source 46 and a fourth drain 34 located on the fourth fin portion on both sides of the third gate 23, wherein the sixth source 46 and the third source 43 are located on the same side of the third gate 23, and the sixth source 46, the fourth drain 34 and the third gate portion crossing over the fourth fin together form a second pull-up transistor PU 2.
After six FinFETs are formed on the substrate, an interlayer dielectric layer is formed on the substrate, a first metal layer 51 is formed in the interlayer dielectric layer, and the first metal layer 51 crosses over the first fin portion, the second fin portion and the third fin portion of the first drain electrode 31 at the partial height; and forming a second metal layer 52, wherein the second metal layer 52 spans the height of the second drain electrode 32, the fifth fin portion, the sixth fin portion and the fourth fin portion where the fourth drain electrode 34 is located. The first metal layer 51 and the second metal layer 52 are opposite to each other in the width direction of the first fin 11. The first metal layer 51 electrically connects the first drain electrode 31 and the third drain electrode 33 to serve as a first storage node; the second metal layer 52 electrically connects the second drain electrode 32 and the fourth drain electrode 34 to serve as a second storage node, and the first storage node and the second storage node are complementary pairs (complementary pairs). Thus, the first pull-down transistor PD1 and the first pull-up transistor PU1 together form a first inverter, and the second pull-down transistor PD2 and the second pull-up transistor PU2 together form a second inverter. Then, a first interconnection metal layer (not shown) in contact with and connected to the first metal layer 51 and the third gate 23, and a second interconnection metal layer (not shown) in contact with and connected to the second metal layer 52 and the first gate 21 are formed on the interlayer dielectric layer. Thus, the first inverter and the second inverter are cross-coupled to form a latch circuit for latching the data logic value, wherein cross-coupling means that the input terminal of the first inverter is electrically connected to the output terminal of the second inverter and the output terminal of the first inverter is electrically connected to the input terminal of the second inverter.
However, referring to fig. 1, the opposite ends of the first metal layer 51 and the second metal layer 52 do not completely cross the third fin 13, but only cover the sidewall of the third fin 13 on the side opposite to the second fin 12. Similarly, the opposite end of the second metal layer 52 and the first metal layer 51 covers only the sidewall of the fourth fin 14 opposite to the fifth fin 15. Thus, the contact area between the first metal layer 51 and the third drain electrode 33 is small, the carrier mobility through the first metal layer 51 and the third drain electrode 33 is low, and the current is small. Similarly, the contact area between the second metal layer 52 and the fourth drain electrode 34 is also small, the carrier mobility through the second metal layer 52 and the fourth drain electrode 34 is also low, and the current is small. This reduces the signal transfer speed of the SRAM cell, resulting in poor SRAM cell performance.
Disclosure of Invention
The invention solves the problems that the signal transmission speed of the prior SRAM unit comprising six fin field effect transistors is lower and the performance is not good.
In order to solve the above problems, the present invention provides a method for forming an SRAM cell, including:
providing a substrate having formed thereon: the first fin portion, the second fin portion, the third fin portion, the fourth fin portion, the fifth fin portion and the sixth fin portion are arranged in parallel;
the first grid electrode crosses the first fin part, the second fin part and the third fin part, and the second grid electrode crosses the first fin part and the second fin part, the first fin part and the second fin part between the first grid electrode and the second grid electrode are jointly used as a first drain electrode, the first fin part and the second fin part on the other side of the first grid electrode relative to the first drain electrode are used as a first source electrode, the first fin part and the second fin part on the other side of the second grid electrode relative to the first drain electrode are used as a second source electrode, the first grid electrode portion, the first source electrode and the first drain electrode which cross the first fin part and the second fin part jointly form a first pull-down transistor, and the second grid electrode, the second source electrode and the first drain electrode jointly form a first transmission transistor;
a third gate crossing the fourth, fifth, and sixth fins, and a fourth gate crossing the fifth and sixth fins, the third grid electrode and the second grid electrode are opposite in the width direction of the first fin part, the fourth grid electrode and the first grid electrode are opposite in the width direction of the first fin part, a fifth fin part and a sixth fin part between the third grid and the fourth grid are jointly used as a second drain, a fifth fin part and a sixth fin part on the other side of the third grid electrode relative to the second drain electrode are used as a third source electrode, a fifth fin part and a sixth fin part on the other side, opposite to the second drain, of the fourth gate are used as fourth sources, a second pull-down transistor is formed by crossing the fifth fin part, the third gate part of the sixth fin, the third source and the second drain, and the fourth gate, the fourth source and the second drain form a second transmission transistor;
the fifth source electrode and the first source electrode are positioned on the same side of the first grid electrode, and the fifth source electrode, the third drain electrode and the first grid electrode part crossing the third fin part jointly form a first pull-up transistor;
the sixth source electrode and the fourth drain electrode are positioned on the parts, on two sides of the third grid electrode, of the fourth fin parts, the sixth source electrode and the third source electrode are positioned on the same side of the third grid electrode, and the sixth source electrode, the fourth drain electrode and the third grid electrode part crossing the fourth fin parts jointly form a second pull-up transistor;
forming an interlayer dielectric layer on the substrate, wherein the upper surface of the interlayer dielectric layer is flush with the upper surfaces of the first grid, the second grid, the third grid and the fourth grid;
performing first imaging on the interlayer dielectric layer, and forming a first groove in the interlayer dielectric layer, wherein the first groove crosses over a first fin part, a second fin part and a third fin part at the height of the first drain electrode;
performing second imaging on the interlayer dielectric layer, and forming a second groove in the interlayer dielectric layer, wherein the second groove crosses a fifth fin part, a sixth fin part and a fourth fin part at the height of the second drain electrode;
a first metal layer is formed in the first trench and a second metal layer is formed in the second trench.
Optionally, before the first metal layer and the second metal layer are formed, performing third patterning on the interlayer dielectric layer, and forming a third trench in the interlayer dielectric layer, where the third trench crosses over the first fin portion and the second fin portion at the height of the portion where the first source is located;
performing fourth patterning on the interlayer dielectric layer, and forming a fourth groove in the first dielectric, wherein the fourth groove crosses over the third fin part at the height of the part where the fifth source electrode is located;
forming a third metal layer in the third trench and a fourth metal layer in the fourth trench.
Optionally, before forming the first metal layer and the second metal layer, fifth patterning is performed on the interlayer dielectric layer, and a fifth trench is formed in the interlayer dielectric layer and spans a fifth fin portion and a sixth fin portion of the height of the third source;
performing sixth imaging on the interlayer dielectric layer, and forming a sixth groove in the first dielectric, wherein the sixth groove crosses over the fourth fin part at the height of the sixth source electrode;
and forming a fifth metal layer in the fifth groove and forming a sixth metal layer in the sixth groove.
Optionally, in the first patterning process, a third trench is further formed in the interlayer dielectric layer, and in the second patterning process, a fourth trench is further formed in the interlayer dielectric layer; or,
in the second patterning process, a third groove is further formed in the interlayer dielectric layer, and in the first patterning process, a fourth groove is further formed in the interlayer dielectric layer;
the third groove crosses over the first fin portion and the second fin portion at the height of the portion where the first source electrode is located, and the fourth groove crosses over the third fin portion at the height of the portion where the fifth source electrode is located;
forming a third metal layer in the third trench and a fourth metal layer in the fourth trench.
Optionally, in the first patterning process, a fifth trench is further formed in the interlayer dielectric layer, and in the second patterning process, a sixth trench is further formed in the interlayer dielectric layer; or,
in the second patterning process, a fifth groove is further formed in the interlayer dielectric layer, and in the first patterning process, a sixth groove is further formed in the interlayer dielectric layer;
the fifth groove crosses over a fifth fin portion and a sixth fin portion of the height of the portion where the third source electrode is located, and the sixth groove crosses over a fourth fin portion of the height of the portion where the sixth source electrode is located;
and forming a fifth metal layer in the fifth groove and forming a sixth metal layer in the sixth groove.
Optionally, the method further comprises: forming a first interconnection metal layer on the interlayer dielectric layer, wherein the first interconnection metal layer covers one end of the third grid electrode facing the second grid electrode and one end of the first metal layer facing the second metal layer; and
forming a second interconnection metal layer, wherein the second interconnection metal layer covers one end of the first grid electrode facing the fourth grid electrode and one end of the second metal layer facing the first metal layer; and
forming a third interconnection metal layer, wherein the third interconnection metal layer covers one end of the second grid electrode, which faces away from the third grid electrode; and
and forming a fourth interconnection metal layer, wherein the fourth interconnection metal layer covers one end of the fourth grid electrode, which faces away from the first grid electrode.
Optionally, the method for performing the first patterning on the interlayer dielectric layer includes:
forming a first photoresist layer on the interlayer dielectric layer;
patterning the first photoresist layer, wherein the patterned first photoresist layer defines the position of the first groove;
etching the interlayer dielectric layer with partial thickness by taking the patterned first photoresist layer as a mask until the first fin part, the second fin part and the third fin part with partial height are exposed to form a first groove;
and removing the patterned first photoresist layer.
Optionally, the method for performing the second patterning on the interlayer dielectric layer includes:
forming a second photoresist layer on the interlayer dielectric layer;
patterning the second photoresist layer, wherein the patterned second photoresist layer defines the position of a second groove;
etching the interlayer dielectric layer with partial thickness to form a second groove by taking the patterned second photoresist layer as a mask;
and removing the patterned second photoresist layer.
Optionally, the first pull-up transistor and the second pull-up transistor are P-type fin field effect transistors;
the first pull-down transistor and the second pull-down transistor are N-type fin field effect transistors.
Compared with the prior art, the technical scheme of the invention has the following advantages:
and forming a first groove in the first dielectric layer through first patterning, forming a second groove through second patterning, and then forming a first metal layer and a second metal layer in the first groove and the second groove respectively. Compared with the prior art that the first groove and the second groove are formed in the same patterning process, the first groove and the second groove are formed through twice patterning respectively, and the first groove and the second groove are prevented from being communicated. Therefore, the length of the first groove in the width direction of the first fin portion and the length of the second groove in the width direction of the first fin portion can be set to be larger, so that one end, opposite to the first groove and the second groove, of the first groove can completely cross over the third fin portion, namely both side walls and the upper surface of the third fin portion are completely exposed, one end, opposite to the second groove and the first groove, of the second groove can completely cross over the fourth fin portion, namely both side walls and the upper surface of the fourth fin portion are completely exposed, and therefore the distance between the first groove and the second groove is obviously reduced. Thus, the contact area between the first metal layer and the third drain electrode is larger, and the current passing through the first metal layer and the third drain electrode is larger; the contact area between the second metal layer and the fourth drain electrode is larger, and the current passing through the second metal layer and the fourth drain electrode is larger, so that the signal transmission speed of the SRAM unit is improved, and the performance of the SRAM unit is better. Moreover, under the condition that the size of the SRAM unit is reduced, the SRAM unit can be technically realized by using the technical scheme, and the strong signal transmission capability of the SRAM unit is ensured and can be technically realized.
Furthermore, the third trench and the fourth trench are also formed by patterning twice, and the third trench and the fourth trench are not communicated by patterning twice. Therefore, compared with the prior art, in the patterning process of forming the third groove, the length of the third groove in the width direction of the first fin portion can be set to be larger, the third groove can fully span the first fin portion and the second fin portion, namely two side walls and an upper surface of the first fin portion and two side walls and an upper surface of the second fin portion are fully exposed, and the distance between the third groove and the fourth groove is small.
Furthermore, the fifth trench and the sixth trench are also formed by patterning twice, and the fifth trench and the sixth trench are not communicated by patterning twice. Therefore, in the patterning process of forming the fifth groove, the length of the fifth groove in the width direction of the first fin portion can be set to be larger, the fifth groove can fully cross over the fifth fin portion and the sixth fin portion, namely two side walls and the upper surface of the fifth fin portion and two side walls and the upper surface of the sixth fin portion are fully exposed, and the distance between the fifth groove and the sixth groove is small.
Drawings
FIG. 1 is a top view of a prior art SRAM cell;
FIGS. 2-9 are schematic diagrams of SRAM cells in the process of forming an embodiment of the present invention.
Detailed Description
Aiming at the problems in the prior art, the analysis shows that: referring to fig. 1, the first metal layer 51 and the second metal layer 52 are formed in the same patterning step. Specifically, the method of forming the first metal layer 51 and the second metal layer 52 includes: firstly, forming a photoresist layer on an interlayer dielectric layer;
exposing the photoresist layer, wherein in the exposure process, the bright area of the mask corresponds to the positions of the first metal layer and the second metal layer, and the photoresist layer corresponding to the bright area is exposed; developing to remove the exposed photoresist layer;
and then, etching the interlayer dielectric layer with partial thickness by taking the patterned photoresist layer as a mask to form a first groove and a second groove, and then removing the patterned photoresist layer. Thereafter, a first metal layer is formed in the first trench and a second metal layer is formed in the second trench using a deposition, chemical mechanical polishing process.
In the above exposure process, if the distance between the two bright areas of the mask is small, for example, smaller than the resolution, the exposure light may be diffracted in the photoresist layer between the two bright areas, so that the portion of the photoresist layer between the two bright areas that should not be exposed is partially exposed and removed after development. Therefore, when the first medium with partial thickness is etched, the interlayer medium layer part between the first groove and the second groove is also etched, the first groove is communicated with the second groove, the first metal layer is contacted with the second metal layer, and the SRAM unit cannot work.
Therefore, in order to avoid the above problems, the prior art defines the space between the first metal layer and the second metal layer to be large, for example, larger than the resolution, so as to avoid the exposure light from being diffracted in the photoresist layer between the two bright areas, and finally prevent the first metal layer and the second metal layer from being contacted.
However, the distance between the first metal layer 51 and the second metal layer 52 is very large, so that the first metal layer 51 only covers the sidewall of the third fin 13 on the side opposite to the second fin 12, and the second metal layer 52 only covers the sidewall of the fourth fin 14 on the side opposite to the fifth fin 15, resulting in a small current passing through the first metal layer 51 and the third drain 33.
In order to solve the problems in the prior art, the technical scheme of the invention provides a novel method for forming an SRAM unit.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, a substrate 100 is provided, and six finfets of an SRAM cell are formed on the substrate 100.
Specifically, the six finfets include:
a first fin portion 101, a second fin portion 102, a third fin portion 103, a fourth fin portion 104, a fifth fin portion 104 and a sixth fin portion 106 arranged in parallel on the substrate 100;
a first gate 111 crossing the first fin 101, the second fin 102, and the third fin 103, and a second gate 112 crossing the first fin 101 and the second fin 102, where a first fin portion and a second fin portion between the first gate 111 and the second gate 112 collectively serve as a first drain 121, a first fin portion and a second fin portion on the other side of the first gate 111 opposite to the first drain 121 serve as a first source 131, a first fin portion and a second fin portion on the other side of the second gate 112 opposite to the first drain 121 serve as a second source 132, a first pull-down transistor PD1 is collectively formed by the first gate portion, the first source 131, and the first drain 121 crossing the first fin 101 and the second fin 102, and a first transfer transistor PG1 is collectively formed by the second gate 112, the second source 132, and the first drain 121;
a third gate 113 crossing the fourth fin 104, the fifth fin 105, and the sixth fin 106, and a fourth gate 114 crossing the fifth fin 105 and the sixth fin 106, where the third gate 113 and the second gate 112 are opposite in the width direction of the first fin 101, the fourth gate 114 and the first gate 111 are opposite in the width direction of the first fin 101, a fifth fin portion and a sixth fin portion between the third gate 113 and the fourth gate 114 are commonly used as the second drain electrode 122, a fifth fin portion and a sixth fin portion on the other side of the third gate 113 opposite to the second drain electrode 122 are commonly used as the third source electrode 133, a fifth fin portion and a sixth fin portion on the other side of the fourth gate 114 opposite to the second drain electrode 122 are commonly used as the fourth source electrode 134, and the third gate portion, the third source electrode 133, and the second drain electrode 122 crossing the fifth fin 105 and the sixth fin 106 form the second pull-down transistor PD2, the fourth gate 114, the fourth source 134, and the second drain 122 collectively constitute a second pass transistor PG 2;
a fifth source 135 and a third drain 123 located at the third fin portion on both sides of the first gate 111, the fifth source 135 and the first source 131 being located at the same side of the first gate 111, the fifth source 135, the third drain 123 and the first gate portion crossing over the third fin 103 together forming a first pull-up transistor PU 1;
the sixth source 136 and the fourth drain 124 are located on the fourth fin portion on both sides of the third gate 113, the sixth source 136 and the third source 133 are located on the same side of the third gate 113, and the sixth source 136, the fourth drain 124 and the third gate portion crossing over the fourth fin 104 together form a second pull-up transistor PU 2.
In a specific embodiment, the first fin 101, the second fin 102, the third fin 103, the fourth fin 104, the fifth fin 105 and the sixth fin 106 are formed in the same step, for example, by a self-aligned double patterning method.
Referring to fig. 2, a distance between the first fin 101 and the second fin 102 is smaller than a distance between the second fin 102 and the third fin 103, and a distance between the fifth fin 105 and the sixth fin 106 is smaller than a distance between the fourth fin 104 and the fifth fin 105. For this reason, taking the distance relationship among the first fin 101, the second fin 102 and the third fin 103 as an example, in one aspect, the first fin 101 and the second fin 102 are operated together in the first pull-down transistor PD1 and the first pass transistor PG1, while the first pull-up transistor PU1 and the first pull-down transistor PD1 are transistors of different types, and the active region where the first pull-up transistor PU1 is located and the active region where the first pull-down transistor PD1 is located should be kept insulated and isolated, so the distance between the second fin 102 and the third fin 103 is larger. On the other hand, if the distance between the second fin 102 and the third fin 103 is small, contact connection may occur during formation of a subsequent interconnect layer electrically connecting the first source 131 and the fifth source 135, respectively, causing short circuit and signal crosstalk between the active region of the first pull-up transistor PU1 and the first pull-down transistor PD 1.
In a specific embodiment, the first gate 111 and the third gate 113 are on the same straight line, the second gate 112 and the fourth gate 114 are on the same straight line, and the first gate 111, the second gate 112, the third gate 113 and the fourth gate 114 are formed in the same step. Specifically, first, the same bar-shaped member where the first gate 111 and the third gate 113 are located, and the same bar-shaped member where the second gate 112 and the fourth gate 114 are located are formed on the substrate, and then, the two bar-shaped members are etched to form the first gate 111, the second gate 112, the third gate 113 and the fourth gate 114 which are relatively independent.
In the embodiment, the first pass transistor PG1 and the first pull-down transistor PD1 share the first drain 121, and both are the same type of transistors, and are N-type finfet transistors; the second pass transistor PG2 and the second pull-down transistor PD2 share the second drain 122, and are both N-type finfets. This is mainly because carriers in the channel region of the N-type fin field effect transistor are mainly electrons, and compared with hole carriers in the channel region of the P-type fin field effect transistor, mobility of electrons is greater than mobility of holes, and thus driving current of the N-type fin field effect transistor is greater than driving current of the P-type fin field effect transistor. Therefore, the first pass transistor PG1 and the second pass transistor PG2 are both N-type finfet transistors, which greatly increases the rate of reading and writing data logic values through the first bit line and the second bit line, and increases the storage rate of the SRAM. In addition, the first pull-up transistor PU1 and the first pull-down transistor PD1 are different types of transistors, the first pull-up transistor PU1 is a P-type finfet transistor, both share the first gate 111, the subsequent first drain 121 and the third drain 123 are electrically connected, and the first pull-up transistor PU1 and the first pull-down transistor PD1 constitute a first inverter.
Accordingly, the second pull-up transistor PU2 is a P-type finfet sharing the third gate 113, the subsequent second drain 122 and fourth drain 124 are electrically connected, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter.
In the embodiment, the first pass transistor PG1 and the first pull-down transistor PD1 share the first fin 101 and the second fin 102; the fifth fin 105 and the sixth fin 106 are shared by the second pass transistor PG2 and the second pull-down transistor PD 2. While the first pull-up transistor PU1 includes a third fin 103 and the second pull-up transistor PU2 includes a fourth fin 104. That is, the active area of the first pass transistor PG1 and the first pull-down transistor PD1, and the active area of the second pass transistor PG2 and the second pull-down transistor PD2 are larger than the active area of the first pull-up transistor PU1 and the active area of the second pull-up transistor PU2, because the carriers in the channel region of the N-type finfet are electrons, more active area is occupied, and the signal transmission rate in the first pass transistor PG1 and the second pass transistor PG2 is also greatly increased.
Referring to fig. 3 and 4, fig. 4 is a schematic cross-sectional view along the AA direction of fig. 3, an interlayer dielectric layer 140 is formed on the substrate 100, and an upper surface of the interlayer dielectric layer 140 is substantially flush with upper surfaces of the first gate 111, the second gate 112, the third gate 113 and the fourth gate 114;
the interlayer dielectric layer 140 is subjected to first patterning, a first groove 151 is formed in the interlayer dielectric layer 140, the first groove 151 crosses over a first fin portion and a second fin portion of the height of the portion where the first drain 121 is located, and a third fin portion of the height of the portion where the third drain 123 is located, in contrast, the first gate 111 crosses over the first fin 101, the second fin 102 and the third fin 103 of the total height, and the second gate 112 crosses over the first fin 101 and the second fin 102 of the total height.
It is noted that, in fig. 3, the first fin 101, the second fin 102, the third fin 103, the fourth fin 104, the fifth fin 105, and the sixth fin 106 are covered by the interlayer dielectric layer 140 and are not visible, and are indicated by dashed lines.
In a specific embodiment, the method for forming the interlayer dielectric layer comprises the following steps:
forming a dielectric material layer on the substrate, wherein the dielectric material layer covers the substrate and the six fin field effect transistors and is higher than the first grid electrode, the second grid electrode, the third grid electrode and the fourth grid electrode;
and carrying out chemical mechanical polishing on the dielectric material layer until the upper surfaces of the first grid, the second grid, the third grid and the fourth grid are stopped.
In an embodiment, the method for performing the first patterning on the interlayer dielectric layer 140 includes:
forming a first photoresist layer on the interlayer dielectric layer 140;
patterning the first photoresist layer, specifically using an exposure and development process, defining the position of the first groove by the patterned first photoresist layer, wherein in the exposure process, an exposure window is a bright area of a first mask and corresponds to the first photoresist layer at the position of the first groove, and exposure light cannot expose the first photoresist layer part around the first groove;
etching the interlayer dielectric layer 140 with a partial thickness by taking the patterned first photoresist layer as a mask until the first fin portion, the second fin portion and the third fin portion with partial height are partially exposed to form a first groove 151;
and removing the patterned first photoresist layer.
Referring to fig. 3, in the present embodiment, after the first patterning process is performed on the interlayer dielectric layer 140, a third trench 153 and a fifth trench 155 are further formed in the interlayer dielectric layer 140, the third trench 153 crosses over the first fin portion and the second fin portion at the height of the portion where the first source 131 is located, and the fifth trench 155 crosses over the fifth fin portion and the sixth fin portion at the height of the portion where the third source 133 is located.
Referring to fig. 5 and 6, fig. 6 is a schematic cross-sectional view along the BB direction of fig. 5, a second patterning is performed on the interlayer dielectric layer 140, and a second trench 152 is formed in the interlayer dielectric layer 140, where the second trench 152 crosses over the fifth fin portion, the sixth fin portion, and the fourth fin portion at the partial height of the drain electrode 122, and the fourth fin portion at the partial height of the drain electrode 124, in contrast, the third gate 113 crosses over the fourth fins 104, 105, and 106 at the full height, and the fourth gate 114 crosses over the fifth fins 105 and 106 at the full height.
In an embodiment, the second patterning of the interlayer dielectric layer 140 includes:
forming a second photoresist layer on the interlayer dielectric layer 140;
patterning the second photoresist layer, specifically using an exposure and development process, defining the position of the second groove by the patterned first photoresist layer, wherein in the exposure process, an exposure window is a bright area of a second mask and corresponds to the second photoresist layer at the position of the second groove, and exposure light cannot expose the part of the second photoresist layer around the second groove;
etching the interlayer dielectric layer 140 with a partial thickness by taking the patterned first photoresist layer as a mask until the fourth fin portion, the fifth fin portion and the sixth fin portion with partial height are partially exposed to form a second trench 152;
and removing the patterned second photoresist layer.
Referring to fig. 5, in the present embodiment, after performing the second patterning process on the interlayer dielectric layer, a fourth trench 154 and a sixth trench 156 are further formed in the interlayer dielectric layer 140, the fourth trench 154 crosses over the third fin portion at the height of the fifth source 135, and the sixth trench 156 crosses over the fourth fin portion at the height of the sixth source 136.
In other embodiments, it may also be: forming a third groove and a sixth groove in the first patterning process, and forming a fifth groove and a fourth groove in the second patterning process; or,
performing third imaging on the interlayer dielectric layer to form a third groove, performing fourth imaging on the interlayer dielectric layer to form a fourth groove, performing fifth imaging on the interlayer dielectric layer to form a fifth groove, and performing sixth imaging on the interlayer dielectric layer to form a sixth groove; or,
performing third imaging on the interlayer dielectric layer to form a third groove and a fifth groove, and performing fourth imaging on the interlayer dielectric layer to form a fourth groove and a sixth groove; or,
and carrying out third imaging on the interlayer dielectric layer to form a third groove and a sixth groove, and carrying out fourth imaging on the interlayer dielectric layer to form a fourth groove and a fifth groove.
In a specific embodiment, the order of the first patterning, the second patterning, the third patterning, the fourth patterning, the fifth patterning, and the sixth patterning is not limited.
In this embodiment, referring to fig. 5, in the second patterning process, a seventh trench 157 and an eighth trench 158 are further formed in the interlayer dielectric layer 140, wherein the seventh trench 157 crosses over the first fin portion and the second fin portion at the height of the portion where the second source 132 is located, and the eighth trench 158 crosses over the fifth fin portion and the sixth fin portion at the height of the portion where the fourth source 134 is located. In other embodiments, the seventh trench and the eighth trench may also be formed in the first patterning process.
In the present embodiment, the first trench 151 and the second trench 152 are opposite to each other in the width direction of the first fin 101, and are formed by patterning twice. In the prior art, the first trench and the second trench are formed in a patterning process, and in order to prevent communication between the first trench and the second trench, a distance between the first trench and the second trench is large, and is about 60-90 nm, so that one end of the first trench opposite to the second trench covers only one side wall of the third fin portion, and one end of the second trench opposite to the first trench covers only one side wall of the fourth fin portion. In the technical scheme, the first groove and the second groove are respectively formed by two times of imaging, in the exposure process of imaging the first groove, the exposure light cannot generate diffraction effect around the bright area of the first mask, and in the exposure process of imaging the second groove, the exposure light cannot generate diffraction effect around the bright area of the second mask, so that the first groove and the second groove cannot be communicated by two times of imaging. Therefore, the length of the first groove in the width direction of the first fin portion and the length of the second groove in the width direction of the first fin portion can be set to be larger, so that the opposite ends of the first groove and the second groove can be completely exposed out of the two side walls and the upper surface of the third fin portion, and the opposite ends of the second groove and the first groove can be completely exposed out of the two side walls and the upper surface of the fourth fin portion, and therefore the distance between the first groove and the second groove can be reduced to 26nm, and the first groove and the second groove cannot be communicated with each other. Thus, the contact area between the first metal layer and the third drain electrode is larger, and the current passing through the first metal layer and the third drain electrode is larger; the contact area between the second metal layer and the fourth drain electrode is larger, and the current passing through the second metal layer and the fourth drain electrode is larger, so that the signal transmission speed of the SRAM unit is improved, and the performance of the SRAM unit is better.
Further, referring to fig. 1, in the related art, a third metal layer 53 electrically connected to the first source 41 in contact, a fourth metal layer 54 electrically connected to the fifth source 45 in contact, a fifth metal layer 55 electrically connected to the third source 43 in contact, and a sixth metal layer 56 electrically connected to the sixth source 46 in contact are further formed. Since the third metal layer 53 and the fourth metal layer 54 are opposite to each other in the width direction of the first fin portion 11, the patterning process for forming the third metal layer 53 and the fourth metal layer 54 also has a problem of communicating contact in the patterning process for forming the first metal layer 51 and the second metal layer 52. Therefore, to avoid this problem, the distance between the third metal layer 53 and the fourth metal layer 54 is large, so that the opposite end of the third metal layer 53 and the fourth metal layer 54 only covers a sidewall and an upper surface of the first fin at a partial height of the first source 41, resulting in a small current passing through the first source 41. Similarly, the fifth metal layer 55 and the sixth metal layer 56 are opposite to each other in the width direction of the first fin 11, the distance between the fifth metal layer 55 and the sixth metal layer 56 is large, and the opposite end of the fifth metal layer 55 and the sixth metal layer 56 covers only one side wall and the upper surface of the sixth fin with a partial height, so that the current passing through the third source 43 is small. This reduces the signal transfer speed in the SRAM cell.
Compared with the prior art, referring to fig. 5, the third trench corresponding to the subsequent third metal layer and the fourth trench corresponding to the subsequent fourth metal layer are respectively formed by two times of patterning, and the third trench and the fourth trench are not communicated by the two times of patterning. Therefore, in the patterning process of forming the third groove, the length of the third groove in the width direction of the first fin portion can be set to be larger, the third groove is enough to expose two side walls and the upper surface of the first fin portion and two side walls and the upper surface of the second fin portion, and the distance between the third groove and the fourth groove is small.
Compared with the prior art, referring to fig. 5, the fifth trench corresponding to the subsequent fifth metal layer and the sixth trench corresponding to the subsequent sixth metal layer are respectively formed by two times of patterning, and the fifth trench and the sixth trench are not communicated by the two times of patterning. Therefore, in the patterning process of forming the fifth groove, the length of the fifth groove in the width direction of the first fin portion can be set to be larger, the fifth groove is enough to expose two side walls and the upper surface of the fifth fin portion and two side walls and the upper surface of the sixth fin portion, and the distance between the fifth groove and the sixth groove is small.
Referring to fig. 7 and 8, fig. 8 is a schematic cross-sectional structure along CC direction of fig. 7, where a first metal layer 161 is formed in the first trench, a second metal layer 162 is formed in the second trench, a third metal layer 163 is formed in the third trench, a fourth metal layer 164 is formed in the fourth trench, a fifth metal layer 165 is formed in the fifth trench, a sixth metal layer 166 is formed in the sixth trench, a seventh metal layer 167 is formed in the seventh trench, and an eighth metal layer 168 is formed in the eighth trench. The first metal layer 161 completely spans the first fin portion where the first drain electrode 121 is located, the second fin portion, and the third fin portion where the third drain electrode 123 is located, the second metal layer 162 completely spans the fifth fin portion where the second drain electrode 122 is located, the sixth fin portion, and the fourth fin portion where the fourth drain electrode 124 is located, a distance between the first metal layer 161 and the second metal layer 162 is small, and the first metal layer 161 and the second metal layer 162 are not in contact with each other. The first metal layer 161 serves as a first storage node, the second metal layer 162 serves as a second storage node, and the first storage node and the second storage node are complementary pairs.
In addition, the third metal layer 163 completely crosses the first fin portion and the second fin portion where the first source 131 is located, and the distance between the third metal layer 163 and the fourth metal layer 164 is small, but there is no contact between the third metal layer 163 and the fourth metal layer 164. The fifth metal layer 165 completely spans the fifth fin portion and the sixth fin portion where the third source electrode 133 is located, a distance between the fifth metal layer 165 and the sixth metal layer 166 is small, and the fifth metal layer 165 and the sixth metal layer 166 are not in contact with each other.
In the present embodiment, the first metal layer 161, the second metal layer 162, the third metal layer 163, the fourth metal layer 164, the fifth metal layer 165, the sixth metal layer 166, the seventh metal layer 167, and the eighth metal layer 168 are formed in the same step.
In a specific embodiment, the forming method of the second metal layer 162, the third metal layer 163, the fourth metal layer 164, the fifth metal layer 165, the seventh metal layer 167, and the eighth metal layer 168 includes:
forming a metal material layer on the interlayer dielectric layer 140, wherein the metal material layer covers the first gate 111, the second gate 112, the third gate 113 and the fourth gate 114 and fills the first trench, the second trench, the third trench, the fourth trench, the fifth trench, the sixth trench, the seventh trench and the eighth trench;
and performing chemical mechanical polishing to remove the metal material layer higher than the upper surface of the interlayer dielectric layer 140, wherein the metal material layer remaining in the first trench is used as a first metal layer 161, the metal material layer remaining in the second trench is used as a second metal layer 162, the metal material layer remaining in the third trench is used as a third metal layer 163, the metal material layer remaining in the fourth trench is used as a fourth metal layer 164, the metal material layer remaining in the fifth trench is used as a fifth metal layer 165, the metal material layer remaining in the sixth trench is used as a sixth metal layer 166, the metal material layer remaining in the seventh trench is used as a seventh metal layer 167, and the metal material layer remaining in the eighth trench is used as an eighth metal layer 168.
Referring to fig. 9, after forming first metal layer 161, second metal layer 162, third metal layer 163, fourth metal layer 164, fifth metal layer 165, sixth metal layer 166, seventh metal layer 167, and eighth metal layer 168, first interconnect metal layer 171 is formed on interlayer dielectric layer 140, and first interconnect metal layer 171 covers one end of third gate 113 facing second gate 112 and one end of first metal layer 161 facing second metal layer 162; and
forming a second interconnection metal layer 172, wherein the second interconnection metal layer 172 covers one end of the first gate 111 facing the fourth gate 114 and one end of the second metal layer 162 facing the first metal layer 161; and
forming a third interconnection metal layer 173, wherein the third interconnection metal layer 173 covers one end of the second gate 112 opposite to the third gate 113; and
a fourth interconnection metal layer 174 is formed, and the fourth interconnection metal layer 174 covers an end of the fourth gate 114 facing away from the first gate 111.
In a specific embodiment, the first interconnect metal layer 171, the second interconnect metal layer 172, the third interconnect metal layer 173 and the fourth interconnect metal layer 174 are formed in the same step, and the specific process is well known to those skilled in the art and will not be described herein again.
The first interconnection metal layer 171 is in contact and electrical connection with the first metal layer 161 and the third gate 113, respectively, and the second interconnection metal layer 172 is in contact and electrical connection with the second metal layer 162 and the first gate 111, respectively, so that cross coupling of the first inverter and the second inverter is realized, and a latch circuit of the SRAM cell is formed.
Then, the second gate 112 is electrically connected to the word line through the third interconnection metal layer 173 and the fourth gate 114 is electrically connected to the word line through the fourth interconnection metal layer 174; the second source 132 is electrically connected to the first bit line through the seventh metal layer 167, the fourth source 134 is electrically connected to the second bit line through the eighth metal layer 168, and the first bit line and the second bit line are complementary bit lines; the first source 131 is electrically connected to the ground through the third metal layer 163 and the third source 133 through the fifth metal layer 165; fifth source electrode 135 is electrically connected to the power supply line through fourth metal layer 164 and sixth source electrode 136 through sixth metal layer 166.
When one SRAM unit works, level reading/writing of a first storage node and a second storage node is finished through a first bit line and a second bit line, and data reading/writing is achieved.
Specifically, the method for implementing data writing of the SRAM cell through the first bit line and the second bit line includes:
the word line is connected to the system high voltage, the first pass transistor PG1 and the second pass transistor PG2 are turned on, if "1" is written, the first bit line is connected to high level, the second bit line is connected to low level, the first pass transistor PG1 is turned on and the second pass transistor PG2 is turned on, the first storage node Q is recorded as "1", the second storage node QN is recorded as "0", and data "1" is written. Conversely, when writing a "0", the first bit line goes low and the second bit line goes high. After data is written, the word line is connected to a low voltage, the first pass transistor PG1 and the second pass transistor PG2 are turned off, and the data is stored in the latch circuit.
Specifically, the reading operation of the SRAM cell data by the first bit line and the second bit line is:
before reading, the first bit line and the second bit line are both high, the word line is connected to the system high voltage, the first pass transistor PG1 and the second pass transistor PG2 are turned on,
when the data stored in the latch circuit is "1", that is, the first storage node is at a high level, the second storage node is at a low level, the first pull-up transistor PU1 and the first pass transistor PG1 are turned on, the first read current enters the first bit line from the fifth source 135, the third drain 123, the first metal layer 161, the first drain 121, and the second source 132, the high level of the first storage node is transmitted to the first bit line, and the first bit line is read to be at a high level; meanwhile, the second pass transistor PG2 and the second pull-down transistor PD2 are also turned on, a second read current enters the ground line from the fourth source 134, the second drain 122 and the third source 133, the low level of the second storage node is transferred to the second bit line, the high level of the second bit line is discharged and becomes the low level, and the reading of the second bit line is the low level, so that the reading of data "1" is completed;
when the data in the latch circuit is "0", that is, the first storage node is at a low level, the second storage node is at a high level, the first pass transistor PG1 and the first pull-down transistor PD1 are turned on, the first read current enters the ground line from the second source 132, the first drain 121, the first source 131, the low level of the first storage node is transferred to the first bit line, the high level of the first bit line is drained to become a low level, and the first bit line is read to be at a low level; meanwhile, the second pass transistor PG2 and the second pull-up transistor PU2 are turned on, a second read current enters the second bit line from the sixth source 136, the fourth drain 124, the second metal layer 162, the second drain 122, and the fourth source 134, the high level of the second storage node is transferred to the second bit line, and the read second bit line is at the high level, thereby completing the reading of data "0".
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A method for forming an SRAM cell, comprising:
providing a substrate having formed thereon: the first fin portion, the second fin portion, the third fin portion, the fourth fin portion, the fifth fin portion and the sixth fin portion are arranged in parallel;
the first grid electrode crosses the first fin part, the second fin part and the third fin part, and the second grid electrode crosses the first fin part and the second fin part, the first fin part and the second fin part between the first grid electrode and the second grid electrode are jointly used as a first drain electrode, the first fin part and the second fin part on the other side of the first grid electrode relative to the first drain electrode are used as a first source electrode, the first fin part and the second fin part on the other side of the second grid electrode relative to the first drain electrode are used as a second source electrode, the first grid electrode portion, the first source electrode and the first drain electrode which cross the first fin part and the second fin part jointly form a first pull-down transistor, and the second grid electrode, the second source electrode and the first drain electrode jointly form a first transmission transistor;
a third gate crossing the fourth, fifth, and sixth fins, and a fourth gate crossing the fifth and sixth fins, the third grid electrode and the second grid electrode are opposite in the width direction of the first fin part, the fourth grid electrode and the first grid electrode are opposite in the width direction of the first fin part, a fifth fin part and a sixth fin part between the third grid and the fourth grid are jointly used as a second drain, a fifth fin part and a sixth fin part on the other side of the third grid electrode relative to the second drain electrode are used as a third source electrode, a fifth fin part and a sixth fin part on the other side, opposite to the second drain, of the fourth gate are used as fourth sources, a second pull-down transistor is formed by crossing the fifth fin part, the third gate part of the sixth fin, the third source and the second drain, and the fourth gate, the fourth source and the second drain form a second transmission transistor;
the fifth source electrode and the first source electrode are positioned on the same side of the first grid electrode, and the fifth source electrode, the third drain electrode and the first grid electrode part crossing the third fin part jointly form a first pull-up transistor;
the sixth source electrode and the fourth drain electrode are positioned on the parts, on two sides of the third grid electrode, of the fourth fin parts, the sixth source electrode and the third source electrode are positioned on the same side of the third grid electrode, and the sixth source electrode, the fourth drain electrode and the third grid electrode part crossing the fourth fin parts jointly form a second pull-up transistor;
forming an interlayer dielectric layer on the substrate, wherein the upper surface of the interlayer dielectric layer is flush with the upper surfaces of the first grid, the second grid, the third grid and the fourth grid;
performing first imaging on the interlayer dielectric layer, and forming a first groove in the interlayer dielectric layer, wherein the first groove crosses over a first fin part, a second fin part and a third fin part at the height of the first drain electrode;
performing second imaging on the interlayer dielectric layer, and forming a second groove in the interlayer dielectric layer, wherein the second groove crosses a fifth fin part, a sixth fin part and a fourth fin part at the height of the second drain electrode;
a first metal layer is formed in the first trench and a second metal layer is formed in the second trench.
2. The method of claim 1, wherein before the first and second metal layers are formed, the interlayer dielectric layer is patterned third, and a third trench is formed in the interlayer dielectric layer, the third trench crossing the first and second fin portions at a height of the first source;
performing fourth patterning on the interlayer dielectric layer, and forming a fourth groove in the interlayer dielectric layer, wherein the fourth groove crosses over the third fin part at the height of the part where the fifth source electrode is located;
forming a third metal layer in the third trench and a fourth metal layer in the fourth trench.
3. The method of claim 1, wherein before the first and second metal layers are formed, fifth patterning is performed on the interlayer dielectric layer, and a fifth trench is formed in the interlayer dielectric layer, wherein the fifth trench crosses over a fifth fin portion and a sixth fin portion of a height of a portion where the third source is located;
performing sixth imaging on the interlayer dielectric layer, and forming a sixth groove in the interlayer dielectric layer, wherein the sixth groove crosses over the fourth fin part at the height of the sixth source electrode;
and forming a fifth metal layer in the fifth groove and forming a sixth metal layer in the sixth groove.
4. The method of forming the SRAM cell of claim 1, wherein in the first patterning process, a third trench is further formed in the interlevel dielectric layer, and in the second patterning process, a fourth trench is further formed in the interlevel dielectric layer; or,
in the second patterning process, a third groove is further formed in the interlayer dielectric layer, and in the first patterning process, a fourth groove is further formed in the interlayer dielectric layer;
the third groove crosses over the first fin portion and the second fin portion at the height of the portion where the first source electrode is located, and the fourth groove crosses over the third fin portion at the height of the portion where the fifth source electrode is located;
forming a third metal layer in the third trench and a fourth metal layer in the fourth trench.
5. The method of forming the SRAM cell of claim 1, wherein in the first patterning process, a fifth trench is further formed in the interlevel dielectric layer, and in the second patterning process, a sixth trench is further formed in the interlevel dielectric layer; or,
in the second patterning process, a fifth groove is further formed in the interlayer dielectric layer, and in the first patterning process, a sixth groove is further formed in the interlayer dielectric layer;
the fifth groove crosses over a fifth fin portion and a sixth fin portion of the height of the portion where the third source electrode is located, and the sixth groove crosses over a fourth fin portion of the height of the portion where the sixth source electrode is located;
and forming a fifth metal layer in the fifth groove and forming a sixth metal layer in the sixth groove.
6. The method of forming the SRAM cell of claim 1, further comprising: forming a first interconnection metal layer on the interlayer dielectric layer, wherein the first interconnection metal layer covers one end of the third grid electrode facing the second grid electrode and one end of the first metal layer facing the second metal layer; and
forming a second interconnection metal layer, wherein the second interconnection metal layer covers one end of the first grid electrode facing the fourth grid electrode and one end of the second metal layer facing the first metal layer; and
forming a third interconnection metal layer, wherein the third interconnection metal layer covers one end of the second grid electrode, which faces away from the third grid electrode; and
and forming a fourth interconnection metal layer, wherein the fourth interconnection metal layer covers one end of the fourth grid electrode, which faces away from the first grid electrode.
7. The method of forming the SRAM cell of claim 1, wherein the first patterning the interlevel dielectric layer comprises:
forming a first photoresist layer on the interlayer dielectric layer;
patterning the first photoresist layer, wherein the patterned first photoresist layer defines the position of the first groove;
etching the interlayer dielectric layer with partial thickness by taking the patterned first photoresist layer as a mask until the first fin part, the second fin part and the third fin part with partial height are exposed to form a first groove;
and removing the patterned first photoresist layer.
8. The method of forming the SRAM cell of claim 1, wherein the second patterning the interlevel dielectric layer comprises:
forming a second photoresist layer on the interlayer dielectric layer;
patterning the second photoresist layer, wherein the patterned second photoresist layer defines the position of a second groove;
etching the interlayer dielectric layer with partial thickness to form a second groove by taking the patterned second photoresist layer as a mask;
and removing the patterned second photoresist layer.
9. The method of claim 1, wherein the first pull-up transistor and the second pull-up transistor are P-type fin field effect transistors;
the first pull-down transistor and the second pull-down transistor are N-type fin field effect transistors.
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