CN104752056B - Thin film capacitor - Google Patents

Abstract

A film capacitor comprising: a semiconductor layer; a first dielectric layer and a second dielectric layer arranged on opposite sides of the semiconductor layer; a first metal layer on the first dielectric layer A side opposite to the semiconductor layer forms a first terminal and a second terminal, one of the first terminal and the second terminal extending through the first dielectric layer into contact with the semiconductor layer, so The first terminal and the second terminal form a capacitor with the first dielectric layer; and a second metal layer forms a third terminal on a side of the second dielectric layer opposite to the semiconductor layer. The first and second terminals may be source and drain terminals, and the third terminal may be a gate terminal. The first metal layer may be divided to form the first terminal and the second terminal. The third terminal may be shared with one of the first terminal and the second terminal.

Description

film capacitor

field of invention

The present invention generally relates to film capacitors.

Background technique

Displays may be formed from arrays of organic light emitting devices ("OLEDs") each controlled by individual circuits (i.e., pixel circuits) with transistors for selectively controlling the circuits, thereby using The display information is programmed and illuminated according to the display information. Thin film transistors ("TFTs") fabricated on substrates can be incorporated into these displays.

Mobility characterizes the reactivity of charge carriers in the presence of an electric field. Mobility is usually expressed in units of cm ² /V s. For a transistor, the mobility of the channel region provides a measure of the transistor's performance when a current is "on" (eg, the current may be supplied by the transistor). In thin film transistors, a layer of semiconductor material is typically used to form the channel region.

The development of OLED display devices has been challenged by the need for suitable driving transistors in the pixel circuits. Amorphous silicon (a-Si), which is the channel material of transistors switching AM-LCD pixels from voltage, has a low mobility (~0.1 cm ² V ⁻¹ s ⁻¹ ). Organic semiconductor channel materials are very suitable for use as pixel circuit drive transistors because of their homogeneity, low cost and various means of deposition, but the optimal mobility of the organic semiconductor channel materials is not compatible with the migration of a-Si rates are similar. In a typical TFT structure, the low-mobility channel layer requires a large source-drain voltage to drive the necessary current. This drains power within the transistor (as opposed to generating light in an OLED), to the detriment of power savings.

P-type a-Si TFTs can have even lower mobility values, and can be as low as 0.01 cm ² V ⁻¹ s ⁻¹ .

Contents of the invention

According to one embodiment, a film capacitor includes: a semiconductor layer; a first dielectric layer and a second dielectric layer arranged on opposite sides of the semiconductor layer; a first metal layer on the first dielectric layer A side of the semiconductor layer opposite to the semiconductor layer forms a first terminal and a second terminal, one of the first terminal and the second terminal extending through the first dielectric layer into contact with the semiconductor layer, The first and second terminals form a capacitor with the first dielectric layer; and a second metal layer forms a third terminal on an opposite side of the second dielectric layer from the semiconductor layer. In one embodiment, the first and second terminals are source and drain terminals and the third terminal is a gate terminal. The first metal layer may be divided to form the first terminal and the second terminal. The third terminal may be shared with one of the first terminal and the second terminal.

In another embodiment, a film capacitor includes: a semiconductor layer; a first dielectric layer and a second dielectric layer disposed on opposite sides of the semiconductor layer, at least the second dielectric layer having an opening therein a first metal layer forming a first terminal on the opposite side of the first dielectric layer from the semiconductor layer; and a second metal layer on the second dielectric layer opposite the semiconductor layer The opposite side of the layer forms a second terminal, the second metal layer extending through the opening in the second dielectric layer into contact with the semiconductor layer.

The foregoing aspects and further aspects and embodiments of the present invention will become apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is taken with reference to the accompanying drawings, A brief description of the figures is provided next.

Description of drawings

The foregoing and other advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 illustrates a block diagram of a bottom-gate thin film transistor having a channel region including a nanoconductor layer.

2 illustrates a block diagram of a top-gate thin film transistor having a channel region including a nanoconductor layer.

FIG. 3A is a schematic cross-sectional view of a thin film transistor 100 having a channel region including a nanoconductor layer.

FIG. 3B is a schematic diagram of a thin film transistor similar to that shown in FIG. 3A but with a shorter nanoconductor layer.

4A is a schematic top view of a nanoconductor layer having a characteristic length greater than the spacing between the drain and source terminals of a TFT.

Fig. 4B is a schematic top view of a nanoconductor layer similar to Fig. 4A, but in which the individual nanoconductors are not completely aligned in the direction from the drain terminal to the source terminal.

FIG. 4C is a schematic top view of a nanoconductor layer similar to FIG. 4A , but wherein the characteristic length of the nanoconductor layer is smaller than the distance between the drain terminal and the source terminal of the TFT.

5 is a flowchart illustrating an example process for fabricating a thin film transistor having a channel region including a nanoconductor layer.

6 is a schematic cross-sectional view of a thin film transistor having a channel region including a nanoconductor layer.

Figure 7 is a pair of cross-sectional views of two typical metal-insulator-metal (MIM) capacitors.

Fig. 8 is a cross-sectional view of a structure with a high capacitance value.

FIG. 9 is a plan view of the structure shown in FIG. 8 .

Fig. 10 is a cross-sectional view of a conversion structure with a high capacitance value.

While the invention is susceptible to various modifications and alternative forms, specific embodiments of the invention have been shown by way of example in the drawings and described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. In fact, the present invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

specific embodiment

FIG. 1 illustrates a block diagram of a bottom-gate thin film transistor 10 having a channel region 31 including a nanoconductor layer 20 . Thin film transistor 10 may generally be formed by deposition or similar process on substrate 12 of the display. For example, substrate 12 may be a backplane substrate or an encapsulating glass substrate, or another suitable substrate that provides a surface on which TFT 10 may be grown. Gate terminal 14 is formed on substrate 12 . The gate terminal 14 is a conductive electrode for receiving signals to operate the TFT 10 . The signal applied to the gate terminal 14 may be a binary "high" signal or a binary "low" signal that turns the TFT 10 on or off, or may be a multi-phase signal that controls the amount of current delivered through the drain and source terminals. level signal.

A dielectric layer 16 (“insulating layer”) is formed over the gate terminal 14 to prevent current from flowing to or from the gate terminal 14 and the channel region 31 of the TFT 10. Area 31 Mobility. Dielectric layer 16 may be produced by a deposition process. A layer of nanoconductors (ie, nanoconductor layer 20 ) is then placed (“positioned”) on dielectric layer 16 . Nanoconductor layer 20 typically includes a plurality of nanoconductors and may include nanowires, nanofibers, and/or nanotubes such as single-walled nanotubes (“SWNTs”), double-walled nanotubes (“DWNTs”), and/or multi-walled nanotubes (“DWNTs”). MWNT") nanotubes. Nanoconductors can be formed from carbon and/or silicon, and can optionally incorporate dopant materials to alter the conductive properties of the nanoconductors. Nanoconductor layer 20 may be a single layer (ie, a single layer) of nanoconductors.

A semiconductor layer 30 is grown over the nanoconductor layer 20 . The semiconductor layer 30 and the nanoconductor layer 20 together form a double-layer channel region 31 of the TFT 10 . For example, the semiconductor layer 30 may be made of an organic semiconductor material or an inorganic semiconductor material. For example, the semiconductor layer 30 may be formed of amorphous silicon or polycrystalline silicon. The semiconductor layer 30 may also incorporate dopants to modify the mobility characteristics of the TFT 10 .

The drain terminal 32 and source terminal 34 of the TFT are then formed on the semiconductor layer. Drain terminal 32 and source terminal 34 are each formed of a conductive material suitable for transporting electrical energy. For example, terminals 32, 34 may be metallic. The distance between the drain terminal 32 and the source terminal 34 defines the channel separation distance. This channel separation distance is a parameter that affects the operational performance of the TFT 10 .

Since the gate 14 is formed directly on the substrate 12, the TFT 10 is referred to as a bottom-gate TFT, so that the side of the TFT 10 having the gate 14 is referred to as the bottom side of the TFT 10, while the side having the drain terminal 32 and the source The side of the TFT 10 with the extreme terminals 34 is referred to as the top side of the TFT 10 .

FIG. 2 illustrates a block diagram of a top-gate thin film transistor 40 having a channel region 31 including a nanoconductor layer 20 . Top-gate TFT 40 is fabricated by applying in reverse order the layered components discussed in relation to bottom-gate TFT 10 shown in FIG. 1 . A drain terminal 32 and a source terminal 34 are each formed on the substrate 12 . A semiconductor layer 30 is then deposited on the drain terminal 32 and the source terminal 34 . Nanoconductor layer 20 is then applied to semiconductor layer 30 to form bilayer channel region 31 . By applying nanoconductor layer 20 to the surface of semiconductor layer 30 opposite drain terminal 32 and source terminal 34 , nanoconductor layer 20 is positioned without any direct contact with drain terminal 32 and source terminal 34 . Therefore, during low field effect operation (eg, low gate-source voltage), the performance of the TFT is dominated by the semiconductor layer, since the nanoconductor does not have any direct contact with the source or drain terminals of the TFT. The TFT thus provides good leakage current performance similar to that of the semiconductor layer 30 . A dielectric layer 16 is then grown on the nanoconductor side of the channel region 31 and the gate terminal 14 is formed on the dielectric layer 16 .

In addition, the nanoconductor nanoconductor layer can change the polarity of the TFT device. For example, carbon nanotubes have p-type characteristics. Accordingly, an amorphous silicon (a-Si) TFT formed with a channel region including carbon nanotubes may have p-type characteristics. The p-type a-Si TFTs thus formed can greatly benefit a-Si TFT applications due to the enhanced mobility of such p-type transistors compared to conventional p-type TFTs. The enhanced mobility of such p-type transistors compared with conventional p-type TFTs may advantageously enable such p-type a-Si TFTs to be utilized in AMOLED display applications previously dominated by n-type TFTs, allowing p type pixel circuit structure.

3A is a schematic cross-sectional view of a thin film transistor 110 (“TFT”) having a channel region 131 including a nanoconductor layer 120 . In the schematic diagram of FIG. 3A , components of TFT 110 are numbered with reference numerals that are 100 greater than the reference numerals of corresponding components of TFT 10 in the block diagram of FIG. 1 . The TFT 110 is formed on a substrate 112, which may be a substrate for a display such as a backplane substrate, a transparent planar substrate, or an encapsulating glass substrate. A gate terminal 114 is formed on the substrate 112 . The gate terminal 114 may be a conductive terminal having characteristics similar to those of the gate terminal 14 described in relation to FIG. 1 . A dielectric layer 116 is grown on the gate terminal 114 to insulate the gate terminal 114 from the channel region 131 of the TFT 110 . Dielectric layer 116 may be an electrical insulator.

The channel region 131 of the TFT has two layers: the nanoconductor layer 120 and the semiconductor layer 130 . The semiconductor layer 130 prevents the nanoconductor layer 120 from direct contact with the drain terminal 132 or the source terminal 134 . The nanoconductor layer 120 typically includes a plurality of nanowires, a plurality of nanofibers and/or a plurality of nanotubes. Individual nanoconductors (“nanoparticles”) in nanoconductor layer 120 are placed within a thin film on dielectric layer 116 . The individual nanoconductors are each desirably generally aligned in a direction from drain terminal 132 to source terminal 134 to increase the effectiveness of charge transfer between drain terminal 132 and source terminal 134 .

FIG. 3B is a schematic diagram of a thin film transistor 111 similar to that illustrated in FIG. 3A but with a shorter nanoconductor layer 121 . The schematic diagram in FIG. 3B shows that the drain terminal 132 and the source terminal 134 can overlap the nanoconductor layer 121 by different amounts. By adjusting the extent of the size of the nanoconductor layer 121 in the direction from the drain terminal 132 to the source terminal 134, the charge transfer characteristics of the bilayer channel region 131 can be altered. For example, the bilayer channel region 131 can be formed by increasing the dimension (e.g., length) of the nanoconductor layer 121, by increasing the density of nanoconductors within the nanoconductor layer 121, and/or by increasing the contact with the drain terminal 132 and/or source The overlapping amount of the extreme terminals 134 is used to provide relatively more charge transfer (eg, increased mobility). As described herein, the amount of overlap between the nanoconductor layer 121 and the drain terminal 132 and source terminal 134 refers to the drain terminal 132/source terminal 132 separated from the nanoconductor layer 121 only by a vertical path through the semiconductor layer 130. The amount of surface area of the source terminal 134 . In FIGS. 3A and 3B , the vertical direction through the semiconductor layer 130 is the direction outwardly perpendicular to the substrate 112 .

Aspects of the present invention further provide that the nanoconductor layer 121 may be configured in a direction from the drain terminal 132 to the source terminal 134 with a dimension that does not overlap with either the drain terminal 132 or the source terminal 134 . For example, the length of the nanoconductor layer 121 may be smaller than the separation distance between the drain terminal 132 and the source terminal 134 . Additional configurations of the nanoconductor layer 121 are generally illustrated by the schematic top views in FIGS. 4A-4C .

4A is a schematic top view of a nanoconductor layer having a characteristic length greater than the spacing between the drain and source terminals of a TFT. While for illustrative purposes nanoconductor layer 20 is shown as individual nanoconductors (e.g., nanoconductors 21, 22) of uniform length each aligned between drain terminal 32 and source terminal 34, the present invention It is not limited to this. Aspects of the present invention are applicable to configurations in which the nanoconductor layer 20 has individual nanoconductors that are not uniform in length and orientation. The schematic diagram of nanoconductor layer 20 in FIG. 4A also illustrates that individual nanoconductors (eg, nanoconductors 21 , 22 ) are arranged in a single layer. Nanoconductor layer 20 may be a dispersed monolayer of nanoconductors that does not completely cover the full cross-sectional area of the bilayer channel region. For example, the gaps between individual nanoconductors (e.g., nanoconductors 21, 22) may be approximately the same size as the width of the nanoconductors themselves, such that individual nanoconductors (e.g., nanoconductors 21, 22) in nanoconductor layer 20 Cumulatively covers approximately half (eg, 50%) of the bilayer channel region. In one example, any gaps between individual nanoconductors (eg, nanoconductors 21 , 22 ) are filled by a semiconductor layer deposited over nanoconductor layer 20 . The nanoconductor layer 20 may be performed with a coverage greater or less than 50% coverage, such as 30% coverage or 70% coverage. In general, increasing the density (ie, coverage) of a nanoconductor monolayer can enhance the charge transfer properties of a bilayer channel region.

In FIGS. 4A-4C , the hash blocks labeled "D" and "S" represent the locations of the drain terminal 32 and the source terminal 34, respectively. The drain terminal 32 has a channel side 33 and the source terminal 34 has a channel side 35 . For convenience, the distance between the channel side 33 of the drain terminal 32 and the channel side 35 of the source terminal 34 may be referred to as a channel separation distance. As shown in FIG. 4A , the length of the nanoconductor layer 20 may be greater than the channel separation distance between the drain terminal 32 and the source terminal 34, so that the drain terminal 32 and the source terminal 34 are each separated from the nanoconductor layer 20. at least partially overlap. By overlapping at least a portion of the nanoconductor layer 20 with the drain terminal 32/source terminal 34, the nanoconductor layer 20 advantageously allows a vertical connection path through the semiconductor layer to enhance the charge transfer characteristics of the bilayer channel region.

FIG. 4B is a schematic top view of a nanoconductor layer similar to FIG. 4A , but where the individual nanoconductors (eg, nanoconductors 21 , 23 ) are not perfectly aligned in a direction oriented from drain terminal 32 to source terminal 34 . Since the nanoconductor layer 20 is not directly connected to any of the drain terminal 32/source terminal 34 (i.e., the nanoconductor layer 20 is only connected to the drain/source terminal through the semiconducting layer), the double-layer channel The charge transfer properties of the regions are relatively insensitive to the precise alignment requirements of the individual nanoconductors (eg, nanoconductors 23). Accordingly, nanoconductors (e.g., nanoconductors 21, 23) are typically enhanced by transporting charge to or from drain terminal 32/source terminal 34 through the semiconductor layer. The effective mobility of the double-layer channel region, so that the charge transfer characteristics of the thin film transistor are not limited by the mobility of the semiconductor layer.

FIG. 4C is a schematic top view of a nanoconductor layer similar to FIG. 4A , but wherein the characteristic length of the nanoconductor layer is smaller than the distance between the drain terminal and the source terminal of the TFT. In the schematic diagram in FIG. 4C, individual nanoconductors (eg, nanoconductors 24, 25) are shown having a length that is less than the channel separation distance. In the configuration illustrated in FIG. 4C , nanoconductor layer 20 does not overlap either drain terminal 32 or source terminal 34 . Therefore, there is no charge transfer path from the drain terminal 32/source terminal 34 to the nanoconductor layer 20, which only includes a vertical charge transfer path through the semiconductor layer. For example, in the configuration shown in Figure 4C, the effective mobility of the bilayer channel region may be limited by the requirement for lateral transfer of charges across.

5 is a flowchart 50 illustrating an example process for fabricating a thin film transistor ("TFT") having a channel region that includes a nanoconductor layer. In a first step 51, a gate terminal of a TFT is formed on a substrate. Next, a dielectric layer is grown on the gate terminal 54 in step 52 . The dielectric layer covers the exposed surface of the gate terminal to prevent the subsequently deposited bilayer channel region from directly contacting the gate terminal. In step 53, a dispersed layer of nanoconductors, such as nanotubes or nanowires, is positioned on the dielectric layer. As discussed in relation to FIGS. 3A-3B , the nanoconductor dispersion layer may be a single layer that does not cover the entire exposed area of the channel region. In step 54, a semiconductor layer is deposited on the nanoconductor layer, and any exposed areas of the dielectric layer. The semiconductor layer may include amorphous silicon. Therefore, the semiconductor layer and the nanoconductor layer jointly form a double-layer channel region. Then in step 55, source and drain terminals are formed on the semiconductor layer. The source and drain terminals are formed so as not to be directly connected to the nanoconductor.

Flowchart 50 is an embodiment of a process for fabricating a bottom-gate TFT (ie, depositing a gate terminal on a substrate). However, a similar process can be used to fabricate a top-gate TFT with a double-layer channel region incorporating a nanoconductor that does not directly contact the drain or source terminal, such as the top-gate TFT shown in FIG. Gate TFT 40. For example, drain and source terminals may be formed on the substrate. A semiconductor layer can be deposited over the drain and source terminals, and a nanoconductor layer can be placed over the semiconductor layer, thereby forming a bilayer channel region. A dielectric layer can be deposited over the bilayer channel region, and a gate terminal can be formed on the dielectric layer.

Figure 6 illustrates a modified structure in which metal source and drain terminals 61 and 62 (e.g., aluminum with a thickness of about 100 nm) are formed on respective layers 63 and 64 of p+ silicon (e.g., about 35 nm in thickness) superior. Immediately below layers 63 and 64 is a layer 65 of semiconductor material (e.g., alternating nanocrystalline silicon and amorphous silicon with a total thickness of about 30 nanometers) deposited on a surface such as carbon nanotubes (e.g., , with a thickness of about 1 to 2 nanometers) on the nanoconductor layer 66. The nanoconductor is deposited over a dielectric layer 67 (eg, thermal silicon dioxide with a thickness of about 100 nanometers), which in turn is deposited on a substrate 68 (eg, p+ silicon). The bottom surface of the substrate 67 is covered with a conductive back contact 69 (eg, aluminum with a thickness of about 100 nanometers).

An exemplary process for forming the structure shown in Figure 6 is as follows:

1. Thermal P ⁺ Si Substrate Cleaning

(a) The substrate was ultrasonically cleaned in acetone for 10 minutes, followed by an additional 10 minutes in isopropanol (IPA). This process was repeated twice.

(b) The substrate was rinsed with deionized water and dried with nitrogen.

NOTE: Place the substrate on the electric furnace (~90°C) for 10 minutes before the next step.

2. Carbon nanotube coating

(a) The substrate was treated with aminopropyltriethoxysilane (APTES).

Prior to coating, the substrate was immersed in APTES solution (1% v/v in IPA solution) for 20 minutes, rinsed with IPA and dried with nitrogen.

(b) Dip-coating carbon nanotubes on the APTES-treated substrate.

Submerge the substrate in the carbon nanotube solution for 15 min. The substrate was then rinsed with plenty of deionized water and dried with nitrogen.

The carbon nanotube-coated substrate was baked on an electric furnace at 180° C. for 20 minutes, after which it was loaded onto a plasma-enhanced chemical vapor deposition (PECVD) system.

3. Deposit nanocrystalline silicon (nc-Si) and amorphous silicon _SiNx using PECVD.

(a) nc-Si (~30nm.)

Gas: SiH ₄ /H ₂ = 40/200 sccm; Pr = 900 mtorr; R _F = 2W; T = 210C (set); Rate = 4.07 nm/min.

(b) SiN _x (150nm)

Gas: SiH ₄ /NH ₃ /N ₂ = 5/100/50 sccm; Pr = 1000 mtorr; R _F = 15 W; T = 250C (set); Rate = 15 nm/min.

4. SiN _x via (mask #1)

(a) Photolithography

Photoresist: NLOF 2035

Rotation: 500 rpm for 10 seconds, followed by 4000 rpm for 90 seconds.

Soft Bake: 1 minute at 110°C.

Contact: low vacuum.

Exposure: 5.4 seconds.

Post-exposure bake: 110°C.

Development: ~30 sec AZ300MIF.

(b) Wet etching of SiN _x using buffered hydrofluoric acid (BHF).

The substrate was immersed in a BHF solution (10% v/v) for 27 seconds.

(c) Stripping of photoresist

The substrate was immersed in AZ KWIT stripper for 10 minutes and then rinsed with deionized water, acetone and IPA.

5. P ⁺ deposition (~35nm thick)

Gas: SiH ₄ /B ₂ H ₆ /H ₂ = 1.8/1.8/200 sccm; Pr = 1500 mtorr; _RF = 65W; T = 250C, (set); Rate = 7.7 nm/min.

6. S/D metal deposition (aluminum, ~100nm thick)

7. S/D Patterning (Mask #1')

Photoresist: AZ 3312

Rotation: 700 rpm for 10 seconds, followed by 4000 rpm for 60 seconds.

Soft Bake: 1 minute at 90°C.

Contact: low vacuum.

Exposure: 4 seconds.

Post-exposure bake: 120°C for 1 minute.

Development: ~15 sec AZ300MIF.

Etching: ~3 minutes in PAN etchant at room temperature.

Stripping: Rinse in AZ KWIT stripper for 4 minutes, then rinse the substrate with deionized water, acetone and IPA.

8. Use S/D metal as a hard mask to separate P ⁺ .

RIE dry etching of P+ silicon:

RF=50W; Pr=20mtorr; CF4/H2=20/3sccm; Rate=~0.43nm/s

9. Device Separation and Isolation (Mask #2)

(a) Photolithography

Photoresist: AZ 3312

Rotation: 700 rpm for 10 seconds, followed by 4000 rpm for 60 seconds.

Soft Bake: 1 minute at 90°C.

Contact: low vacuum.

Exposure: 4 seconds.

Post-exposure bake: 120°C for 1 minute.

Development: ~15 sec AZ300MIF.

(b) Dry etching of SiN _x /Si/carbon nanotubes.

_RF = 125W; Pr = 150mtorr; _CF4 / _O2 = 43/5 sccm; rate = ~4nm/s.

10. Back contact metal deposition (Al, ~100nm thick)

(a) Removal of back thermal oxide.

The front side of the wafer was protected by PR AZ3312 before it was immersed in BHF (10% v/v) for 4 minutes.

(b) Metal deposited on the backside of the wafer.

Immediately after the thermal oxide on the backside of the wafer was removed by BHF, the wafer was loaded into a vacuum chamber for metal deposition.

7-10 illustrate a film capacitor comprising: a semiconductor layer having a controllable resistance; a first dielectric layer and a second dielectric layer arranged on opposite sides of the semiconductor layer; a first a metal layer forming a first terminal on a side of the first dielectric layer opposite to the semiconductor layer; a second metal layer on a side of the second dielectric layer opposite to the semiconductor layer forming a second terminal and a third terminal extending through the second dielectric layer in contact with the semiconductor layer, the second terminal not in contact with the semiconductor layer; and a voltage source, It is coupled with one of the second terminal and the third terminal to reduce the resistance of the semiconductor layer, and the other of the second terminal and the third terminal forms a capacitor with the semiconductor layer. The second and third terminals may be source and drain terminals, and the first terminal may be a gate terminal. The second metal layer may be divided to form the second terminal and the third terminal, and the first terminal may be shared with one of the second terminal and the third terminal. The second and third terminals may be connected to form a capacitor between the semiconductor layer and the second and third terminals. A power source of switched voltage may be connected to the terminals of the film capacitor.

In FIG. 7, a capacitor is formed between the semiconductor layer and at least one of the two metal layers on opposite sides of the semiconductor layer. Each metal layer is separated from the semiconductor layer by a dielectric layer. The main challenge is that semiconductors are very resistive, and therefore, the RC delay associated with charging the capacitor will be high, resulting in lower frame rates or lag.

To avoid high RC delays, three-terminal capacitors are used as shown in Figures 8 and 9. The first metal layer on one side of the semiconductor layer is separated from the semiconductor layer by the first dielectric layer and forms a first terminal A for controlling the resistivity of the semiconductor layer. The second metal layer on the other side of the semiconductor layer is separated from the semiconductor layer by the second dielectric layer. The second metal layer is divided to form a second terminal B and a third terminal C, thereby forming a capacitor between the terminal B and the terminal C. Terminal C extends through the second dielectric layer to contact the semiconductor layer.

In one example, terminal A is connected to a low or high voltage line in the panel, depending on the type of semiconductor (eg, low for p-type and high for n-type). In this case, the resistance of the semiconductor layer is significantly lowered by charge accumulation (or consumption). In another example, terminal A is shared with the other terminal (B or C). In this case, one of these terminals has a voltage which reduces the resistance of the semiconductor material, depending on the type of semiconductor.

In Figures 8 and 9 there are two contacts between the terminal C and the semiconductor layer, but one contact or more than two contacts are also possible (depending on the available area).

The order of the layers can vary, and Figures 8 and 9 show an example of a 3-terminal capacitor.

The voltage on the control terminal of the capacitor can be a fixed voltage or a switched voltage. In the case of switching voltages, the RC delay to charge or discharge the capacitor can be controlled. For example, a voltage that reduces the RC delay can be used during charging of the capacitor, and then a voltage for the hold cycle that makes the capacitor more stable. In this case, the characteristics of the capacitor do not change significantly due to the high voltage difference bias stress.

Figure 10 shows another structure that provides high capacitance values without adding additional processing steps to the manufacturing process. Since the second dielectric 2 is usually thicker than the semiconductor layer, the conventional approach with stacked dielectrics results in smaller capacitors than using stacked semiconductors and dielectrics. Here, the second dielectric is etched, during which the dielectric layer is patterned, and then the metal for electrode B is deposited in contact with the semiconductor layer through the opening in the pattern. In order to have a consistent capacitance, electrode B and electrode A can be connected in such a way that the voltage across both electrodes A and B is always higher or lower than the threshold voltage of the formed metal-insulator-semiconductor capacitor. Therefore, a semiconducting layer will always act as an insulator or a conductor layer.

While particular embodiments and applications of the present invention have been shown and described, it is to be understood that the invention is not limited to the precise constructions and compositions disclosed herein and does not depart from the spirit of the invention as defined in the appended claims. Various modifications, changes, and variations may become apparent from the foregoing description, given the scope and scope.

Claims (6)

1. A film capacitor comprising: a semiconductor layer having a controllable resistance; a first dielectric layer and a second dielectric layer disposed on opposite sides of the semiconductor layer; a first metal layer forming a first terminal on the opposite side of the first dielectric layer from the semiconductor layer; a second metal layer forming a second terminal and a third terminal on a side of the second dielectric layer opposite the semiconductor layer, the third terminal extending through the second dielectric layer to communicate with the second dielectric layer the semiconductor layer is in contact and the second terminal is not in contact with the semiconductor layer; and a voltage source coupled to one of the first terminal and the second terminal to reduce the resistance of the semiconductor layer, and the other of the first terminal and the second terminal is connected to The semiconductor layer forms a capacitor. 2. The film capacitor of claim 1, wherein the second terminal and the third terminal are a source terminal and a drain terminal, and the first terminal is a gate terminal. 3. The film capacitor of claim 1, wherein the second metal layer is divided to form the second terminal and the third terminal. 4. The film capacitor of claim 1, wherein the first terminal is shared with one of the second terminal and the third terminal. 5. The film capacitor according to claim 1, wherein the second terminal is connected to the first terminal, and a capacitor is formed between the semiconductor layer and the first terminal and the second terminal. 6. The film capacitor of claim 1, wherein a power source for switching a voltage is connected to a terminal of the film capacitor.