CN104734657B

CN104734657B - A kind of chip and its port Impedance matching and correlation circuit

Info

Publication number: CN104734657B
Application number: CN201310700398.5A
Authority: CN
Inventors: 赵鹏; 宋阳; 李帅人; 刘艳娇
Original assignee: ShenZhen Guowei Electronics Co Ltd
Current assignee: ShenZhen Guowei Electronics Co Ltd
Priority date: 2013-12-18
Filing date: 2013-12-18
Publication date: 2017-11-10
Anticipated expiration: 2033-12-18
Also published as: CN104734657A

Abstract

The invention belongs to chip port impedance match technique field, there is provided a kind of chip and its port Impedance matching and correlation circuit.The present invention adjusts total resistance of first resistor matching module or second resistance matching module in chip by Digital Logic control module,And control the voltage and the voltage of first resistor matching module or the voltage of second resistance matching module of resistance comparison module alternating acquisition non-essential resistance,By resistance comparison module to the voltage of non-essential resistance compared with the first internal resistance voltage or the second internal resistance voltage,And feedback signal is compared to Digital Logic control module according to comparative result output,Judge whether total resistance of first resistor matching module or second resistance matching module is equal to the resistance of non-essential resistance according to comparing feedback signal by Digital Logic control module again,It is,Then show that impedance matching is completed,It is no,Then Digital Logic control module continues to adjust total resistance of first resistor matching module or second resistance matching module and completes the purpose of impedance matching to reach.

Description

A kind of chip and its port Impedance matching and correlation circuit

Technical field

The invention belongs to chip port impedance match technique field, more particularly to a kind of chip and its port Impedance matching school Positive circuit.

Background technology

Stepped up with the transmission rate of data communication system from KHz ranks to GHz ranks, the transmission of signal is increasingly Influenceed by chip port impedance and its matching factor.In traditional system design, because the integrated level of chip is relatively low, it is Control degree of the engineer for system of uniting is higher, tends not to imparting chip and possesses self-correction port status and impedance spy Property ability, when finding that matching problem occurs in port Impedance, system engineer typically directly adds extra on system board Match circuit, and manually debug mode resolved impedance spectroscopy mismatch the problem of.The advantages of this mode is flexible, but to core The requirement of piece user is high.With the increasing of the integrated trend of system, system scale becomes increasing, and the design of system is difficult Degree also increases therewith, and because chip manufacturer is often unwilling to provide the interconnection of on-chip system (SOC, System On Chip) Structure and correlative detail, and the port for being available for outside debugging that chip is reserved is fewer and fewer, so as to cause the extensive of system It is integrated to realize.In order to solve this problem, the method that prior art provides a port self-correcting and impedance matching, it is logical The input port and output port crossed in chip integrate the matching internal resistance with matches impedances on line.However, due to Chip technology problem, resistance deviation often can reach 30%, this will result in actual flow come out impedance and simulation value between It is widely different, and can increase signal reflex on line when deviation is excessive and reduce the communication quality of physical circuit.

In summary, the deviation that prior art is present between impedance and the impedance simulation value because of chip internal build-out resistor is big And the problem of increasing signal reflex on line and reducing the communication quality of physical circuit.

The content of the invention

It is an object of the invention to provide a kind of chip port impedance matching correcting circuit, it is intended to solves prior art and is deposited Increase signal reflex on line because the deviation between the impedance of chip internal build-out resistor and impedance simulation value is big and reduce The problem of communication quality of physical circuit.

The present invention is achieved in that a kind of chip port impedance matching correcting circuit, is built in chip, and with the core Resistance access switch module connection inside piece, the resistance access switch module connection non-essential resistance, the resistance access are opened Module is closed to be used to control the annexation between the non-essential resistance and the chip；

The chip port impedance matching correcting circuit includes Digital Logic control module, reference current supplying module, the One resistors match module, second resistance matching module and resistance comparison module；

It is the Digital Logic control module and the resistance access switch module, the reference current supplying module, described First resistor matching module, the second resistance matching module and resistance comparison module connection, the reference current supply The first resistor matching module, the second resistance matching module and resistance access switch module are connected to module, Reference current access interface, the second resistance matching module of the resistance comparison module and the first resistor matching module Reference current access interface and the resistance access switch module current input terminal be connected；

The Digital Logic control module output digital controlled signal drives the reference current supplying module output corresponding Voltage, the Digital Logic control module alternately the first comparison control signal of output and the second comparison control signal to the resistance It is worth comparison module and resistance access switch module；

When the Digital Logic control module exports the first comparison control signal, the Digital Logic control module is by institute The total resistance for stating first resistor matching module and the second resistance matching module is arranged to zero, and the resistance accesses switch module The non-essential resistance is accessed by the chip according to first comparison control signal, and obtained from the reference current supplying module Reference current to the non-essential resistance, the resistance comparison module is taken to pass through the resistance according to first comparison control signal Access the voltage that switch module obtains the non-essential resistance；

When the Digital Logic control module exports the second comparison control signal, resistance access switch module according to Second comparison control signal disconnects the connection between the non-essential resistance and the chip, while the Digital Logic controls Total resistance of the first resistor matching module or the second resistance matching module is arranged to the resistance value being not zero by module, The first resistor matching module or the second resistance matching module obtain reference current from the reference current supplying module And corresponding first internal resistance voltage or the second internal resistance voltage are produced, the resistance comparison module is according to the described second ratio The first internal resistance voltage or the second internal resistance voltage are obtained compared with control signal；

The resistance comparison module is by the voltage of the non-essential resistance and the first internal resistance voltage or described second Internal resistance voltage is compared, and compares feedback signal to the Digital Logic control module, institute according to comparative result output State Digital Logic control module and the first resistor matching module or the second resistance are judged according to the relatively feedback signal Whether total resistance of matching module is identical with the resistance of the non-essential resistance, if it is, the Digital Logic control module control Make the first resistor matching module or the second resistance matching module maintains former resistance constant, if it is not, then the numeral Logic control module adjusts total resistance of the first resistor matching module or the second resistance matching module, and keeps replacing The first comparison control signal and the second comparison control signal are exported so that the resistance comparison module continues to the non-essential resistance Voltage compared with the first internal resistance voltage or the second internal resistance voltage, until the first resistor Untill total resistance with module or the second resistance matching module is equal to the resistance of the non-essential resistance.

Another object of the present invention, which also resides in, provides a kind of chip, including resistance access switch module, the resistance access Switch module connects non-essential resistance, and the resistance access switch module is used to control between the non-essential resistance and the chip Annexation；The chip also includes above-mentioned chip port impedance matching correcting circuit.

The present invention includes Digital Logic control module, reference current supplying module, first resistor by using in the chips The chip port impedance matching correcting circuit of matching module, second resistance matching module and resistance comparison module, passes through numeral Logic control module adjusts total resistance of first resistor matching module or second resistance matching module, and controls resistance comparison module Alternately obtain the voltage of non-essential resistance and the voltage (i.e. the first internal resistance voltage) or second resistance of first resistor matching module The voltage (i.e. the second internal resistance voltage) of matching module, by resistance comparison module to the voltage of non-essential resistance and the first inside electricity Resistance voltage or the second internal resistance voltage are compared, and are compared feedback signal to Digital Logic according to comparative result output and controlled Module, then judge that first resistor matching module or second resistance match mould according to feedback signal is compared by Digital Logic control module Whether total resistance of block is identical with the resistance of non-essential resistance, is, then shows that impedance matching is completed, no, then Digital Logic control mould Block continues to adjust total resistance of first resistor matching module or second resistance matching module to reach the purpose of completion impedance matching, Solves deviation between impedance because of chip internal build-out resistor and impedance simulation value present in prior art so as to solve The problem of increasing signal reflex on line greatly and reduce the communication quality of physical circuit.

Brief description of the drawings

Fig. 1 is the function structure chart of chip port impedance matching correcting circuit provided in an embodiment of the present invention；

Fig. 2 is the reference current supplying module in chip port impedance matching correcting circuit provided in an embodiment of the present invention Exemplary block diagram；

Fig. 3 is the first resistor matching module in chip port impedance matching correcting circuit provided in an embodiment of the present invention Exemplary block diagram；

Fig. 4 is the second resistance matching module in chip port impedance matching correcting circuit provided in an embodiment of the present invention Exemplary block diagram；

Fig. 5 is the example of the resistance comparison module in chip port impedance matching correcting circuit provided in an embodiment of the present invention Structure chart.

Embodiment

In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.

Fig. 1 shows the modular structure of chip port impedance matching correcting circuit provided in an embodiment of the present invention, in order to just In explanation, the part related to the embodiment of the present invention is illustrate only, details are as follows：

Chip port impedance matching correcting circuit 100 is built in chip, and accesses switch module with the resistance of chip internal 200 current input terminal connection, the output end connection non-essential resistance R of resistance access switch module 200_EXT, resistance access switching molding Block 200 is used to control the annexation between non-essential resistance and chip.

Chip port impedance matching correcting circuit 100 includes Digital Logic control module 101, reference current supplying module 102nd, first resistor matching module 103, second resistance matching module 104 and resistance comparison module 105.

Digital Logic control module 101 and resistance access switch module 200, reference current supplying module 102, first resistor Matching module 103, second resistance matching module 104 and resistance comparison module 105 connect, reference current supplying module 102 The current input terminal of current output terminal connection first resistor matching module 103, the access of the reference current of second resistance matching module 104 Port and the reference current access interface of resistance access switch module 200, resistance comparison module 105 match mould with first resistor The reference current access interface of block 103, the reference current access interface of second resistance matching module 104 and resistance access switch The current input terminal of module 200 is connected.

Digital Logic control module 101 exports digital controlled signal driving reference current supplying module 102 and exported accordingly Voltage, Digital Logic control module 101 alternately output the first comparison control signal and the second comparison control signal to resistance value ratio compared with Module 105 and resistance access switch module 200.

When Digital Logic control module 101 exports the first comparison control signal, Digital Logic control module 101 is by first Resistors match module 103 and total resistance of second resistance matching module 104 are arranged to zero, the resistance access basis of switch module 200 First comparison control signal is by non-essential resistance R_EXTAccess chip, and reference current is obtained to outer from reference current supplying module 102 Portion resistance R_EXT, resistance comparison module 105 according to the first comparison control signal by resistance access switch module 200 obtain outside Resistance R_EXTVoltage.

When Digital Logic control module 101 exports the second comparison control signal, resistance accesses switch module 200 according to the Two comparison control signals disconnect non-essential resistance R_EXTConnection between chip, while Digital Logic control module 101 is electric by first Total resistance of resistance matching module 103 or second resistance matching module 104 is arranged to the resistance value being not zero, first resistor matching mould Block 103 or second resistance matching module 104 obtain reference current from reference current supplying module 102 and produced in corresponding first Portion's resistive voltage or the second internal resistance voltage, resistance comparison module 105 obtain described first according to the second comparison control signal Internal resistance voltage or the second internal resistance voltage.

Resistance comparison module 105 is by non-essential resistance R_EXTVoltage and the first internal resistance voltage or described second in Portion's resistive voltage is compared, and compares feedback signal to Digital Logic control module 101 according to comparative result output, and numeral is patrolled Volume control module 101 judges the total of first resistor matching module 103 or second resistance matching module 104 according to feedback signal is compared Resistance whether with non-essential resistance R_EXTResistance it is identical, if it is, Digital Logic control module 101 control first resistor matching Module 103 or second resistance matching module 104 maintain former resistance constant, if it is not, then the adjustment of Digital Logic control module 101 the Total resistance of one resistors match module 103 or second resistance matching module 104, and keep alternately the first comparison control signal of output With the second comparison control signal so that resistance comparison module 105 continues to non-essential resistance R_EXTVoltage with described first inside electricity Resistance voltage or the second internal resistance voltage are compared, until first resistor matching module 103 or second resistance matching mould Untill total resistance of block 104 is equal to the resistance of the non-essential resistance.

As one embodiment of the invention, Digital Logic control module 101 can be the CPU for possessing mathematical logic disposal ability (Central Processing Unit, CPU) or MCU (Micro Control Unit, micro-control unit).

As one embodiment of the invention, as shown in Fig. 2 reference current supplying module 102 includes partial pressure unit 1021, first Switch element K1, second switch unit K2, the 3rd switch element K3, the 4th switch element K4, the 5th switch element K5, the 6th open Close unit K6, the 7th switch element K7, the 8th switch element K8, the 9th switch element K9, the tenth switch element K10, the 11st Switch element K11, the 12nd switch element K12, the 13rd switch element K13, the 14th switch element K14, the 15th switch Unit K15, sixteenmo close unit K16, the 17th switch element K17, eighteenmo and close unit K18, the 19th switch element K19, the 20th switch element K20, the 21st switch element K21, the 22nd switch element K22, the 23rd switch are single First K23, the 24th switch element K24, the 25th switch element K25, the second sixteenmo pass unit K26, the 27th are opened Close unit K27, the second eighteenmo closes unit K28, the 29th switch element K29, the 30th switch element K30, the 31st Switch element K31.

The input and output end of partial pressure unit 1021 connect reference power supply VCC and ground respectively, first switch unit K1's First input end and the second input connect the first partial pressure end and the second partial pressure end of partial pressure unit 1021, second switch list respectively First K2 first input end and the second input connect the 3rd partial pressure end and the 4th partial pressure end of partial pressure unit 1021 respectively, and the 3rd Switch element K3 first input end and the second input connect the 5th partial pressure end and the 6th partial pressure of partial pressure unit 1021 respectively End, the 4th switch element K4 first input end and the second input connect the 7th partial pressure end and the of partial pressure unit 1021 respectively Eight partial pressure ends, the 5th switch element K5 first input end and the second input connect the 9th partial pressure of partial pressure unit 1021 respectively End and the tenth point of pressure side, the 6th switch element K6 first input end and the second input connect the of partial pressure unit 1021 respectively 11 partial pressure ends and the 12nd partial pressure end, the 7th switch element K7 first input end and the second input connect partial pressure list respectively The 13rd partial pressure end and the 14th partial pressure end of member 1021, the 8th switch element K8 first input end and the second input difference Connect the 15th partial pressure end and the 16th partial pressure end of partial pressure unit 1021, first switch unit K1 the first controlled end and second Switch element K2 the first controlled end, the 3rd switch element K3 the first controlled end, the 4th switch element K4 the first controlled end, 5th switch element K5 the first controlled end, the 6th switch element K6 the first controlled end, the first of the 7th switch element K7 by Control end and the 8th switch element K8 the first controlled end connect and connect Digital Logic control module 101 altogether, first switch unit K1 the second controlled end and second switch unit K2 the second controlled end, the 3rd switch element K3 the second controlled end, the 4th open Close unit K4 the second controlled end, the 5th switch element K5 the second controlled end, the 6th switch element K6 the second controlled end, the Seven switch element K7 the second controlled end and the 8th switch element K8 the second controlled end connect and connect Digital Logic control altogether Module 101, the 9th switch element K9 first input end and the second input connect first switch unit K1 output end respectively With second switch unit K2 output end, the tenth switch element K10 first input end and the second input connect the 3rd respectively The output end of switch element K3 output end and the 4th switch element K4, the 11st switch element K11 first input end and Two inputs connect the 5th switch element K5 output end and the 6th switch element K6 output end, the 12nd switch element respectively K12 first input end and the second input connect respectively the 7th switch element K7 output end and the 8th switch element K8 it is defeated Go out end, the 9th switch element K9 the first controlled end and the tenth switch element K10 the first controlled end, the 11st switch element K11 the first controlled end and the 12nd switch element K12 the first controlled end connect and connect Digital Logic control module altogether 101, the 9th switch element K9 the second controlled end and the tenth switch element K10 the second controlled end, the 11st switch element K11 The second controlled end and the 12nd switch element K12 the second controlled end connect altogether and connect Digital Logic control module 101, The output end and the tenth that 13 switch element K13 first input end and the second input connects the 9th switch element K9 respectively is opened Unit K10 output end is closed, the 14th switch element K14 first input end and the second input connect the 11st switch respectively The output end of unit K11 output end and the 12nd switch element K12, the 13rd switch element K13 the first controlled end and 14 switch element K14 the first controlled end connects and connects the switch element K13's of Digital Logic control module the 101, the 13rd altogether Second controlled end and the 14th switch element K14 the second controlled end connect and connect Digital Logic control module 101 altogether, and the 15th Switch element K15 first input end and the second input connect the 13rd switch element K13 output end and the 14th respectively Switch element K14 output end, the 15th switch element K15 the first controlled end and the connection Digital Logic control of the second controlled end Module 101, sixteenmo closes unit K16 first input end and the second input connects the 15th switch element K15's respectively The output end of output end and the 17th switch element K17, sixteenmo closes unit K16 the first controlled end and the second controlled end connects Digital Logic control module 101 is connect, sixteenmo closes electric current of the unit K16 output end as reference current supplying module 102 Output end, the 17th switch element K17 first input end and the second input connect eighteenmo and close the defeated of unit K18 respectively Go out end and the 19th switch element K19 output end, the 17th switch element K17 the first controlled end and the connection of the second controlled end Digital Logic control module 101, eighteenmo closes unit K18 first input end and the second input connects the 20th and opened respectively Close unit K20 output end and the 21st switch element K21 output end, the 19th switch element K19 first input end Connect the 22nd switch element K22 output end and the 23rd switch element K23 output end respectively with the second input, First controlled end of the first controlled end and the 19th switch element K19 that eighteenmo closes unit K18 connects and connects numeral altogether patrols Collect the switch element K20 of control module the 101, the 20th first input end and the second input connects the 24th switch list respectively The output end of first K24 output end and the 25th switch element K25, the 21st switch element K21 first input end and Second input connects the second sixteenmo and closes unit K26 output end and the 27th switch element K27 output end respectively, the 22 switch element K22 first input end and the second input connects the output end that the second eighteenmo closes unit K28 respectively With the 29th switch element K29 output end, the 23rd switch element K23 first input end and the second input difference Connect the 30th switch element K30 output end and the 31st switch element K31 output end, the 20th switch element K20 The first controlled end and the 21st switch element K21 the first controlled end, the 22nd switch element K22 the first controlled end And the 23rd switch element K23 the first controlled end connect altogether and connect Digital Logic control module 101, the 20th switch is single First K20 the second controlled end and the 21st switch element K21 the second controlled end, the second of the 22nd switch element K22 Controlled end and the 23rd switch element K23 the second controlled end connect and connect Digital Logic control module 101 altogether, and the 20th Four switch element K24 first input end and the second input connect the 17th partial pressure end and the tenth of partial pressure unit 1021 respectively Eight partial pressure ends, the 25th switch element K25 first input end and the second input connect the of partial pressure unit 1021 respectively 19 partial pressure ends and the second ten points of pressure sides, the second sixteenmo closes unit K26 first input end and the second input connects respectively 21st partial pressure end of partial pressure unit 1021 and the 22nd partial pressure end, the 27th switch element K27 first input end Connect the 23rd partial pressure end and the 24th partial pressure end of partial pressure unit 1021 respectively with the second input, the second eighteenmo closes Unit K28 first input end and the second input connect the 25th partial pressure end and the 26th of partial pressure unit 1021 respectively Partial pressure end, the 29th switch element K29 first input end and the second input connect the second of partial pressure unit 1021 respectively 17 partial pressure ends and the 28th partial pressure end, the 30th switch element K30 first input end and the second input connect respectively 29th partial pressure end of partial pressure unit 1021 and the 30th point of pressure side, the 31st switch element K31 first input end and Second input connects the 31st partial pressure end and the 32nd partial pressure end of partial pressure unit 1021 respectively, and the 24th switch is single First K24 the first controlled end and the 25th switch element K25 the first controlled end, the second sixteenmo close the first of unit K26 Controlled end, the 27th switch element K27 the first controlled end, the second eighteenmo close unit K28 the first controlled end, the 20th Nine switch element K29 the first controlled end, the 30th switch element K30 the first controlled end and the 31st switch element K31 the first controlled end connects and connects the switch element K24 of Digital Logic control module the 101, the 24th the second controlled end altogether Second controlled end of the second controlled end, the second sixteenmo pass unit K26 with the 25th switch element K25, the 27th are opened Close unit K27 the second controlled end, the second eighteenmo closes unit K28 the second controlled end, the of the 29th switch element K29 Second controlled end of two controlled ends, the 30th switch element K30 the second controlled end and the 31st switch element K31 connects altogether And Digital Logic control module 101 is connected, first switch unit K1 earth terminal and second switch unit K2 earth terminal, the 3rd Switch element K3 earth terminal, the 4th switch element K4 earth terminal, the 5th switch element K5 earth terminal, the 6th switch element K6 earth terminal, the 7th switch element K7 earth terminal, the 8th switch element K8 earth terminal, the 9th switch element K9 ground connection End, the tenth switch element K10 earth terminal, the 11st switch element K11 earth terminal, the 12nd switch element K12 ground connection End, the 13rd switch element K13 earth terminal, the 14th switch element K14 earth terminal, the 15th switch element K15 connect Ground terminal, sixteenmo close unit K16 earth terminal, the 17th switch element K17 earth terminal, eighteenmo and close unit K18's Earth terminal, the 19th switch element K19 earth terminal, the 20th switch element K20 earth terminal, the 21st switch element K21 earth terminal, the 22nd switch element K22 earth terminal, the 23rd switch element K23 earth terminal, the 24th Switch element K24 earth terminal, the 25th switch element K25 earth terminal, the second sixteenmo close unit K26 earth terminal, 27th switch element K27 earth terminal, the second eighteenmo close unit K28 earth terminal, the 29th switch element K29 The earth terminal of earth terminal, the 30th switch element K30 earth terminal and the 31st switch element K31 is connected to ground altogether.

Wherein, partial pressure unit 1021 is the resistance string being formed by connecting by multiple resistance identical resistant series, and each two Partial pressure end of the common contact of resistance as partial pressure unit 1021, i.e., above-mentioned the first partial pressure end to the 32nd partial pressure end.

First switch unit K1, second switch unit K2, the 3rd switch element K3, the 4th switch element K4, the 5th switch Unit K5, the 6th switch element K6, the 7th switch element K7, the 8th switch element K8, the 9th switch element K9, the tenth switch are single First K10, the 11st switch element K11, the 12nd switch element K12, the 13rd switch element K13, the 14th switch element K14, the 15th switch element K15, sixteenmo close unit K16, the 17th switch element K17, eighteenmo close unit K18, 19th switch element K19, the 20th switch element K20, the 21st switch element K21, the 22nd switch element K22, 23rd switch element K23, the 24th switch element K24, the 25th switch element K25, the second sixteenmo close unit It is single that K26, the 27th switch element K27, the second eighteenmo close unit K28, the 29th switch element K29, the 30th switch First K30 and the 31st switch element K31 is internal structure identical switch element, and the switch element includes the first NMOS First input end of pipe N1 and the second NMOS tube N2, the first NMOS tube N1 drain electrode as switch element, the first NMOS tube N1's Output end of the common contact of source electrode and the second NMOS tube N2 drain electrode as switch element, the second NMOS tube N2 source electrode, which is used as, to be opened Close the second input of unit, the first NMOS tube N1 grid and the second NMOS tube N2 grid respectively as switch element the The common contact of one controlled end and the second controlled end, the first NMOS tube N1 substrate and the second NMOS tube N2 substrate is single as switch The earth terminal of member.

In said reference electric current supplying module 102, what the resistance string in partial pressure unit 1021 exported to reference power supply VCC Direct current carries out partial pressure, and partial pressure direct current is produced at the partial pressure end of partial pressure unit 1021, included in each switch element The switch controlling signal that first NMOS tube N1 and the second NMOS tube N2 is sent according to Digital Logic control module 101 is realized corresponding Make-break operation (the first NMOS tube N1 does not turn on the second NMOS tube N2 in the same time), and in conducting from partial pressure unit 1021 partial pressure end obtains partial pressure direct current, and unit K16 output end (the first NMOS tube N1 source electrode is finally closed in sixteenmo With the common contact of the second NMOS tube N2 drain electrodes) the corresponding reference current of output, sixteenmo pass unit K16 output voltage is (i.e. The output voltage of reference current supplying module 101) size depend on all switch elements in partial pressure unit 1021 and included First NMOS tube N1 and the second NMOS tube N2 on off operating mode.

Assuming that reference power supply VCC voltage is V₀, then the output voltage Vout of reference current supplying module 102 is with each opening Close corresponding relation (the same switch as shown in the table of the on off operating mode of the first NMOS tube N1 and the second NMOS tube N2 in unit The first NMOS tube N1 and the second NMOS tube N2 in unit have opposite level to be controlled respectively)：

As shown in Fig. 2 the first NMOS tube N1 and the second NMOS tube N2 in first switch unit K1 are respectively by B₀WithControl System, B₀WithOpposite levels each other, i.e. B₀For high level when,For low level, similarly, first in the 9th switch element K9 NMOS tube N1 and the second NMOS tube N2 are respectively by B₁WithControl, the first NMOS tube N1 in the 13rd switch element K13 and the Two NMOS tube N2 are respectively by B₂WithControl, N2 points of the first NMOS tube N1 and the second NMOS tube in the 15th switch element K15 Not by B₃WithControl, the first NMOS tube N1 and the second NMOS tube N2 in the unit K16 of sixteenmo pass are respectively by B₄WithControl Make, the first NMOS tube N1 and the second NMOS tube N2 in the 17th switch element K17 are respectively by B₃WithControl, eighteenmo close The first NMOS tube N1 and the second NMOS tube N2 in unit K18 is respectively by B₂WithControl, the in the 20th switch element K20 One NMOS tube N1 and the second NMOS tube N2 are respectively by B₁WithControl, the first NMOS tube N1 in the 24th switch element K24 With the second NMOS tube N2 respectively by B₀WithControl, remaining switch element is also to be controlled according to above-mentioned principle, therefore not Repeat again.

As one embodiment of the invention, as shown in figure 3, first resistor matching module 103 includes the first fixed resistance value module 1031 and the first resistance value changeable terminals module 1032.

Total resistance of first resistor matching module 103 can variable resistance for total resistance and first of the first fixed resistance value module 1031 It is worth total resistance sum of module 1032, total resistance of the first fixed resistance value module 1031 is immutable, is controlled in Digital Logic When module 101 is adjusted to total resistance of first resistor matching module 103, Digital Logic control module 101 is can to first The total resistance for becoming resistance module 1032 is adjusted.

First fixed resistance value module 1031 includes first resistor R1, the 32nd NMOS tube N32, the 33rd NMOS tube N33, second resistance R2, the 34th NMOS tube N34,3rd resistor R3, the 35th NMOS tube N35, the 4th resistance R4, the 3rd 16 NMOS tube N36, the 5th resistance R5, the 37th NMOS tube N37, the 6th resistance R6, the 38th NMOS tube N38, the 7th Resistance R7, the 39th NMOS tube N39, the 8th resistance R8, the 40th NMOS tube N40, the 9th resistance R9, the 41st NMOS tube N41, the tenth resistance R10, the 42nd NMOS tube N42, the 11st resistance R11, the 43rd NMOS tube N43, the 12nd resistance R12, the 44th NMOS tube N44, the 13rd resistance R13 and the 45th NMOS tube N45.

First resistance value changeable terminals module 1032 includes the 15th resistance R15, the 46th NMOS tube N46, the 47th NMOS Pipe N47, the 48th NMOS tube N48, the 49th NMOS tube N49, the 16th resistance R16, the 50th NMOS tube N50, the 5th 11 NMOS tube N51, the 17th resistance R17, the 52nd NMOS tube N52, the 18th resistance R18, the 53rd NMOS tube N53, the 19th resistance R19, the 54th NMOS tube N54, the 20th resistance R20, the 55th NMOS tube N55, the 21st Resistance R21, the 56th NMOS tube N56, the 22nd resistance R22, the 57th NMOS tube N57, the 23rd resistance R23, 58th NMOS tube N58, the 24th resistance R24 and the 59th NMOS tube N59.

First resistor R1 first end and second resistance R2 first end, 3rd resistor R3 first end, the 4th resistance R4 First end, the 5th resistance R5 first end, the 6th resistance R6 first end, the 7th resistance R7 first end, the 8th resistance R8 First end, the 9th resistance R9 first end, the tenth resistance R10 first end, the 11st resistance R11 first end, the 12nd Resistance R12 first end, the 13rd resistance R13 first end, the 15th resistance R15 first end, the of the 16th resistance R16 One end, the 17th resistance R17 first end, the 18th resistance R18 first end, the 19th resistance R19 first end, the 20th Resistance R20 first end, the 21st resistance R21 first end, the 22nd resistance R22 first end, the 23rd resistance R23 first end and the 24th resistance R24 first end connect the common contact to be formed as first resistor matching module altogether 103 reference current access interface, first resistor R1 the 32nd NMOS tube N32 of the second end connection drain electrode, the 32nd NMOS tube N32 source electrode connects the 33rd NMOS tube N33 drain electrode, the 32nd NMOS tube N32 grid and the 33rd NMOS tube N33 grid connects and accesses the first control level altogether, and second resistance R2 the second end connects the 34th NMOS tube N34 Drain electrode, the 34th NMOS tube N34 grid access first control level, 3rd resistor R3 the second end connection the 35th NMOS tube N35 drain electrode, the 35th NMOS tube N35 grid access the first control level, the 4th resistance R4 the second end connects Meet the 36th NMOS tube N36 drain electrode, the 36th NMOS tube N36 grid access the first control level, the 5th resistance R5 The second end connect the 37th NMOS tube N37 drain electrode, the 37th NMOS tube N37 grid access first control level, 6th resistance R6 the second end connects the 38th NMOS tube N38 drain electrode, the 38th NMOS tube N38 grid access first Level is controlled, the 7th resistance R7 the second end connects the 39th NMOS tube N39 drain electrode, the 39th NMOS tube N39 grid Pole access the first control level, the 8th resistance R8 the second end connects the 40th NMOS tube N40 drain electrode, the 40th NMOS tube N40 grid access the first control level, the 9th resistance R9 the 41st NMOS tube N41 of the second end connection drain electrode, the 4th 11 NMOS tube N41 grid access the first control level, the tenth resistance R10 the second end connects the 42nd NMOS tube N42 Drain electrode, the 42nd NMOS tube N42 grid access first control level, the 11st resistance R11 the second end connection the 4th 13 NMOS tube N43 drain electrode, the 43rd NMOS tube N43 grid access the first control level, the of the 12nd resistance R12 The 44th NMOS tube N44 of two ends connection drain electrode, the 44th NMOS tube N44 grid access the first control level, the tenth Three resistance R13 the second end connects the 45th NMOS tube N45 drain electrode, the 45th NMOS tube N45 grid access first Control level, the 32nd NMOS tube N32 substrate, the 33rd NMOS tube N33 substrate and source electrode, the 34th NMOS tube N34 substrate and source electrode, the 35th NMOS tube N35 substrate and source electrode, the 36th NMOS tube N36 substrate and source electrode, 37th NMOS tube N37 substrate and source electrode, the 38th NMOS tube N38 substrate and source electrode, the 39th NMOS tube N39 Substrate and source electrode, the 40th NMOS tube N40 substrate and source electrode, the 41st NMOS tube N41 substrate and source electrode, the 40th Two NMOS tube N42 substrate and source electrode, the 43rd NMOS tube N43 substrate and source electrode, the 44th NMOS tube N44 substrate Ground, the 15th resistance R15 the second end connection the 40th are connected to altogether with source electrode, the 45th NMOS tube N45 substrate and source electrode Six NMOS tube N46 drain electrode, the 47th NMOS tube N47 drain electrode and source electrode connect the 46th NMOS tube N46 source respectively Pole and the 48th NMOS tube N48 drain electrode, the 48th NMOS tube N48 source electrode connect the 49th NMOS tube N49 leakage Pole, the 46th NMOS tube N46 grid and the 47th NMOS tube N47 grid, the 48th NMOS tube N48 grid with And the 49th NMOS tube N49 grid connect altogether and connect Digital Logic control module 101, the 16th resistance R16 the second end The 50th NMOS tube N50 drain electrode is connected, the 50th NMOS tube N50 source electrode connects the 51st NMOS tube N51 drain electrode, the 50 NMOS tube N50 grid connects and is connected Digital Logic control module 101 altogether with the 51st NMOS tube N51 grid, the 17 resistance R17 the second end connects the 52nd NMOS tube N52 drain electrode, the 52nd NMOS tube N52 grid connection number The resistance R18 of word Logic control module the 101, the 18th the 53rd NMOS tube N53 of the second end connection drain electrode, the 53rd The NMOS tube N53 resistance R19 of grid connection Digital Logic control module the 101, the 19th the second end connects the 54th NMOS Pipe N54 drain electrode, the 20th resistance R20 the second end connect the 55th NMOS tube N55 drain electrode, the 54th NMOS tube The NMOS tube N53 of N54 the 54th grid connects and is connected Digital Logic control module altogether with the 55th NMOS tube N55 grid 101, the 21st resistance R21 the 56th NMOS tube N56 of the second end connection drain electrode, the second of the 22nd resistance R22 The 57th NMOS tube N57 of end connection drain electrode, the 23rd resistance R23 the second end connect the 58th NMOS tube N58's Drain electrode, the 24th resistance R24 the second end connect the 59th NMOS tube N59 drain electrode, the 56th NMOS tube N56 grid Pole and the 57th NMOS tube N57 grid, the 58th NMOS tube N58 grid and the 59th NMOS tube N59 grid Extremely connect altogether and connect the NMOS tube N46 of Digital Logic control module the 101, the 46th substrate, the 47th NMOS tube N47 lining Bottom, the NMOS tube N47 of the 48th NMOS tube N48 the 48th substrate, the 49th NMOS tube N49 substrate and source electrode, 50 NMOS tube N50 substrate, the 51st NMOS tube N51 substrate and source electrode, the 52nd NMOS tube N52 substrate and source Pole, the 53rd NMOS tube N53 substrate and source electrode, the 54th NMOS tube N54 substrate and source electrode, the 55th NMOS tube N55 substrate and source electrode, the 56th NMOS tube N56 substrate and source electrode, the 57th NMOS tube N57 substrate and source electrode, 58th NMOS tube N58 substrate and source electrode, the 59th NMOS tube N59 substrate and source electrode is connected to ground altogether.

Wherein, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the 11st resistance R11, the 12nd resistance R12, the 13rd resistance R13, the 18th resistance R18, the 19th resistance R19, the 20th resistance R20, the 21st resistance R21, the 22nd resistance R22, the 23rd resistance R23 and the 24th resistance R24 resistance are identical and are the first resistance Ω 1, first resistor R1 with 17th resistance R17 resistance is identical and is the second resistance Ω 2, and the 16th resistance R16 resistance is the 3rd resistance Ω 3, and the tenth Five resistance R15 resistance is the 4th resistance Ω 4, and Ω 2 is 2 times of Ω 1, and Ω 3 is 2 times of Ω 2, and Ω 4 is 2 times of Ω 3, so, Ω 2=2 × Ω 1, Ω 3=2 × Ω 2=4 × Ω 1, Ω 4=2 × Ω 3=8 × Ω 1.

When total resistance of first resistor matching module 103 is arranged to the resistance being not zero by Digital Logic control module 101 During value, in above-mentioned first resistor matching module 103, Digital Logic control module 101 exports the first above-mentioned control level Control the 32nd NMOS tube N32, the 33rd NMOS tube N33, the 34th NMOS tube N34, the 35th NMOS tube N35, 36th NMOS tube N36, the 37th NMOS tube N37, the 38th NMOS tube N38, the 39th NMOS tube N39, the 4th Ten NMOS tube N40, the 41st NMOS tube N41, the 42nd NMOS tube N42, the 43rd NMOS tube N43, the 44th NMOS tube N44 and the 45th NMOS tube N45 are all turned on, then total resistance of the first fixed resistance value module 1031 is mutually simultaneously First resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th electricity of connection Hinder R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance R10, the 11st resistance R11, the 12nd resistance R12 and the 13rd Resistance obtained by resistance R13 parallel connections, for total resistance of the first fixed resistance value module 1031 as a reference resistor value, its is bigger than normal In the standard electric resistance needed for chip.For the first resistance value changeable terminals module 1032, due to the 46th NMOS tube N46, the 40th Seven NMOS tube N47, the 48th NMOS tube N48 and the 49th NMOS tube N49 are that grid connects altogether, so four be to simultaneously turn on Or shut-off, similarly, the 50th NMOS tube N50 and the 51st NMOS tube N51 are also to simultaneously turn on or turn off, and the 54th NMOS tube N54 and the 55th NMOS tube N55 is also to simultaneously turn on or turn off, the 56th NMOS tube N56, the 57th NMOS tube N57, the 58th NMOS tube N58 and the 59th NMOS tube N59 are also to simultaneously turn on or turn off.

In an alternative embodiment of the invention, above-mentioned first control level is directly fed by power supply to ensure the 32nd NMOS Pipe N32, the 33rd NMOS tube N33, the 34th NMOS tube N34, the 35th NMOS tube N35, the 36th NMOS tube N36, the 37th NMOS tube N37, the 38th NMOS tube N38, the 39th NMOS tube N39, the 40th NMOS tube N40, 41 NMOS tube N41, the 42nd NMOS tube N42, the 43rd NMOS tube N43, the 44th NMOS tube N44 and the 4th 15 NMOS tube N45 are all turned on, and chip port impedance matching correcting circuit also includes resistance access on-off circuit, and it is connected Between reference current supplying module 102 and first resistor matching module 103, when Digital Logic control module 101 is electric by first When total resistance of resistance matching module 103 is arranged to zero, Digital Logic control module 101 controls resistance access on-off circuit to disconnect base Connection between quasi- electric current supplying module 102 and first resistor matching module 103；When Digital Logic control module 101 is by first When total resistance of resistors match module 103 is arranged to the resistance value being not zero, resistance access on-off circuit is controlled by Digital Logic Module 101 is controlled and turned on, and the reference current so as to which reference current supplying module 102 is exported introduces first resistor matching Module 103.

If using the 15th resistance R15 as first resistor unit C, the 16th resistance R16 as second resistance cells D, 17th resistance R17 as 3rd resistor unit E, the 18th resistance R18 as the 4th resistance unit F, the 19th resistance R19 and 20th resistance R20 forms the 5th resistance unit G, the 21st resistance R21, the 22nd resistance R22, the 23rd resistance R23 and the 24th resistance R24 forms the 6th resistance unit H, then first resistor unit C total resistance is Ω 4=8 × Ω 1, Total resistance of second resistance cells D is Ω 3=4 × Ω 1, and 3rd resistor unit E total resistance is Ω 2=2 × Ω 1, and the 4th is electric The total resistance for hindering unit F is Ω 1, and the 5th resistance unit G total resistance is(the 19th resistance R19 and the 20th resistance R20 Resistance obtained by parallel connection), the 6th resistance unit H total resistance is(the 21st resistance R21, the 22nd resistance R22, Resistance obtained by 23rd resistance R23 and the 24th resistance R24 parallel connections), it is known that, from first resistor unit C to Six resistance unit H, total resistance are successively decreased with 1/2 relation, thus can form a resistance scan correction array, and numeral is patrolled Total resistance that control module 101 adjusts the first resistance value changeable terminals module 1032 according to order from big to small is collected, i.e., first turns on first The PMOS that the maximum resistance unit of total resistance is connected in resistance unit C to the 6th resistance unit H, then according to resistance value ratio compared with The comparison feedback signal of module 105 accordingly turns on the PMOS that the less resistance unit of total resistance is connected, by repeatedly adjusting Total resistance of first resistor matching module 103 is set to be equal to non-essential resistance R afterwards_EXTResistance, so as to realize impedance matching.Above-mentioned number The PMOS that word Logic control module 101 controls first resistor unit C to the 6th resistance unit H to be connected realizes the order of conducting It is as shown in the table that (" 0 " represents shut-off, and " 1 " represents conducting, and the turn-on sequence of PMOS is performed from the sequential control of following table the first row To last column)：

For upper table, if adjusting the first resistance value changeable terminals module 1032 according to certain a line in Digital Logic control module 101 Total resistance after, the first internal resistance voltage caused by first resistor matching module 103 is equal to non-essential resistance R_EXTVoltage, Then show that total resistance of first resistor matching module 103 is equal to non-essential resistance R_EXTResistance, therefore impedance matching complete, numeral Logic control module 101 continues to corresponding PMOS according to the row and turned on.

As one embodiment of the invention, as shown in figure 4, second resistance matching module 104 includes the second fixed resistance value module 1041 and the second resistance value changeable terminals module 1042.

Total resistance of second resistance matching module 104 can variable resistance for total resistance and second of the second fixed resistance value module 1041 It is worth total resistance sum of module 1042, total resistance of the second fixed resistance value module 1041 is immutable, is controlled in Digital Logic When module 101 is adjusted to total resistance of second resistance matching module 104, Digital Logic control module 101 is can to second The total resistance for becoming resistance module 1042 is adjusted.

Second fixed resistance value module 1041 includes the 3rd NMOS tube N3, the 4th NMOS tube N4, the 25th resistance R25, the 26 resistance R26, the 27th resistance R27, the 28th resistance R28, the 29th resistance R29, the 30th resistance R30, 31st resistance R31 and the 32nd resistance R32.

Second resistance value changeable terminals module 1042 includes the first phase inverter INV1, first switch adjustment unit KS1, second switch and adjusted Save unit KS2, the 33rd resistance R33, the 34th resistance R34, the 35th resistance R35, the 36th resistance R36, the Two phase inverter INV2, the 3rd switch-mode regulation unit KS3, the 4th switch-mode regulation unit KS4, the 37th resistance R37, the 38th Resistance R38, the 3rd phase inverter INV3, the 5th switch-mode regulation unit KS5, the 6th switch-mode regulation unit KS6, the 39th resistance R39, the 4th phase inverter INV4, the 7th switch-mode regulation unit KS7, the 8th switch-mode regulation unit KS8, the 40th resistance R40, the 4th 11 resistance R41, the 5th phase inverter INV5, the 9th switch-mode regulation unit KS9, the tenth switch-mode regulation unit KS10, the 42nd Resistance R42, the 43rd resistance R43, the 44th resistance R44, the 45th resistance R45, hex inverter INV6, the 11st Switch-mode regulation unit KS11, the 12nd switch-mode regulation unit KS12, the 46th resistance R46, the 47th resistance R47, the 4th 18 resistance R48, the 49th resistance R49, the 50th resistance R50, the 51st resistance R51, the 52nd resistance R52 and 53rd resistance R53.

3rd NMOS tube N3 grid and the 4th NMOS tube N4 grid access the second control level, the 25th resistance R25 first end and the 26th resistance R26 first end, the 27th resistance R27 first end, the 28th resistance R28 First end, the 29th resistance R29 first end, the 30th resistance R30 first end, the first of the 31st resistance R31 End and the 32nd resistance R32 first end connect the 3rd NMOS tube N3 of the common contact to be formed connection simultaneously drain electrode and the altogether Four NMOS tube N4 drain electrode, the first phase inverter INV1 input, the second phase inverter INV2 input, the 3rd phase inverter INV3 Input, the 4th phase inverter INV4 input, the 5th phase inverter INV5 input and hex inverter INV6 it is defeated Enter end and be all connected with Digital Logic control module 101, first switch adjustment unit KS1 controlled end and second switch adjustment unit KS2 controlled end is connected to the first phase inverter INV1 output end, first switch adjustment unit KS1 first input end and second altogether Switch-mode regulation unit KS2 first input end connects the 3rd NMOS tube N3 grid and the 4th NMOS tube N4 grid respectively, the The first end of 33 resistance R33 first end and the 34th resistance R34, the 35th resistance R35 first end and the The common contact of 36 resistance R36 first end while the second input and second switch with first switch adjustment unit KS1 Adjustment unit KS2 the second input connection；3rd switch-mode regulation unit KS3 controlled end and the 4th switch-mode regulation unit KS4 Controlled end be connected to the second phase inverter INV2 output end altogether, the 3rd switch-mode regulation unit KS3 first input end and the 4th is opened The first input end for closing adjustment unit KS4 connects the 3rd NMOS tube N3 grid and the 4th NMOS tube N4 grid respectively, and the 3rd The common contact of 17 resistance R37 first end and the 38th resistance R38 first end simultaneously with the 3rd switch-mode regulation unit KS3 The second input and the 4th switch-mode regulation unit KS4 the second input connection；5th switch-mode regulation unit KS5 controlled end It is connected to the 3rd phase inverter INV3 output end, the 5th switch-mode regulation unit KS5 altogether with the 6th switch-mode regulation unit KS6 controlled end First input end and the 6th switch-mode regulation unit KS6 first input end connect the 3rd NMOS tube N3 grid and the 4th respectively NMOS tube N4 grid, the 39th resistance R39 first end simultaneously with the 5th switch-mode regulation unit KS5 the second input and 6th switch-mode regulation unit KS6 the second input connection；7th switch-mode regulation unit KS7 controlled end and the 8th switch-mode regulation Unit KS8 controlled end is connected to the 4th phase inverter INV4 output end altogether, the 7th switch-mode regulation unit KS7 first input end and 8th switch-mode regulation unit KS8 first input end connects the 3rd NMOS tube N3 grid and the 4th NMOS tube N4 grid respectively Pole, the 40th resistance R40 first end while the second input and the 8th switch-mode regulation list with the 7th switch-mode regulation unit KS7 First KS8 the second input connection, the 40th resistance R40 the second end connect the 41st resistance R41 first end；9th opens The controlled end of the controlled end and the tenth switch-mode regulation unit KS10 that close adjustment unit KS9 is connected to the 5th phase inverter INV5 output altogether End, the 9th switch-mode regulation unit KS9 first input end and the tenth switch-mode regulation unit KS10 first input end connect respectively 3rd NMOS tube N3 grid and the 4th NMOS tube N4 grid, the 42nd resistance R42 first end switch with the 9th simultaneously Adjustment unit KS9 the second input and the tenth switch-mode regulation unit KS10 the second input connect, the 43rd resistance R43 It is connected between the 42nd resistance R42 the second end and the 44th resistance R44 first end, the 44th resistance R44's Second end connects the 45th resistance R45 first end；11st switch-mode regulation unit KS11 controlled end and the 12nd switch Adjustment unit KS12 controlled end is connected to hex inverter INV6 output end altogether, and the first of the 11st switch-mode regulation unit KS11 Input and the 12nd switch-mode regulation unit KS12 first input end connect the 3rd NMOS tube N3 grid and the 4th respectively NMOS tube N4 grid, the 46th resistance R46 first end the second input with the 11st switch-mode regulation unit KS11 simultaneously End connects with the 12nd switch-mode regulation unit KS12 the second input, and the 47th resistance R47 is connected to the 46th resistance Between R46 the second end and the 48th resistance R48 first end, the 48th resistance R48 the second end connection the 49th Resistance R49 first end, the 50th resistance R50 are connected to the 49th resistance R49 the second end with the 51st resistance R51's Between first end, the 52nd resistance R52 is connected to the of the 51st resistance R51 the second end and the 53rd resistance R53 Between one end；25th resistance R25 the second end and the 26th resistance R26 the second end, the of the 27th resistance R27 Two ends, the 28th resistance R28 the second end, the 29th resistance R29 the second end, the 30th resistance R30 the second end, 31 resistance R31 the second end and the 32nd resistance R32 the second end connect the common contact to be formed, the 33rd electricity altogether Hinder R33 the second end and the second end of the 34th resistance R34, the 35th resistance R35 the second end and the 36th electricity Hinder common contact, the 37th resistance R37 the second end and the connecing altogether for the 38th resistance R38 the second end at R36 the second end Point, the 39th resistance R39 the second end, the 41st resistance R41 the second end, the 45th resistance R45 the second end with And the 53rd resistance R53 the second end connect reference current of the common contact to be formed as second resistance matching module 104 altogether Access interface；3rd NMOS tube N3 substrate and source electrode, the 4th NMOS tube N4 substrate and source electrode, first switch adjustment unit KS1 earth terminal, second switch adjustment unit KS2 output end, the 3rd switch-mode regulation unit KS3 output end, the 4th switch Adjustment unit KS4 output end, the 5th switch-mode regulation unit KS5 output end, the 6th switch-mode regulation unit KS6 output end, 7th switch-mode regulation unit KS7 output end, the 8th switch-mode regulation unit KS8 output end, the 9th switch-mode regulation unit KS9 Output end, the tenth switch-mode regulation unit KS10 output end, the 11st switch-mode regulation unit KS11 output end and the 12nd Switch-mode regulation unit KS12 output end is connected to ground altogether.

Wherein, the 25th resistance R25, the 26th resistance R26, the 27th resistance R27, the 28th resistance R28, 29th resistance R29, the 30th resistance R30, the 31st resistance R31, the 32nd resistance R32, the 33rd resistance R33, the 34th resistance R34, the 35th resistance R35, the 36th resistance R36, the 37th resistance R37, the 38th Resistance R38, the 39th resistance R39, the 40th resistance R40, the 41st resistance R41, the 42nd resistance R42, the 40th Three resistance R43, the 44th resistance R44, the 45th resistance R45, the 46th resistance R46, the 47th resistance R47, 48 resistance R48, the 49th resistance R49, the 50th resistance R50, the 51st resistance R51, the 52nd resistance R52 with And the 53rd resistance R53 resistance it is identical, be the first foregoing resistance Ω 1, then the 25th resistance R25, the 26th Resistance R26, the 27th resistance R27, the 28th resistance R28, the 29th resistance R29, the 30th resistance R30, the 30th Resistance obtained by one resistance R31 and the 32nd resistance R32 parallel connections is33rd resistance R33, the 34th electricity Resistance obtained by resistance R34, the 35th resistance R35 and the 36th resistance R36 parallel connections is37th resistance R37 It is with the resistance obtained by the 38th resistance R38 parallel connections40th resistance R40 and the 41st resistance R41 series connection gained The resistance arrived is the resistance R42 of 2 × Ω the 1, the 42nd, the 43rd resistance R43, the electricity of the 44th resistance R44 and the 45th It is the resistance R46 of 4 × Ω the 1, the 46th, the 47th resistance R47, the 48th resistance to hinder the resulting resistance of R45 series connection R48, the 49th resistance R49, the 50th resistance R50, the 51st resistance R51, the 52nd resistance R52 and the 53rd Resistance obtained by resistance R53 series connection is 8 × Ω 1.

First switch adjustment unit KS1 and second switch adjustment unit KS2 is structure identical switch-mode regulation unit, described Switch-mode regulation unit includes the 30th PMOS P30, the 56th NMOS tube N56, the 57th NMOS tube N57, the 58th NMOS tube N58, the 59th NMOS tube N59 and the 60th NMOS tube N60；30th PMOS P30 grid and the 50th Controlled end of the common contact of six NMOS tube N56 grid as switch-mode regulation unit, the 30th PMOS P30 drain electrode and substrate First input end of the common contact as switch-mode regulation unit, the 30th PMOS P30 source electrode and the 56th NMOS tube N56 Drain electrode be connected to the 57th NMOS tube N57 grid, the 58th NMOS tube N58 grid and the 59th NMOS tube altogether N59 grid and the 60th NMOS tube N60 grid are connected to the 57th NMOS tube N57 grid, the 57th NMOS altogether Second input of the pipe N57 drain electrode as the switch-mode regulation unit, the 58th NMOS tube N58 drain electrode, the 59th NMOS tube N59 drain electrode and the 60th NMOS tube N60 drain electrode are connected to the 57th NMOS tube N57 drain electrode altogether, and the 50th Six NMOS tube N56 source electrode and substrate, the 57th NMOS tube N57 source electrode and substrate, the 58th NMOS tube N58 source electrode Connect to be formed altogether with substrate, the 59th NMOS tube N59 source electrode and substrate and the 60th NMOS tube N60 source electrode and substrate Output end of the common contact as switch-mode regulation unit.

3rd switch-mode regulation unit KS3 and the 4th switch-mode regulation unit KS4 is structure identical switch-mode regulation unit, described Switch-mode regulation unit includes the 38th PMOS P38, the 61st NMOS tube N61, the 62nd NMOS tube N62 and the 6th 13 NMOS tube N63；The common contact of 38th PMOS P38 grid and the 61st NMOS tube N61 grid, which is used as, to be opened Close the controlled end of adjustment unit, the 38th PMOS P38 drain electrode and the common contact of substrate as switch-mode regulation unit the One input, the 38th PMOS P38 source electrode and the 61st NMOS tube N61 drain electrode and the 63rd NMOS tube N63 grid is connected to the grid of the 62nd NMOS tube N62, the 62nd NMOS tube N62 drain electrode and the 63rd altogether Second input of the common contact of NMOS tube N63 drain electrode as the switch-mode regulation unit, the 61st NMOS tube N61 Source electrode and substrate, source electrode and substrate and the 63rd NMOS tube the N63 source electrode and lining of the 62nd NMOS tube N62 Bottom connects output end of the common contact to be formed as switch-mode regulation unit altogether.

5th switch-mode regulation unit KS5 and the 6th switch-mode regulation unit KS6 is structure identical switch-mode regulation unit, and this is opened Closing adjustment unit includes the 39th PMOS P39, the 64th NMOS tube N64 and the 65th NMOS tube N65；39th Controlled end of the common contact of PMOS P39 grid and the 64th NMOS tube N64 grid as switch-mode regulation unit, the 3rd First input end of the 19 PMOS P39 drain electrode as switch-mode regulation unit, the 39th PMOS P39 source electrode and the 6th 14 NMOS tube N64 drain electrode is connected to the 65th NMOS tube N65 grid, the 65th NMOS tube N65 drain electrode conduct altogether Second input of switch-mode regulation unit, the 39th PMOS P39 substrate, the 64th NMOS tube N64 substrate and source Pole and the 65th NMOS tube N65 substrate and source electrode connect output of the common contact to be formed as switch-mode regulation unit altogether End.

7th switch-mode regulation unit KS7 and the 8th switch-mode regulation unit KS8 is structure identical switch-mode regulation unit, and this is opened Closing adjustment unit includes the 31st PMOS P31, the 7th NMOS tube N7, the 8th NMOS tube N8 and the 9th NMOS tube N9；The Controlled end of the common contact of 31 PMOS P31 grid and the 7th NMOS tube N7 grid as switch-mode regulation unit, the 31 PMOS P31 first input end of the drain electrode as switch-mode regulation unit, the 31st PMOS P31 source electrode and the The common contact of seven NMOS tube N7 drain electrode connects the common contact of the 8th NMOS tube N8 grid and the 9th NMOS tube N9 grid, the Second input of the eight NMOS tube N8 drain electrode as switch-mode regulation unit, the 8th NMOS tube N8 source electrode connect the 9th NMOS tube N9 drain electrode, the 31st PMOS P31 substrate, the 7th NMOS tube N7 substrate and source electrode, the 8th NMOS tube N8 substrate And the 9th NMOS tube N9 substrate and source electrode connect output end of the common contact to be formed as switch-mode regulation unit altogether.

9th switch-mode regulation unit KS9 and the tenth switch-mode regulation unit KS10 is structure identical switch-mode regulation unit, should Switch-mode regulation unit includes the 32nd PMOS P32, the tenth NMOS tube N10, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube N13 and the 14th NMOS tube N14；32nd PMOS P32 drain electrode is as switch-mode regulation list The first input end of member, the 32nd PMOS P32 source electrode are connected the 11st with the common contact of the tenth NMOS tube N10 drain electrode The grid and the 14th NMOS tube of NMOS tube N11 grid and the 12nd NMOS tube N12 grid, the 13rd NMOS tube N13 The common contact of N14 grid, the 11st NMOS tube N11 the second input to drain as switch-mode regulation unit, the 12nd NMOS tube N12 drain electrode and source electrode connect the drain electrode of the 11st NMOS tube N11 source electrode and the 13rd NMOS tube N13 respectively, the 13 NMOS tube N13 source electrode connects the 14th NMOS tube N14 drain electrode, the 32nd PMOS P32 substrate, the tenth NMOS Pipe N10 substrate and source electrode, the 11st NMOS tube N11 substrate, the 12nd NMOS tube N12 substrate, the 13rd NMOS tube N13 Substrate and the 14th NMOS tube N14 substrate and source electrode connect output of the common contact to be formed as switch-mode regulation unit altogether End.

11st switch-mode regulation unit KS11 and the 12nd switch-mode regulation unit KS12 is structure identical switch-mode regulation list Member, the switch-mode regulation unit include the 33rd PMOS P33, the 15th NMOS tube N15, the 16th NMOS tube N16, the 17th NMOS tube N17, the 18th NMOS tube N18, the 19th NMOS tube N19, the 20th NMOS tube N20, the 21st NMOS tube N21, 22nd NMOS tube N22 and the 23rd NMOS tube N23；33rd PMOS P33 grid and the 15th NMOS tube Controlled end of the common contact of N15 grid as switch-mode regulation unit, the 33rd PMOS P33 drain electrode is as switch-mode regulation The first input end of unit, the 33rd PMOS P33 the 15th NMOS tube N15 of source electrode connection drain electrode, the 33rd PMOS P33 grid is connected the 16th NMOS tube N16 grid and the tenth with the common contact of the 15th NMOS tube N15 grid Seven NMOS tube N17 grid, the 18th NMOS tube N18 grid, the 19th NMOS tube N19 grid, the 20th NMOS tube N20 Grid, the 21st NMOS tube N21 grid, the 22nd NMOS tube N22 grid and the 23rd NMOS tube N23 Grid connects the common contact to be formed altogether, the second input of the 16th NMOS tube N16 drain electrode as switch-mode regulation unit, and the tenth Seven NMOS tube N17 drain electrode and source electrode connect the drain electrode of the 16th NMOS tube N16 source electrode and the 18th NMOS tube N18 respectively, 19th NMOS tube N19 drain electrode and source electrode connect the leakage of the 18th NMOS tube N18 source electrode and the 20th NMOS tube N20 respectively Pole, the 21st NMOS tube N21 drain electrode and source electrode connect the 20th NMOS tube N20 source electrode and the 22nd NMOS tube respectively N22 drain electrode, the 22nd NMOS tube N22 source electrode connect the 23rd NMOS tube N23 drain electrode, the 33rd PMOS P33 substrate, the 15th NMOS tube N15 substrate and source electrode, the 16th NMOS tube N16 substrate, the 17th NMOS tube N17 Substrate, the 18th NMOS tube N18 substrate, the 19th NMOS tube N19 substrate, the 20th NMOS tube N20 substrate, the 20th One NMOS tube N21 substrate, the 22nd NMOS tube N22 substrate and the 23rd NMOS tube N23 substrate and source electrode is total to Connect output end of the common contact to be formed as switch-mode regulation unit.

When total resistance of second resistance matching module 104 is arranged to the resistance being not zero by Digital Logic control module 101 During value, in above-mentioned second resistance matching module 104, Digital Logic control module 101 exports the second above-mentioned control level To control the 3rd NMOS tube N3 and the 4th NMOS tube N4 conductings, so total resistance of the second fixed resistance value module 1041 is fixed not Become.

And in an alternative embodiment of the invention, above-mentioned second control level is directly fed by power supply to ensure the 3rd NMOS tube N3 and the 4th NMOS tube N4 conductings, so that total resistance of the second fixed resistance value module 1041 immobilizes, and chip port Impedance matching correcting circuit also includes electric resistance array on-off circuit, and it is connected to reference current supplying module 102 and second resistance Between matching module 104, when total resistance of second resistance matching module 104 is arranged to zero by Digital Logic control module 101, Digital Logic control module 101 controls electric resistance array on-off circuit to disconnect reference current supplying module 102 and matched with second resistance Connection between module 104；When total resistance of second resistance matching module 104 is arranged to not by Digital Logic control module 101 During the resistance value for being zero, electric resistance array on-off circuit is controlled by Digital Logic control module 101 and turned on, so as to which benchmark is electric The reference current that stream supplying module 102 is exported introduces second resistance matching module 104.

For the second resistance value changeable terminals module 1042, if by the 46th resistance R46, the 47th resistance R47, the 40th Eight resistance R48, the 49th resistance R49, the 50th resistance R50, the 51st resistance R51, the 52nd resistance R52 and 53 resistance R53 are as the first adjustable resistance unit C1, by the 42nd resistance R42, the 43rd resistance R43, the 40th Four resistance R44 and the 45th resistance R45 are as the second adjustable resistance unit D1, by the electricity of the 40th resistance R40 and the 41st R41 is hindered as the 3rd adjustable resistance unit E1, using the 39th resistance R39 as the 4th adjustable resistance unit F1, by the 30th Seven resistance R37 and the 38th resistance R38 are as the 5th adjustable resistance unit G1, by the 33rd resistance R33, the 34th electricity R34, the 35th resistance R35 and the 36th resistance R36 are hindered as the 6th adjustable resistance unit H1, then from the first adjustable resistance For unit C1 to the 6th adjustable resistance unit H1, resistance is successively decreased with 1/2 relation, thus can also form a resistance scan school Positive array, its control principle control the principle of first resistor matching module 103 identical with aforementioned digital Logic control module 101, Therefore repeat no more.

Further, since first switch adjustment unit KS1 and second switch adjustment unit KS2 structures are identical and anti-by first Phase device INV1 output signal control, the 3rd switch-mode regulation unit KS3 and the 4th switch-mode regulation unit KS4 structures it is identical and by Second phase inverter INV2 output signal control, the 5th switch-mode regulation unit KS5 and the 6th switch-mode regulation unit KS6 structures are identical And controlled by the 3rd phase inverter INV3 output signal, the 7th switch-mode regulation unit KS7 and the 8th switch-mode regulation unit KS8 knots Structure is identical and output signal control by the 4th phase inverter INV4, the 9th switch-mode regulation unit KS9 and the tenth switch-mode regulation list First KS10 structures it is identical and by the 5th phase inverter INV5 output signal control, the 11st switch-mode regulation unit KS11 and the tenth Two switch-mode regulation unit KS12 structures it is identical and by hex inverter INV6 output signal control, using such symmetrical junction Structure is advantageous to reduce parasitic parameter, shown that circuit performance can be made more stable.

As one embodiment of the invention, as shown in figure 5, resistance comparison module 105 includes：

24th NMOS tube N24, the 25th NMOS tube N25, the 26th NMOS tube N26, the 27th NMOS tube N27, the 28th NMOS tube N28, the 29th NMOS tube N29, the 30th NMOS tube N30, the 31st NMOS tube N31, 34 PMOS P34, the 35th PMOS P35, the 36th PMOS P36, the 37th PMOS P37, the 50th Four resistance R54, the 55th resistance R55, the 56th resistance R56, the 57th resistance R57, the 58th resistance R58, 59 resistance R59, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and level shifting circuit 1051；

24th NMOS tube N24 grid and the 31st NMOS tube N31 grid connect altogether, and are controlled from Digital Logic Module 101 receives the first comparison control signal or the second comparison control signal, the 24th NMOS tube N24 source electrode and the 50th Four resistance R54 first end is connected to the 27th NMOS tube N27 grid altogether, the 54th resistance R54 the second end connection the Two electric capacity C2 first end, the 56th resistance R56 first end are connected to the 20th altogether with the 57th resistance R57 first end Four NMOS tube N24 drain electrode, the 55th resistance R55 are connected to the 34th PMOS P34 source electrode and the 56th resistance Between R56 the second end, the 57th resistance R57 the second end, the 25th NMOS tube N25 drain and gate, the 20th Eight NMOS tube N28 grid and the 29th NMOS tube N29 grid connect altogether, the 34th PMOS P34 drain electrode and the 35 PMOS P35 drain electrode, the 36th PMOS P36 drain electrode and the 37th PMOS P37 drain electrode connects altogether In the 30th NMOS tube N30 drain electrode, the 35th PMOS P35 source electrode and grid are connected to the 36th PMOS P36 altogether Grid, the 26th NMOS tube N26 drain electrode connection the 35th PMOS P35 source electrode, the 27th NMOS tube N27's Drain electrode and the 37th PMOS P37 grid are connected to the 36th PMOS P36 source electrode, the 26th NMOS tube N26 altogether Source electrode and the 27th NMOS tube N27 source electrode be connected to the 28th NMOS tube N28 drain electrode altogether, the second of the second electric capacity C2 End and the 25th NMOS tube N25 source electrode, the 28th NMOS tube N28 source electrode and the 29th NMOS tube N29 source Extremely it is connected to ground altogether, the drain electrode of the 37th PMOS P37 source electrode and the 29th NMOS tube N29, the 30th NMOS tube N30 Source electrode and the 31st NMOS tube N31 drain electrode are connected to the input of level shifting circuit 1051, level shifting circuit altogether The 1051 NMOS tube N31 of output end connection Digital Logic control module the 101, the 31st source electrode and the 26th NMOS tube N26 grid is connected to the 58th resistance R58 first end altogether, and the 58th resistance R58 the second end connects the 3rd electric capacity C3 First end, the 3rd electric capacity C3 the second end and the first electric capacity C1 first end is connected to the 59th resistance R59 first end altogether, First electric capacity C1 the second end ground connection, the electric current of the 59th resistance R59 the second end connection resistance access switch module 200 are defeated The reference current for entering end, the reference current access interface of first resistor matching module 103 and second resistance matching module 104 connects Inbound port.

In above-mentioned resistance comparison module 105, it is assumed that the output current of reference current supplying module 102 is I, when the 20th Four NMOS tube N24 grid and the 31st NMOS tube N31 grid are high level (the first i.e. foregoing comparison control signal) When, resistance access switch module 200 is simultaneously according to the high level by non-essential resistance R_EXTAccess chip, first resistor matching module 103 and total resistance of second resistance matching module 104 be arranged to zero by Digital Logic control module 101, so now the 5th Switch module 200 and non-essential resistance R is accessed in 19 resistance R59 the second end by resistance_EXTConnection, the 59th resistance R59's The voltage V at the second end_b1=I × R_EXT(V_b1As non-essential resistance R_EXTVoltage), the 24th NMOS tube N24 and the 31st NMOS tube N31 is both turned on, then electric current is carried out by the 24th NMOS tube N24 and the 54th resistance R54 to the second electric capacity C2 Charging, so the 26th NMOS tube N26 grid voltage V_inWith the 27th NMOS tube N27 grid voltage V_ipIt is equal to Second electric capacity C2 voltage V_C2, i.e. V_ip=V_in=V_C2, the 3rd electric capacity C3 both end voltages V_C3=V_in- V_b1=V_C2- V_b1。

When the 24th NMOS tube N24 grid and the 31st NMOS tube N31 grid are low level (i.e. foregoing the Two comparison control signals) when, resistance access switch module 200 disconnects non-essential resistance R according to the low level simultaneously_EXTWith chip Connection, Digital Logic control module 101 set total resistance of first resistor matching module 103 or second resistance matching module 104 Be set to the resistance value being not zero, thus now the 59th resistance R59 the second end by with first resistor matching module 103 or Second resistance matching module 104 connects, the voltage V at the 59th resistance R59 the second end_b2=I × R (V_b2As foregoing One internal resistance voltage or the second internal resistance voltage), R is first resistor matching module 103 or second resistance matching module 104 Total resistance, now the 24th NMOS tube N24 and the 31st NMOS tube N31 be turned off, according to law of conservation of charge, the 3rd The voltage V at electric capacity C3 both ends_C3=V_C2- V_b1, so the voltage of the 3rd electric capacity C3 top crown is V_C2- V_b1+V_b2, then so 26 NMOS tube N26 grid voltage V_in=V_C2- V_b1+V_b2。

In summary, the comparator in resistance comparison module 105 is (by the 26th NMOS tube N26, the 27th NMOS tube N27, the 35th PMOS P35, the 36th PMOS P36 and the 37th PMOS P37 are formed) input difference The grid of grid and the 27th NMOS tube N27 for the 26th NMOS tube N26, so the electricity of two inputs of comparator Pressure is respectively V_ipAnd V_in, and V_ip=V_C2, V_in=V_C2- V_b1+V_b2。

If V_ip>V_in, then V is shown_b1>V_b2, i.e. total resistance or the second resistance matching of first resistor matching module 103 Total resistance of module 104 is less than outer meeting resistance R_EXTResistance, then the 37th PMOS P37 source electrode is as comparator Output end exports high level to level shifting circuit 1051.

If V_ip<V_in, then V is shown_b1<V_b2, i.e. total resistance or the second resistance matching of first resistor matching module 103 Total resistance of module 104 is more than outer meeting resistance R_EXTResistance, then, the 37th PMOS P37 source electrode is as comparator Output end exports low level to level shifting circuit 1051.

Level shifting circuit 1051 exports more anti-after the corresponding level conversion processing of output level progress to comparator Feedback signal is electric to first according to the comparison feedback signal to Digital Logic control module 101, then by Digital Logic control module 101 The total resistance for hindering total resistance or second resistance matching module 104 of matching module 103 is adjusted, and first resistor is matched mould Total resistance of total resistance or second resistance matching module 104 of block 103 is eventually equal to non-essential resistance R_EXTResistance, so as to reach To the purpose of impedance matching correction.

Application based on said chip port Impedance matching and correlation circuit in the chips, the embodiment of the present invention additionally provide one Kind chip, it includes resistance access switch module 200, and resistance access switch module 200 connects non-essential resistance R_EXT, resistance access Switch module 200 is used to control non-essential resistance R_EXTAnnexation between chip；Said chip also includes the embodiment of the present invention The chip port impedance matching correcting circuit provided.

The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.

Claims

1. a kind of chip port impedance matching correcting circuit, being built in chip, and switch is accessed with the resistance of the chip internal Module connects, the resistance access switch module connection non-essential resistance, and the resistance access switch module is described outer for controlling Annexation between portion's resistance and the chip；It is characterized in that：

The chip port impedance matching correcting circuit includes Digital Logic control module, reference current supplying module, the first electricity Hinder matching module, second resistance matching module and resistance comparison module；

The Digital Logic control module and resistance access switch module, the reference current supplying module, described first Resistors match module, the second resistance matching module and resistance comparison module connection, the reference current supply mould Block connects the first resistor matching module, the second resistance matching module and resistance access switch module, described Reference current access interface, the base of the second resistance matching module of resistance comparison module and the first resistor matching module The current input terminal of quasi- electric current access interface and resistance access switch module is connected；

The Digital Logic control module output digital controlled signal drives the corresponding electricity of reference current supplying module output Pressure, the Digital Logic control module alternately export the first comparison control signal and the second comparison control signal to the resistance value ratio Compared with module and resistance access switch module；

When the Digital Logic control module exports the first comparison control signal, the Digital Logic control module is by described the Total resistance of one resistors match module and the second resistance matching module is arranged to zero, the resistance access switch module according to The non-essential resistance is accessed the chip by first comparison control signal, and obtains base from the reference current supplying module Quasi- electric current to the non-essential resistance, the resistance comparison module is accessed according to first comparison control signal by the resistance Switch module obtains the voltage of the non-essential resistance；

When the Digital Logic control module exports the second comparison control signal, the resistance accesses switch module according to Second comparison control signal disconnects the connection between the non-essential resistance and the chip, while the Digital Logic control module Total resistance of the first resistor matching module or the second resistance matching module is arranged to the resistance value being not zero, it is described First resistor matching module or the second resistance matching module obtain reference current from the reference current supplying module and produced Raw corresponding first internal resistance voltage or the second internal resistance voltage, the resistance comparison module compare control according to described second First internal resistance voltage described in signal acquisition processed or the second internal resistance voltage；

The resistance comparison module is by inside the voltage of the non-essential resistance and the first internal resistance voltage or described second Resistive voltage is compared, and compares feedback signal to the Digital Logic control module, the number according to comparative result output Word Logic control module judges that the first resistor matching module or the second resistance match according to the relatively feedback signal Whether total resistance of module is identical with the resistance of the non-essential resistance, if it is, the Digital Logic control module controls institute State first resistor matching module or the second resistance matching module maintains former resistance constant, if it is not, then the Digital Logic Control module adjusts total resistance of the first resistor matching module or the second resistance matching module, and keeps alternately exporting First comparison control signal and the second comparison control signal are so that the resistance comparison module continues the electricity to the non-essential resistance Pressure is compared with the first internal resistance voltage or the second internal resistance voltage, until first resistor matching mould Untill total resistance of block or the second resistance matching module is equal to the resistance of the non-essential resistance.

2. chip port impedance matching correcting circuit as claimed in claim 1, it is characterised in that the reference current supplies mould It is single that block includes partial pressure unit, first switch unit, second switch unit, the 3rd switch element, the 4th switch element, the 5th switch Member, the 6th switch element, the 7th switch element, the 8th switch element, the 9th switch element, the tenth switch element, the 11st are opened Unit, the 12nd switch element, the 13rd switch element, the 14th switch element, the 15th switch element, sixteenmo is closed to close Unit, the 17th switch element, eighteenmo close unit, the 19th switch element, the 20th switch element, the 21st switch Unit, the 22nd switch element, the 23rd switch element, the 24th switch element, the 25th switch element, second Sixteenmo closes unit, the 27th switch element, the second eighteenmo and closes unit, the 29th switch element, the 30th switch list Member and the 31st switch element；

The input and output end of the partial pressure unit connect reference power supply and ground respectively, and the first of the first switch unit is defeated Enter end and the second input connects the first partial pressure end and the second partial pressure end of the partial pressure unit, the second switch unit respectively First input end and the second input connect the 3rd partial pressure end and the 4th partial pressure end of the partial pressure unit respectively, the described 3rd The first input end of switch element and the second input connect the 5th partial pressure end and the 6th partial pressure end of the partial pressure unit respectively, The first input end and the second input of 4th switch element connect the 7th partial pressure end and of the partial pressure unit respectively Eight partial pressure ends, the first input end and the second input of the 5th switch element connect the 9th point of the partial pressure unit respectively Pressure side and the tenth point of pressure side, the first input end and the second input of the 6th switch element connect the partial pressure unit respectively The 11st partial pressure end and the 12nd partial pressure end, the first input end and the second input of the 7th switch element connect respectively 13rd partial pressure end of the partial pressure unit and the 14th partial pressure end, the first input end of the 8th switch element and second defeated Enter end and connect the 15th partial pressure end and the 16th partial pressure end of the partial pressure unit respectively, the first switch unit first by Control first controlled end at end and the second switch unit, the first controlled end of the 3rd switch element, the 4th switch First controlled end of unit, the first controlled end of the 5th switch element, the first controlled end of the 6th switch element, institute First controlled end of the first controlled end and the 8th switch element of stating the 7th switch element connects and connects the numeral altogether Logic control module, it is the second controlled end of the second controlled end of the first switch unit and the second switch unit, described Second controlled end of the 3rd switch element, the second controlled end of the 4th switch element, the second of the 5th switch element Controlled end, the second controlled end of the 6th switch element, the second controlled end and the described 8th of the 7th switch element Second controlled end of switch element connects and connects the Digital Logic control module altogether, the first input of the 9th switch element End and the second input connect the output end of the first switch unit and the output end of the second switch unit respectively, described The first input end and the second input of tenth switch element connect the output end and described of the 3rd switch element respectively The output end of four switch elements, the first input end and the second input of the 11st switch element connect the described 5th respectively The output end of the output end of switch element and the 6th switch element, the first input end of the 12nd switch element and Two inputs connect the output end of the 7th switch element and the output end of the 8th switch element respectively, and the described 9th opens Close the first controlled end of unit and the first controlled end of the tenth switch element, the first of the 11st switch element controlled First controlled end of end and the 12nd switch element connects and connects the Digital Logic control module altogether, and the described 9th opens Close the second controlled end of unit and the second controlled end of the tenth switch element, the second of the 11st switch element controlled Second controlled end of end and the 12nd switch element connects and connects the Digital Logic control module altogether, and the described 13rd The output end and the described tenth that the first input end of switch element and the second input connect the 9th switch element respectively is opened The output end of unit is closed, the first input end and the second input of the 14th switch element connect the described 11st and opened respectively Close the output end of unit and the output end of the 12nd switch element, the first controlled end of the 13rd switch element and institute The first controlled end for stating the 14th switch element connects and connects the Digital Logic control module altogether, the 13rd switch element The second controlled end and the second controlled end of the 14th switch element connect altogether and connect the Digital Logic control module, institute State the first input end of the 15th switch element and the second input connect respectively the 13rd switch element output end and Described in the output end of 14th switch element, the first controlled end of the 15th switch element and the connection of the second controlled end Digital Logic control module, the sixteenmo closes the first input end of unit and the second input connects the described 15th respectively The output end of the output end of switch element and the 17th switch element, the sixteenmo close unit the first controlled end and Second controlled end connects the Digital Logic control module, and the sixteenmo closes the output end of unit as the reference current The current output terminal of supplying module, the first input end and the second input of the 17th switch element connect described respectively Eighteenmo closes the output end of unit and the output end of the 19th switch element, and the first of the 17th switch element is controlled End connects the Digital Logic control module with the second controlled end, the first input end of eighteenmo pass unit and second defeated Enter to hold and connect the output end of the 20th switch element and the output end of the 21st switch element respectively, the described tenth The first input end of nine switch elements and the second input connect the output end of the 22nd switch element and described respectively The output end of 23rd switch element, the eighteenmo close the first controlled end of unit and the 19th switch element First controlled end connects and connects the Digital Logic control module altogether, the first input end and second of the 20th switch element Input connects the output end of the 24th switch element and the output end of the 25th switch element respectively, described The first input end and the second input of 21st switch element connect the output end that second sixteenmo closes unit respectively With the output end of the 27th switch element, the first input end and the second input point of the 22nd switch element Second eighteenmo is not connected closes the output end of unit and the output end of the 29th switch element, the described 23rd The first input end of switch element and the second input connect the output end and the described 3rd of the 30th switch element respectively The output end of 11 switch elements, the of the first controlled end of the 20th switch element and the 21st switch element First controlled end of one controlled end, the first controlled end of the 22nd switch element and the 23rd switch element Connect altogether and connect the Digital Logic control module, the second controlled end of the 20th switch element is opened with the described 21st Close the second controlled end of unit, the second controlled end of the 22nd switch element and the 23rd switch element Second controlled end connects and connects the Digital Logic control module altogether, the first input end of the 24th switch element and Two inputs connect the 17th partial pressure end and the 18th partial pressure end of the partial pressure unit, the 25th switch element respectively First input end and the second input connect respectively the partial pressure unit the 19th partial pressure end and the second ten points of pressure sides, it is described Second sixteenmo closes the first input end of unit and the second input connects the 21st partial pressure end of the partial pressure unit respectively With the 22nd partial pressure end, the first input end and the second input of the 27th switch element connect the partial pressure respectively 23rd partial pressure end of unit and the 24th partial pressure end, second eighteenmo close the first input end of unit and second defeated Enter the 25th partial pressure end and the 26th partial pressure end that end connects the partial pressure unit respectively, the 29th switch element First input end and the second input connect the 27th partial pressure end and the 28th partial pressure end of the partial pressure unit respectively, The first input end and the second input of 30th switch element connect the 29th partial pressure of the partial pressure unit respectively End and the 30th point of pressure side, the first input end and the second input of the 31st switch element connect the partial pressure respectively 31st partial pressure end of unit and the 32nd partial pressure end, the first controlled end of the 24th switch element and described the First controlled end of 25 switch elements, second sixteenmo close the first controlled end of unit, the 27th switch First controlled end of unit, second eighteenmo close the first controlled end of unit, the first of the 29th switch element First controlled end of controlled end, the first controlled end of the 30th switch element and the 31st switch element connects altogether And the Digital Logic control module is connected, the second controlled end of the 24th switch element and the described 25th switch Second controlled end of unit, second sixteenmo close the second controlled end of unit, the second of the 27th switch element Controlled end, second eighteenmo close the second controlled end, described of the second controlled end of unit, the 29th switch element Second controlled end of the second controlled end of the 30th switch element and the 31st switch element connects and connected described altogether The earth terminal of Digital Logic control module, the earth terminal of the first switch unit and the second switch unit, the described 3rd The earth terminal of switch element, the earth terminal of the 4th switch element, the earth terminal of the 5th switch element, the described 6th open Close the earth terminal of unit, the earth terminal of the 7th switch element, the earth terminal of the 8th switch element, the 9th switch The earth terminal of unit, the earth terminal of the tenth switch element, the earth terminal of the 11st switch element, the described 12nd are opened Close the earth terminal of unit, the earth terminal of the 13rd switch element, the earth terminal of the 14th switch element, the described tenth The earth terminal of five switch elements, the sixteenmo close the earth terminal, described of the earth terminal of unit, the 17th switch element Eighteenmo close the earth terminal of unit, the earth terminal of the 19th switch element, the 20th switch element earth terminal, The earth terminal of 21st switch element, the earth terminal of the 22nd switch element, the 23rd switch are single The earth terminal of member, the earth terminal of the 24th switch element, the earth terminal of the 25th switch element, described second Sixteenmo closes the ground connection that the earth terminal of unit, the earth terminal of the 27th switch element, second eighteenmo close unit End, the earth terminal of the 29th switch element, the earth terminal of the 30th switch element and the described 31st are opened The earth terminal for closing unit is connected to ground altogether.

3. chip port impedance matching correcting circuit as claimed in claim 1, it is characterised in that the first resistor matches mould Block includes the first fixed resistance value module and the first resistance value changeable terminals module；

Total resistance of the first resistor matching module is total resistance of the first fixed resistance value module and described first variable Total resistance sum of resistance module, total resistance of the first fixed resistance value module is immutable, in the Digital Logic control When molding block is adjusted to total resistance of the first resistor matching module, the Digital Logic control module is to described Total resistance of one resistance value changeable terminals module is adjusted；

The first fixed resistance value module includes first resistor R1, the 32nd NMOS tube, the 33rd NMOS tube, second resistance R2, the 34th NMOS tube, 3rd resistor R3, the 35th NMOS tube, the 4th resistance R4, the 36th NMOS tube, the 5th electricity Hinder R5, the 37th NMOS tube, the 6th resistance R6, the 38th NMOS tube, the 7th resistance R7, the 39th NMOS tube, the 8th Resistance R8, the 40th NMOS tube, the 9th resistance R9, the 41st NMOS tube, the tenth resistance R10, the 42nd NMOS tube, the tenth One resistance R11, the 43rd NMOS tube, the 12nd resistance R12, the 44th NMOS tube, the 13rd resistance R13 and the 40th Five NMOS tubes；

The first resistance value changeable terminals module includes the 15th resistance R15, the 46th NMOS tube, the 47th NMOS tube, the 4th 18 NMOS tubes, the 49th NMOS tube, the 16th resistance R16, the 50th NMOS tube, the 51st NMOS tube, the 17th electricity Hinder R17, the 52nd NMOS tube, the 18th resistance R18, the 53rd NMOS tube, the 19th resistance R19, the 54th NMOS Pipe, the 20th resistance R20, the 55th NMOS tube, the 21st resistance R21, the 56th NMOS tube, the 22nd resistance R22, the 57th NMOS tube N57, the 23rd resistance R23, the 58th NMOS tube, the 24th resistance R24 and the 5th 19 NMOS tubes；

The first end of the first resistor R1 and the first end of the second resistance R2, the first end of the 3rd resistor R3, institute State the 4th resistance R4 first end, the first end of the 5th resistance R5, the first end of the 6th resistance R6, the 7th electricity Hinder R7 first end, the first end of the 8th resistance R8, the first end of the 9th resistance R9, the tenth resistance R10 First end, the first end of the 11st resistance R11, the first end of the 12nd resistance R12, the 13rd resistance R13 First end, the first end of the 15th resistance R15, the first end of the 16th resistance R16, the 17th resistance R17 first end, the first end of the 18th resistance R18, the first end of the 19th resistance R19, the 20th electricity Hinder R20 first end, the first end of the 21st resistance R21, the first end of the 22nd resistance R22, described the 23 resistance R23 first end and the first end of the 24th resistance R24 connect the common contact to be formed as institute altogether State the reference current access interface of first resistor matching module, the second end connection the described 32nd of the first resistor R1 The drain electrode of NMOS tube, the drain electrode of source electrode connection the 33rd NMOS tube of the 32nd NMOS tube, the described 30th The grid of two NMOS tubes and the grid of the 33rd NMOS tube connect and access the first control level altogether, the second resistance R2 The second end connect the drain electrode of the 34th NMOS tube, grid access first control of the 34th NMOS tube Level, the second end of the 3rd resistor R3 connect the drain electrode of the 35th NMOS tube, the 35th NMOS tube Grid access the first control level, the second end of the 4th resistance R4 connect the drain electrode of the 36th NMOS tube, Grid access the first control level of 36th NMOS tube, the second end connection described the of the 5th resistance R5 The drain electrode of 37 NMOS tubes, grid access the first control level of the 37th NMOS tube, the 6th resistance R6 the second end connects the drain electrode of the 38th NMOS tube, grid access first control of the 38th NMOS tube Level processed, the second end of the 7th resistance R7 connect the drain electrode of the 39th NMOS tube, the 39th NMOS tube Grid access the first control level, the second end of the 8th resistance R8 connects the drain electrode of the 40th NMOS tube, Grid access the first control level of 40th NMOS tube, the second end connection the described 4th of the 9th resistance R9 The drain electrode of 11 NMOS tubes, grid access the first control level of the 41st NMOS tube, the tenth resistance R10 The second end connect the drain electrode of the 42nd NMOS tube, grid access first control of the 42nd NMOS tube Level, the second end of the 11st resistance R11 connect the drain electrode of the 43rd NMOS tube, the 43rd NMOS tube Grid access the first control level, the second end of the 12nd resistance R12 connects the 44th NMOS tube Drain electrode, grid access the first control level of the 44th NMOS tube, the second end of the 13rd resistance R13 connects The drain electrode of the 45th NMOS tube is connect, grid access the first control level of the 45th NMOS tube is described The substrate of 32nd NMOS tube, the substrate of the 33rd NMOS tube and source electrode, the substrate of the 34th NMOS tube With source electrode, the substrate of the 35th NMOS tube and source electrode, the substrate of the 36th NMOS tube and source electrode, the described 3rd The substrate and source electrode of 17 NMOS tubes, the substrate of the 38th NMOS tube and source electrode, the lining of the 39th NMOS tube Bottom and source electrode, the substrate of the 40th NMOS tube and source electrode, the substrate of the 41st NMOS tube and source electrode, the described 4th The substrate and source electrode of 12 NMOS tubes, the substrate of the 43rd NMOS tube and source electrode, the lining of the 44th NMOS tube Bottom and source electrode, the substrate of the 45th NMOS tube and source electrode are connected to ground, the second end connection of the 15th resistance R15 altogether The drain electrode of 46th NMOS tube, the drain electrode of the 47th NMOS tube and source electrode connect the described 46th respectively The drain electrode of the source electrode of NMOS tube and the 48th NMOS tube, the source electrode connection the described 40th of the 48th NMOS tube The drain electrode of nine NMOS tubes, the grid of the 46th NMOS tube and the grid of the 47th NMOS tube, the described 40th The grid of eight NMOS tubes and the grid of the 49th NMOS tube connect and connect the Digital Logic control module altogether, described 16th resistance R16 the second end connects the drain electrode of the 50th NMOS tube, the source electrode connection institute of the 50th NMOS tube The drain electrode of the 51st NMOS tube is stated, the grid of the 50th NMOS tube connects simultaneously altogether with the grid of the 51st NMOS tube The Digital Logic control module is connected, the second end of the 17th resistance R17 connects the leakage of the 52nd NMOS tube Pole, the grid of the 52nd NMOS tube connect the Digital Logic control module, the second end of the 18th resistance R18 The drain electrode of the 53rd NMOS tube is connected, the grid of the 53rd NMOS tube connects the Digital Logic control mould Block, the second end of the 19th resistance R19 connect the drain electrode of the 54th NMOS tube, the 20th resistance R20's Second end connects the drain electrode of the 55th NMOS tube, grid and the 55th NMOS of the 54th NMOS tube The grid of pipe connects and connects the Digital Logic control module altogether, the second end of the 21st resistance R21 connection described the The drain electrode of 56 NMOS tubes, the second end of the 22nd resistance R22 connect the drain electrode of the 57th NMOS tube, institute The second end for stating the 23rd resistance R23 connects the drain electrode of the 58th NMOS tube, and the of the 24th resistance R24 Two ends connect the drain electrode of the 59th NMOS tube, grid and the 57th NMOS tube of the 56th NMOS tube Grid, the grid of the 58th NMOS tube and the grid of the 59th NMOS tube connect altogether and connect the numeral Logic control module, the substrate of the 46th NMOS tube, the substrate of the 47th NMOS tube, the described 48th The substrate of NMOS tube, the substrate of the 49th NMOS tube and source electrode, the substrate of the 50th NMOS tube, the described 50th The substrate and source electrode of one NMOS tube, the substrate of the 52nd NMOS tube and source electrode, the substrate of the 53rd NMOS tube With source electrode, the substrate of the 54th NMOS tube and source electrode, the substrate of the 55th NMOS tube and source electrode, the described 5th The substrate and source electrode of 16 NMOS tubes, the substrate of the 57th NMOS tube and source electrode, the lining of the 58th NMOS tube Bottom and source electrode, the substrate of the 59th NMOS tube and source electrode are connected to ground altogether.

4. chip port impedance matching correcting circuit as claimed in claim 1, it is characterised in that the second resistance matches mould Block includes the second fixed resistance value module and the second resistance value changeable terminals module；

Total resistance of the second resistance matching module is total resistance of the second fixed resistance value module and described second variable Total resistance sum of resistance module, total resistance of the second fixed resistance value module is immutable, in the Digital Logic control When molding block is adjusted to total resistance of the second resistance matching module, the Digital Logic control module is to described Total resistance of two resistance value changeable terminals modules is adjusted；

The second fixed resistance value module includes the 3rd NMOS tube, the 4th NMOS tube, the 25th resistance R25, the 26th electricity Hinder R26, the 27th resistance R27, the 28th resistance R28, the 29th resistance R29, the 30th resistance R30, the 31st Resistance R31 and the 32nd resistance R32；

The second resistance value changeable terminals module includes the first phase inverter, first switch adjustment unit, second switch adjustment unit, the 3rd 13 resistance R33, the 34th resistance R34, the 35th resistance R35, the 36th resistance R36, the second phase inverter, the 3rd open Pass adjustment unit, the 4th switch-mode regulation unit, the 37th resistance R37, the 38th resistance R38, the 3rd phase inverter, the 5th open Close adjustment unit, the 6th switch-mode regulation unit, the 39th resistance R39, the 4th phase inverter, the 7th switch-mode regulation unit, the 8th Switch-mode regulation unit, the 40th resistance R40, the 41st resistance R41, the 5th phase inverter, the 9th switch-mode regulation unit, the tenth open Close adjustment unit, the 42nd resistance R42, the 43rd resistance R43, the 44th resistance R44, the 45th resistance R45, the Hex inverter, the 11st switch-mode regulation unit, the 12nd switch-mode regulation unit, the 46th resistance R46, the 47th resistance R47, the 48th resistance R48, the 49th resistance R49, the 50th resistance R50, the 51st resistance R51, the 52nd electricity Hinder R52 and the 53rd resistance R53；

The grid of 3rd NMOS tube and grid access the second control level of the 4th NMOS tube, the 25th electricity Hinder R25 first end and the 26th resistance R26 first end, the first end of the 27th resistance R27, described the 28 resistance R28 first end, the first end of the 29th resistance R29, the first end of the 30th resistance R30, The first end of the 31st resistance R31 and the first end of the 32nd resistance R32 connect the common contact to be formed altogether The drain electrode of the 3rd NMOS tube and the drain electrode of the 4th NMOS tube, the input of first phase inverter, institute are connected simultaneously State the input of the second phase inverter, input of the 3rd phase inverter, the input of the 4th phase inverter, the described 5th anti- The input of the input of phase device and the hex inverter is all connected with the Digital Logic control module, the first switch The controlled end of adjustment unit and the controlled end of the second switch adjustment unit are connected to the output end of first phase inverter, institute altogether State the first input end of first switch adjustment unit and the first input end of the second switch adjustment unit connect respectively it is described The grid of the grid of 3rd NMOS tube and the 4th NMOS tube, the first end and the described 3rd of the 33rd resistance R33 The first of the first end of 14 resistance R34s, the first end of the 35th resistance R35 and the 36th resistance R36 The common contact at end simultaneously with the second input of the first switch adjustment unit and the second switch adjustment unit second Input connects；The controlled end of the 3rd switch-mode regulation unit is connected to institute altogether with the controlled end of the 4th switch-mode regulation unit State the output end of the second phase inverter, the first input end of the 3rd switch-mode regulation unit and the 4th switch-mode regulation unit First input end connects the grid of the 3rd NMOS tube and the grid of the 4th NMOS tube, the 37th resistance respectively The common contact of R37 first end and the 38th resistance R38 first end simultaneously with the 3rd switch-mode regulation unit Second input connects with the second input of the 4th switch-mode regulation unit；The controlled end of the 5th switch-mode regulation unit It is connected to the output end of the 3rd phase inverter, the 5th switch-mode regulation list altogether with the controlled end of the 6th switch-mode regulation unit The first input end of member and the first input end of the 6th switch-mode regulation unit connect the grid of the 3rd NMOS tube respectively With the grid of the 4th NMOS tube, the first end of the 39th resistance R39 simultaneously with the 5th switch-mode regulation unit The second input connected with the second input of the 6th switch-mode regulation unit；The 7th switch-mode regulation unit it is controlled The controlled end of end and the 8th switch-mode regulation unit is connected to the output end of the 4th phase inverter, the 7th switch-mode regulation altogether The first input end of the first input end of unit and the 8th switch-mode regulation unit connects the grid of the 3rd NMOS tube respectively Pole and the grid of the 4th NMOS tube, the first end of the 40th resistance R40 simultaneously with the 7th switch-mode regulation unit The second input connected with the second input of the 8th switch-mode regulation unit, the second end of the 40th resistance R40 Connect the first end of the 41st resistance R41；The controlled end of the 9th switch-mode regulation unit is adjusted with the described tenth switch The controlled end of section unit is connected to the output end of the 5th phase inverter altogether, the first input end of the 9th switch-mode regulation unit and The first input end of the tenth switch-mode regulation unit connects the grid of the 3rd NMOS tube and the 4th NMOS tube respectively Grid, the first end of the 42nd resistance R42 the second input with the 9th switch-mode regulation unit and institute simultaneously The second input connection of the tenth switch-mode regulation unit is stated, the 43rd resistance R43 is connected to the 42nd resistance Between R42 the second end and the 44th resistance R44 first end, the second end connection of the 44th resistance R44 The first end of the 45th resistance R45；The controlled end of the 11st switch-mode regulation unit is adjusted with the described 12nd switch The controlled end of section unit is connected to the output end of the hex inverter, the first input end of the 11st switch-mode regulation unit altogether Connect the grid and the described 4th of the 3rd NMOS tube respectively with the first input end of the 12nd switch-mode regulation unit The grid of NMOS tube, the first end of the 46th resistance R46 are simultaneously defeated with the second of the 11st switch-mode regulation unit Enter end to connect with the second input of the 12nd switch-mode regulation unit, the 47th resistance R47 is connected to described the Between 46 resistance R46 the second end and the 48th resistance R48 first end, the 48th resistance R48's Second end connects the first end of the 49th resistance R49, and the 50th resistance R50 is connected to the 49th resistance Between R49 the second end and the 51st resistance R51 first end, the 52nd resistance R52 is connected to described Between 51 resistance R51 the second end and the 53rd resistance R53 first end；The 25th resistance R25's Second end and the second end of the 26th resistance R26, the second end of the 27th resistance R27, the described 28th Resistance R28 the second end, the second end of the 29th resistance R29, the second end of the 30th resistance R30, described 31 resistance R31 the second end and the second end of the 32nd resistance R32 connect the common contact to be formed, described altogether 33 resistance R33 the second end and the second end of the 34th resistance R34, the second of the 35th resistance R35 The second end and described the of end and the 36th resistance the R36 common contact at the second end, the 37th resistance R37 The common contact at 38 resistance R38 the second end, the second end of the 39th resistance R39, the 41st resistance R41 The second end, the second end of the 45th resistance R45 and the second end of the 53rd resistance R53 connect to be formed altogether Reference current access interface of the common contact as the second resistance matching module；The substrate of 3rd NMOS tube and source Pole, the substrate of the 4th NMOS tube and source electrode, the earth terminal of the first switch adjustment unit, second switch regulation are single Member output end, the output end of the 3rd switch-mode regulation unit, the output end of the 4th switch-mode regulation unit, the described 5th The output of the output end of switch-mode regulation unit, the output end, the 7th switch-mode regulation unit of the 6th switch-mode regulation unit End, the output end of the 8th switch-mode regulation unit, the output end of the 9th switch-mode regulation unit, the tenth switch-mode regulation The output end of the output end of unit, the output end of the 11st switch-mode regulation unit and the 12nd switch-mode regulation unit It is connected to ground altogether.

5. chip port impedance matching correcting circuit as claimed in claim 4, it is characterised in that the first switch regulation is single First and described second switch adjustment unit is structure identical switch-mode regulation unit, and the switch-mode regulation unit includes the 30th PMOS, the 56th NMOS tube, the 57th NMOS tube, the 58th NMOS tube, the 59th NMOS tube and the 60th NMOS tube；

The common contact of the grid of 30th PMOS and the grid of the 56th NMOS tube is as the switch-mode regulation The controlled end of unit, the drain electrode of the 30th PMOS and the common contact of substrate are first defeated as the switch-mode regulation unit Enter end, the source electrode of the 30th PMOS is connected to the 57th NMOS tube altogether with the drain electrode of the 56th NMOS tube Grid, the grid and the grid of the 59th NMOS tube and the grid of the 60th NMOS tube of the 58th NMOS tube The grid of the 57th NMOS tube is extremely connected to altogether, and the drain electrode of the 57th NMOS tube is as the switch-mode regulation unit The second input, the draining of the 58th NMOS tube, the drain electrode and the described 60th of the 59th NMOS tube The drain electrode of NMOS tube is connected to the drain electrode of the 57th NMOS tube, source electrode and substrate, the institute of the 56th NMOS tube altogether State the source electrode and substrate, the source electrode of the 58th NMOS tube and substrate, the 59th NMOS of the 57th NMOS tube The source electrode of pipe connects the common contact to be formed as the switch altogether with substrate and the source electrode of the 60th NMOS tube with substrate The output end of adjustment unit；

The 3rd switch-mode regulation unit and the 4th switch-mode regulation unit are structure identical switch-mode regulation unit, described to open Closing adjustment unit includes the 38th PMOS, the 61st NMOS tube, the 62nd NMOS tube and the 63rd NMOS tube；

The common contact of the grid of 38th PMOS and the grid of the 61st NMOS tube is adjusted as the switch Save the controlled end of unit, the drain electrode of the 38th PMOS and the common contact of substrate as the switch-mode regulation unit the One input, the source electrode of the 38th PMOS and the drain electrode and the described 63rd of the 61st NMOS tube The grid of NMOS tube is connected to the grid of the 62nd NMOS tube, the drain electrode and the described 6th of the 62nd NMOS tube altogether Second input of the common contact of the drain electrode of 13 NMOS tubes as the switch-mode regulation unit, the 61st NMOS tube Source electrode is total to substrate, the source electrode of the 62nd NMOS tube and the source electrode and substrate of substrate and the 63rd NMOS tube Connect output end of the common contact to be formed as switch-mode regulation unit；

The 5th switch-mode regulation unit and the 6th switch-mode regulation unit are structure identical switch-mode regulation unit, described to open Closing adjustment unit includes the 39th PMOS, the 64th NMOS tube and the 65th NMOS tube；39th PMOS Controlled end of the common contact of the grid of the grid of pipe and the 64th NMOS tube as the switch-mode regulation unit, described the First input end of the drain electrode as the switch-mode regulation unit of 39 PMOSs, the source electrode of the 39th PMOS and The drain electrode of 64th NMOS tube is connected to the grid of the 65th NMOS tube, the leakage of the 65th NMOS tube altogether Second input of the pole as the switch-mode regulation unit, substrate, the 64th NMOS of the 39th PMOS The substrate and source electrode of the substrate and source electrode of pipe and the 65th NMOS tube connect the common contact to be formed and adjusted as switch altogether Save the output end of unit.

6. chip port impedance matching correcting circuit as claimed in claim 4, it is characterised in that the 7th switch-mode regulation list First and described 8th switch-mode regulation unit is structure identical switch-mode regulation unit, and the switch-mode regulation unit includes the 31st PMOS, the 7th NMOS tube, the 8th NMOS tube and the 9th NMOS tube；The grid and the described 7th of 31st PMOS Controlled end of the common contact of the grid of NMOS tube as the switch-mode regulation unit, the drain electrode conduct of the 31st PMOS The first input end of the switch-mode regulation unit, the source electrode of the 31st PMOS and the drain electrode of the 7th NMOS tube Contact connects the common contact of the grid of the 8th NMOS tube and the grid of the 9th NMOS tube altogether, the 8th NMOS tube The second input to drain as the switch-mode regulation unit, the source electrode of the 8th NMOS tube connect the 9th NMOS tube Drain electrode, the substrate of the 31st PMOS, the substrate of the 7th NMOS tube and source electrode, the substrate of the 8th NMOS tube And the substrate and source electrode of the 9th NMOS tube connect output end of the common contact to be formed as the switch-mode regulation unit altogether.

7. chip port impedance matching correcting circuit as claimed in claim 4, it is characterised in that the 9th switch-mode regulation unit and Tenth switch-mode regulation unit is structure identical switch-mode regulation unit, the switch-mode regulation unit include the 32nd PMOS, Tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube and the 14th NMOS tube；Described 30th First input end of the drain electrode as the switch-mode regulation unit of two PMOSs, the source electrode of the 32nd PMOS with it is described The common contact of the drain electrode of tenth NMOS tube connects the grid of the 11st NMOS tube and the grid of the 12nd NMOS tube, institute State the common contact of the grid of the 13rd NMOS tube and the grid of the 14th NMOS tube, the drain electrode of the 11st NMOS tube As the second input of the switch-mode regulation unit, the drain electrode of the 12nd NMOS tube and source electrode connect the described tenth respectively The drain electrode of the source electrode of one NMOS tube and the 13rd NMOS tube, the source electrode connection the described 14th of the 13rd NMOS tube The drain electrode of NMOS tube, the substrate of the 32nd PMOS, the substrate of the tenth NMOS tube and source electrode, the described 11st The substrate of NMOS tube, the substrate of the 12nd NMOS tube, the substrate of the 13rd NMOS tube and the 14th NMOS The substrate and source electrode of pipe connect output end of the common contact to be formed as the switch-mode regulation unit altogether.

8. chip port impedance matching correcting circuit as claimed in claim 4, it is characterised in that the 11st switch-mode regulation Unit and the 12nd switch-mode regulation unit are structure identical switch-mode regulation unit, and the switch-mode regulation unit includes the 3rd 13 PMOSs, the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube, the 18th NMOS tube, the 19th NMOS tube, 20th NMOS tube, the 21st NMOS tube, the 22nd NMOS tube and the 23rd NMOS tube；

The common contact of the grid of 33rd PMOS and the grid of the 15th NMOS tube is as the switch-mode regulation The controlled end of unit, first input end of the drain electrode as the switch-mode regulation unit of the 33rd PMOS, described the The source electrodes of 33 PMOSs connects the drain electrode of the 15th NMOS tube, the grid of the 33rd PMOS and described the The common contact of the grid of 15 NMOS tubes connects the grid of the 16th NMOS tube and the grid of the 17th NMOS tube, institute State the grid of the 18th NMOS tube, the grid of the 19th NMOS tube, the grid of the 20th NMOS tube, the described 20th The grid of the grid of one NMOS tube, the grid of the 22nd NMOS tube and the 23rd NMOS tube connects to be formed altogether Common contact, second input of the drain electrode as the switch-mode regulation unit of the 16th NMOS tube, the described 17th The drain electrode of NMOS tube and source electrode connect the source electrode of the 16th NMOS tube and the drain electrode of the 18th NMOS tube respectively, described The drain electrode of 19th NMOS tube and source electrode connect the source electrode of the 18th NMOS tube and the leakage of the 20th NMOS tube respectively Pole, the drain electrode of the 21st NMOS tube and source electrode connect the source electrode and the described 22nd of the 20th NMOS tube respectively The drain electrode of NMOS tube, the drain electrode of source electrode connection the 23rd NMOS tube of the 22nd NMOS tube, the described 30th The substrate of three PMOSs, the substrate of the 15th NMOS tube and source electrode, the substrate of the 16th NMOS tube, the described 17th The substrate of NMOS tube, the substrate of the 18th NMOS tube, the substrate of the 19th NMOS tube, the 20th NMOS tube Substrate, the substrate of the 21st NMOS tube, the substrate of the 22nd NMOS tube and the 23rd NMOS tube Substrate and source electrode connect output end of the common contact to be formed as the switch-mode regulation unit altogether.

9. chip port impedance matching correcting circuit as claimed in claim 1, it is characterised in that the resistance comparison module bag Include：

24th NMOS tube, the 25th NMOS tube, the 26th NMOS tube, the 27th NMOS tube, the 28th NMOS Pipe, the 29th NMOS tube, the 30th NMOS tube, the 31st NMOS tube, the 34th PMOS, the 35th PMOS, 36th PMOS, the 37th PMOS, the 54th resistance, the 55th resistance, the 56th resistance R, the 50th Seven resistance, the 58th resistance, the 59th resistance, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and level conversion Circuit；

The grid of 24th NMOS tube and the grid of the 31st NMOS tube connect altogether, and from the Digital Logic control Molding block receives first comparison control signal or second comparison control signal, the source electrode of the 24th NMOS tube It is connected to the grid of the 27th NMOS tube, the 54th resistance altogether with the first end of the 54th resistance R54 R54 the second end connects the first end of the second electric capacity C2, the first end and the described 50th of the 56th resistance R56 Seven resistance R57 first end is connected to the drain electrode of the 24th NMOS tube altogether, and the 55th resistance R55 is connected to described Between the source electrode of 34th PMOS and the 56th resistance R56 the second end, the of the 57th resistance R57 Two ends, the drain and gate of the 25th NMOS tube, the grid and the described 29th of the 28th NMOS tube The grid of NMOS tube connects altogether, drain electrode and the draining of the 35th PMOS, the described 3rd of the 34th PMOS The drain electrode of 16 PMOSs and the drain electrode of the 37th PMOS are connected to the drain electrode of the 30th NMOS tube altogether, described The source electrode and grid of 35th PMOS are connected to the grid of the 36th PMOS altogether, the 26th NMOS tube Drain electrode connects the source electrode of the 35th PMOS, drain electrode and the 37th PMOS of the 27th NMOS tube Grid be connected to the source electrodes of the 36th PMOS pipes, the source electrode and the described 27th of the 26th NMOS tube altogether The source electrode of NMOS tube is connected to the drain electrode of the 28th NMOS tube, the second end and the described 20th of the second electric capacity C2 altogether The source electrode of the source electrode of five NMOS tubes, the source electrode of the 28th NMOS tube and the 29th NMOS tube is connected to ground altogether, The draining of the source electrode of 37th PMOS and the 29th NMOS tube, the source electrode of the 30th NMOS tube and The drain electrode of 31st NMOS tube is connected to the input of the level shifting circuit, the output of the level shifting circuit altogether End connects the Digital Logic control module, the source electrode of the 31st NMOS tube and the grid of the 26th NMOS tube The first end of the 58th resistance R58 is connected to altogether, and the second end of the 58th resistance R58 connects the 3rd electric capacity C3 first end, the second end of the 3rd electric capacity C3 and the first electric capacity C1 first end are connected to the 59th electricity altogether R59 first end is hindered, the second end of the first electric capacity C1 is grounded, described in the second end connection of the 59th resistance R59 The resistance access current input terminal of switch module, the reference current access interface of the first resistor matching module and described the The reference current access interface of two resistors match modules.

10. a kind of chip, including resistance access switch module, the resistance access switch module connection non-essential resistance, the electricity Resistance access switch module is used to control the annexation between the non-essential resistance and the chip；Characterized in that, the core Piece also includes the chip port impedance matching correcting circuit as described in claim any one of 1-9.