CN104715723B - Display device and its image element circuit and driving method - Google Patents

Abstract

A pixel circuit, comprising: a driving transistor and a light-emitting element connected in series between a first level end and a second level end, the first electrode of the driving transistor is connected to the first end of the light-emitting element, and the control electrode of the driving transistor A second transistor and a storage capacitor are connected between the conducting electrode and a conducting electrode. In the initialization phase, the second transistor is turned on, and the potential at both ends of the storage capacitor and the potential of the control electrode of the driving transistor are respectively initialized; in the threshold compensation phase, the threshold voltage of the driving transistor is read and stored in The storage capacitor realizes compensation for the threshold voltage of the drive transistor, and then compensates for the non-uniformity displayed by the pixel circuit.

Description

Display device, pixel circuit and driving method thereof

technical field

The present application relates to the field of display devices, in particular to a display device, a pixel circuit and a driving method thereof.

Background technique

Due to the advantages of high brightness, high luminous efficiency, wide viewing angle and low power consumption, Organic Light-Emitting Diode (OLED) display has been extensively studied in recent years and has been rapidly applied to a new generation of displays. The OLED display can be driven in two ways: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED). Although the cost of passive matrix driving is low, it cannot realize high-resolution display due to crosstalk phenomenon, and the passive matrix driving current is large, which reduces the service life of OLED. In contrast, the active matrix driving method sets a different number of transistors on each pixel as a current source, which avoids crosstalk, requires less driving current, and lower power consumption, which increases the life of the OLED and can achieve High-resolution display, at the same time, the active matrix drive is easier to meet the needs of large-area and high-gray-level display.

The pixel circuit of a traditional AMOLED is a simple two-thin film transistor (Thin Film Transistor, TFT) structure. Although this circuit has a simple structure, it cannot compensate the drift of the driving transistor T1 and the OLED threshold voltage or because the TFT device is made of polycrystalline materials. This results in non-uniform threshold voltages of TFT devices across the panel. When the threshold voltage of the driving transistor T1 and the threshold voltage of the OLED drift or the values on the panel are inconsistent, the driving current I _DS will change, and different pixels on the panel have different drifts due to different bias voltages, so It will cause the unevenness of the panel display.

Contents of the invention

The present application provides a display device, a pixel circuit and a driving method thereof, so as to compensate the non-uniformity of the threshold voltage or threshold voltage drift of a driving transistor.

According to the first aspect, a pixel circuit is provided in an embodiment, including:

It is used to connect the driving transistor and the light emitting element in series between the first level end and the second level end, as well as the second transistor, the third transistor and the storage capacitor; the first pole of the driving transistor is connected to the first end of the light emitting element to form the first Three nodes, the second pole of the driving transistor and the second terminal of the light-emitting element are respectively used to connect to the first level terminal and the second level terminal; the control pole of the driving transistor is connected to the first pole of the second transistor to form a first node, The second pole of the second transistor is connected to the first pole of the third transistor to form a second node, the control pole of the second transistor is used to input the light-emitting control signal; the second pole of the third transistor is used to connect to the Or the data line of the reference potential, the control electrode of the third transistor is used to input the scan signal; the storage capacitor is connected between the second node and the third node.

According to the second aspect, a pixel circuit is provided in an embodiment, including:

The driving transistor and the light emitting element, as well as the second transistor, the third transistor, the fourth transistor, the fifth transistor and the storage capacitor, which are connected in series between the first level end and the second level end; the first pole of the driving transistor is connected to The first end of the light-emitting element forms a third node, the second pole of the driving transistor and the second end of the light-emitting element are respectively used to connect to the first level end and the second level end; the control electrode of the driving transistor is connected to the second transistor The first pole forms the first node, the second pole of the second transistor is connected to the first pole of the third transistor to form the second node, the control pole of the second transistor is used for inputting the light-emitting control signal; the second pole of the third transistor is used for Connected to the data line for providing data signals, the control pole of the third transistor is used to input the scan signal; the first pole of the fifth transistor is connected to the first node, and the second pole of the fifth transistor is used to input the reference potential, The control pole of the fifth transistor is connected to the control pole of the third transistor; the first pole of the fourth transistor is connected to the third node, the second pole of the fourth transistor is used for inputting the initialization potential, and the control pole of the fourth transistor is used for inputting Initialize the control signal; the storage capacitor is connected between the second node and the third node.

According to a third aspect, an embodiment provides a display device, including:

A pixel circuit matrix, the pixel circuit matrix includes the above-mentioned pixel circuits arranged in a matrix of n rows and m columns, wherein n and m are integers greater than 0; a gate drive circuit is used to generate a scan pulse signal, and pass the The scan lines formed in one direction provide required control signals to the pixel circuits; the data drive circuit is used to generate data voltage signals representing grayscale information, and provide data signals to the pixel circuits through the data lines formed along the second direction ; The controller is used to provide control timing to the gate drive circuit and the data drive circuit.

According to the fourth aspect, an embodiment provides a pixel circuit driving method, each driving cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase and a light emitting phase, and the driving method includes:

In the initialization phase, the second transistor is turned on to respectively initialize the potential at both ends of the storage capacitor and the potential of the control electrode of the driving transistor; in the threshold compensation phase, the third transistor and/or the fifth transistor are turned on to provide a reference potential to the control electrode of the driving transistor , read the threshold voltage information of the drive transistor and store it through the storage capacitor; in the data writing phase, the third transistor is turned on to transmit the data voltage and stored in the storage capacitor; in the light-emitting phase, the first transistor is driven according to the voltage difference across the storage capacitor A driving current is generated to drive the light-emitting element to emit light.

According to the pixel circuit of the above-mentioned embodiment, by connecting the second transistor and the storage capacitor between the control electrode and the first electrode of the driving transistor, and cooperating with timing control, the threshold value of the driving transistor is read by providing a reference potential to the driving transistor control electrode The voltage is stored in the storage capacitor, thereby realizing the compensation for the threshold voltage of the driving transistor, and then compensating for the non-uniformity displayed by the pixel circuit.

Description of drawings

Fig. 1a is a structural diagram of a pixel circuit disclosed in Embodiment 1;

Fig. 1b is a structural diagram of another pixel circuit disclosed in Embodiment 1;

FIG. 2 is a driving sequence diagram of a pixel circuit disclosed in Embodiment 1;

Fig. 3a is a structural diagram of a pixel circuit disclosed in Embodiment 2;

Fig. 3b is another pixel circuit structure diagram disclosed in Embodiment 2;

FIG. 4 is a driving sequence diagram of a pixel circuit disclosed in Embodiment 2;

Figure 5a is a scheme for providing initialization potential deformation disclosed in Embodiment 2;

Figure 5b is another scheme for providing initialization potential deformation disclosed in Embodiment 2;

Fig. 6a is a structural diagram of a pixel circuit disclosed in Embodiment 3;

Fig. 6b is another pixel circuit structure diagram disclosed in the third embodiment;

FIG. 7 is a driving sequence diagram of a pixel circuit disclosed in Embodiment 3;

Fig. 8a is a structural diagram of a pixel circuit disclosed in Embodiment 4;

Fig. 8b is another pixel circuit structure diagram disclosed in Embodiment 4;

FIG. 9 is a driving sequence diagram of a pixel circuit disclosed in Embodiment 4;

Fig. 10a is a structural diagram of a pixel circuit disclosed in Embodiment 5;

Fig. 10b is another pixel circuit structure diagram disclosed in Embodiment 5;

FIG. 11 is a driving sequence diagram of a pixel circuit disclosed in Embodiment 5;

FIG. 12 is a structural principle diagram of a display device disclosed in the sixth embodiment.

detailed description

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

First, some terms are explained: the transistor in this application may be a transistor of any structure, such as a bipolar junction transistor (BJT) or a field effect transistor (FET). When the transistor is a bipolar transistor, its control pole refers to the base of the bipolar transistor, the first pole can be the collector or emitter of the bipolar transistor, and the corresponding second pole can be the base of the bipolar transistor. Emitter or collector, in the actual application process, "emitter" and "collector" can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first One pole can be the drain or source of the field effect transistor, and the corresponding second pole can be the source or drain of the field effect transistor. In the actual application process, the "source" and "drain" can be based on the signal flow direction And swap. The transistors in displays are usually a type of field-effect transistor: a thin-film transistor (TFT). In the following, the present application will be described in detail by taking the transistor as a field effect transistor as an example. In other embodiments, the transistor may also be a bipolar transistor.

The light-emitting element is an organic light-emitting diode (Organic Light-Emitting Diode, OLED), and in other embodiments, it may also be other light-emitting elements. The first end of the light emitting element can be a cathode or an anode, and correspondingly, the second end of the light emitting element is an anode or a cathode. Those skilled in the art should understand that: the current should flow from the anode to the cathode of the light-emitting element, therefore, based on the flow direction of the current, the anode and the cathode of the light-emitting element can be determined.

The effective level can be high level or low level, which can be replaced adaptively according to the function realization of specific components.

The first level end and the second level end are two ends of the power supply provided for the operation of the pixel circuit. In one embodiment, the first level terminal may be the high level terminal V _DD , and the second level terminal may be the low level terminal V _SS or the ground line, and in other embodiments, an adaptive replacement may also be made. It should be noted that: for the pixel circuit, the first level terminal (such as the high level terminal V _DD ) and the second level terminal (such as the low level terminal V _SS ) are not part of the pixel circuit of this application, in order to make those skilled in the art To better understand the technical solution of the present application, the first level terminal and the second level terminal are introduced in particular for description.

It should be noted that, for the convenience of description and to enable those skilled in the art to understand the technical solution of the present application more clearly, the relevant parts of the circuit structure of the first node A, the second node B and the third node C are introduced in this application document marked, it cannot be identified as an additional terminal introduced in the circuit.

For the convenience of description, the high level is characterized by V _H , and the low level is characterized by V _L.

Embodiment one:

Please refer to FIG. 1a and FIG. 1b, which are a structural diagram of a pixel circuit disclosed in this embodiment, including: a drive transistor T1 and a light emitting element OLED used to be connected in series between the first level terminal VDD and the second level terminal VSS, and The second transistor T2, the third transistor T3 and the storage capacitor C1. Wherein, in the pixel circuit shown in FIG. 1a, each transistor (driving transistor T1, second transistor T2 and third transistor T3) is an N-type thin film transistor; in the pixel circuit shown in FIG. 1b, each transistor (driving transistor T1, The second transistor T2 and the third transistor T3) are P-type thin film transistors.

The first pole of the driving transistor T1 is connected to the first end of the light-emitting element OLED to form a third node C, and the second pole of the driving transistor T1 and the second end of the light-emitting element OLED are respectively used to connect to the first level terminal VDD and the second Level terminal VSS. In one embodiment, please refer to FIG. 1a, the first terminal of the light-emitting element OLED is an anode, and the second terminal of the light-emitting element OLED is a cathode; the second electrode of the driving transistor T1 is used to connect to the first level terminal VDD to emit light The second terminal of the OLED is used to be connected to the second level terminal VSS. In another embodiment, please refer to FIG. 1b, the first end of the light emitting element OLED is a cathode, the second end of the light emitting element OLED is an anode; the second pole of the driving transistor T1 is used to connect to the second level terminal VSS, The second end of the light emitting element OLED is used to be connected to the first level end VDD.

The control electrode of the driving transistor T1 is connected to the first electrode of the second transistor T2 to form a first node A, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3 to form a second node B, and the second transistor T2 The control pole of is used to input the light-emitting control signal V _EM .

The second pole of the third transistor T3 is used to connect to the data line DATA. In a specific embodiment, the data line DATA is used to provide the data signal V _DATA or the reference potential V _REF . In other embodiments, the data line DATA can also be used The initialization potential is provided to initialize the potential of each node; the control electrode of the third transistor T3 is used for inputting the scan signal V _Scan .

The storage capacitor C1 is connected between the second node B and the third node C.

In a specific embodiment, the pixel circuit works sequentially in the first stage, the second stage and the third stage. In this embodiment, the first stage may sequentially include an initialization stage and a threshold compensation stage, the second stage is a data writing stage, and the third stage is a light emitting stage.

In the first stage, the second transistor T2 and the third transistor T3 are respectively turned on in response to the first active level of the light emission control signal V _EM and the first active level of the scanning signal V _Scan , and supply voltage to the first node A and the second node B. transmit the reference potential V _REF to initialize the potentials of the first node A and the second node B, and provide an initialization potential to the third node C through a corresponding signal source to initialize the potential of the third node C. In this embodiment, the third The initialization potential of the node C is provided by the first level terminal VDD through the turned-on driving transistor T1, and the threshold voltage V _TH of the driving transistor T1 is read. In one embodiment, please refer to FIG. 1a, in the initialization phase, the second pole of the driving transistor T1 transmits the initialization potential (for example, low level) provided by the first level terminal VDD to initialize the potential of the third node C; stage, the second pole of the drive transistor T1 transmits the active level (for example, high level) of the first level terminal VDD, and then the potential of the third node C changes (for example, rises), until the potential of the node is the same as that of the drive transistor T1 When the difference between the control pole of the drive transistor T1 is the threshold voltage of the drive transistor T1, the storage capacitor C1 is obtained according to the potential of the control pole of the drive transistor T1 (that is, the second node B or the first node A) and the voltage difference between the third node C Threshold voltage V _TH of drive transistor T1. In another embodiment, please refer to FIG. 1b. In the initialization phase, the initialization potential of the third node C is provided by the second level terminal VSS, that is, the second pole of the driving transistor T1 transmits the initialization potential provided by the second level terminal VSS. (eg high level) to initialize the potential of the third node C; in the threshold compensation stage, the second pole of the drive transistor T1 transmits the active level (eg low level) of the second level terminal VSS, so the third node C The potential changes (for example, drops), until the potential of this node is different from the control electrode of the driving transistor T1 by the threshold voltage of the driving transistor T1, the storage capacitor C1 is based on the control electrode of the driving transistor T1 (that is, the second node B or the first node The voltage difference between the potential of A) and the third node C obtains the threshold voltage V _TH of the driving transistor T1.

In the second stage, the second transistor T2 is controlled by the light emission control signal V _EM to be in an off state, and the third transistor T3 is turned on to transmit the data signal V _DATA to the second node B in response to the second active level of the scanning signal V _Scan ;

In the third stage, the third transistor T3 is controlled by the scan signal V _Scan to be in an off state, the second transistor T2 is turned on in response to the second active level of the light emission control signal V _EM , and the drive transistor T1 is turned on in response to the potential of the first node A Drive the light-emitting element OLED to emit light.

It should be noted that, in one embodiment, please _refer to _FIG . _An effective level and a second effective level) are both high levels; in another embodiment, please refer to FIG. ) and the active level of the scan signal V _Scan (including the first active level and the second active level) are both low level.

In this embodiment, the second active level of the scanning signal V _Scan lags behind the first active level of the scanning signal V _Scan and the first active level of the light emission control signal V _EM , and the second active level of the light emission control signal V _EM The active level lags behind the second active level of the scan signal V _Scan .

The driving process of the pixel circuit disclosed in this embodiment will be described below by taking FIG. 1a as an example. The driving process of the pixel circuit in this embodiment is divided into an initialization stage, a threshold compensation stage, a data writing stage, and a light-emitting stage. Figure 2 shows the signal timing of this embodiment, and the details of this embodiment are described in conjunction with Figure 2 and Figure 1a drive process.

In the initialization stage: the scanning signal V _Scan provided to the third transistor T3 is at a high level V _H , that is, the first active level; the light emission control signal V _EM is at a high level V _H , that is, the first active level. Thus, the third transistor T3 and the second transistor T2 are turned on. The data line DATA transmits the reference potential V _REF to the third transistor T3, and the reference potential V _REF is input to the first node A through the turned-on transistors T3 and T2, so that the potential of the first node A is V _REF , since the first node A It is connected with the second node B through the second transistor T2, so the voltages of the two nodes are the same. At the same time, the drive transistor T1 is in the conduction state, and the first level terminal VDD outputs an initialization potential low-level signal V _L , and the level signal is input to the third node C through the switching transistor T1, so that the third node C is electrically level to V _L . Thus, the potential initialization of the first node A, the second node B, and the third node C is completed.

In the threshold compensation stage: the scan signal V _Scan and the light emission control signal V _EM continue to maintain the first active level, high level V _H , and the data line DATA still transmits the reference potential V _REF . The signal provided by the first level terminal VDD changes from the low level V _L back to the high level V _H , and charges the third node C through the driving transistor T1 . Therefore, the potential of the third node C will rise slowly until the node rises to V _REF -V _TH , the driving transistor T1 will enter the cut-off state, and the potential of the third node C will remain at V _REF -V _TH . Where V _TH is the threshold voltage of the driving transistor T1. After the threshold compensation phase ends, the threshold voltage information of the driving transistor T1 is stored on the node C through the storage capacitor C1. It should be noted that V _REF -V _TH is smaller than the threshold voltage of the light emitting element OLED.

Data writing stage: the luminescence control signal V _EM becomes low level, and the scanning signal V _Scan becomes the second active level, such as high level V _H . At this time, the second transistor T2 is in the off state, the third transistor T3 is in the on state, the data line DATA provides the data voltage V _DATA and writes it into the second node B through the on third transistor T3. It should be noted that, in other embodiments, when there are multiple rows of pixel circuits and the method of emitting light at the same time is adopted, at this stage, the second active level of the scanning signal V _Scan of each row arrives sequentially to complete the second active level row by row. The data voltage V _DATA of node B is written. When the potential of the second node B is charged from V _REF to V _DATA , the data voltage V _DATA will be coupled to the node C through the coupling effect of the storage capacitor C1 and the intrinsic capacitance C2 of the light-emitting element OLED, so that the node C The potential change is:

Wherein, VnodeC represents the potential of the third node C, and C1 and C2 are the capacitance values of the storage capacitor C1 and the intrinsic capacitance of the light emitting element OLED respectively.

Light-emitting stage: the second active level of the light-emitting control signal V _EM , such as a high level V _H , arrives, and the scanning signal V _Scan maintains a low level. At this time, the second transistor T2 is in the conduction state, the light emitting element OLED starts to emit light, and the potential of the third node C also becomes V _OLED . V _OLED is the potential of the anode of the light-emitting element OLED when it emits light. At this time, since the second node B and the first node A are coupled through the second transistor T2, the potentials of the two nodes are the same, and the node A (B) becomes:

From (1-2), it can be concluded that the current flowing through the light-emitting element OLED during the light-emitting phase is:

Wherein, μ _n , C _ox , W and L are the effective mobility, the gate capacitance per unit area, the channel width and the channel length of the driving transistor T1 respectively. It can be seen from (1-3) that the current flowing through the light-emitting element OLED has nothing to do with the threshold voltage of the drive transistor T1 and the threshold voltage of the OLED itself, so the pixel circuit in this example can well compensate for the unevenness of the display .

It should be noted that, in other embodiments, when there are multiple rows of pixel circuits and the method of emitting light at the same time is adopted, after the writing of the data voltage V _DATA of the second node B of each row is completed, the light emission control signal V _EM second effective level before arriving.

The advantage of this embodiment is that the circuit structure is simple, with only three transistors and one storage capacitor, which can increase the pixel aperture ratio, reduce the current density of the light-emitting element OLED, and improve the service life of the light-emitting element OLED; the circuit adopts a charging threshold value extraction The method, that is, the source follower structure, has a compensation effect on both positive and negative thresholds, so this method is also effective for depletion-type transistors; and, in other embodiments, when the circuit adopts the driving mode of simultaneous light emission, the In 3D display, the influence of crosstalk can be effectively avoided. In addition, in the process of initialization and threshold value compensation, the circuit inputs a low level at the anode of the light-emitting element OLED, which can effectively prolong the service life of the light-emitting element OLED.

It should be noted that when the transistors use P-type thin film transistors, please refer to Figure 1b, the driving process is the same as that of Figure 1a, the difference is that the active level of each transistor is the low level V _L ; In the initialization phase, the second level terminal VSS provides a high level, and charges the third node C (cathode of the light-emitting element OLED) to a high level.

Embodiment two:

In Embodiment 1, the initialization potential of the third node C is provided through the first level terminal VDD or the second level terminal VSS. The difference between this embodiment and the above-mentioned embodiment is that the pixel circuit disclosed in this embodiment also includes a fourth Transistor T4 to provide a corresponding potential to the third node C. Please refer to FIG. 3 a and FIG. 3 b , which are structural diagrams of a pixel circuit disclosed in this embodiment.

A first electrode of the fourth transistor T4 is connected to the third node C, a second electrode of the fourth transistor T4 is used for inputting an initialization potential, and a control electrode of the fourth transistor T4 is used for inputting an initialization control signal V _Ini . In the initialization phase, the fourth transistor T4 is turned on in response to the active level of the initialization control signal V _Ini , and the second pole of the fourth transistor T4 transmits the initialization potential input by the second pole of the fourth transistor T4 to the third node C.

It should be noted that when the driving transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are N-type thin film transistors, please refer to FIG. 3a, the initialization potential of the second pole input of the fourth transistor T4 is low Level V _L , the effective level of the initialization control signal V _Ini is a high level V _H . When the driving transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are P-type thin film transistors, please refer to FIG. 3b, the initialization potential of the second pole input of the fourth transistor T4 is a high level V _H , The active level of the initialization control signal V _Ini is a low level V _L .

Taking FIG. 3a as an example, please refer to FIG. 4, which is a timing diagram of the driving process of the pixel circuit shown in FIG. 3a. The driving process of the pixel circuit is roughly the same as the driving process of Embodiment 1, including: initialization phase, threshold value compensation phase, data writing phase and light emitting phase, the difference lies in the initialization phase, the low level V of the third node C _L is provided by the second pole of the fourth transistor T4 instead of the first level terminal VDD, and the rest of the driving process is the same as that of the first embodiment, and will not be repeated here.

It should be noted that, since the initialization potential of the third node C is low level V _L , therefore, the second pole of the fourth transistor T4 can be connected to the second level terminal VSS, please refer to FIG. 5a, the second level terminal VSS An initialization potential of low level V _L is provided to the second electrode of the fourth transistor T4.

Of course, when the pixel circuit shown in FIG. 3b is used, that is, when each transistor is a P-type thin film transistor, the effective level of the initialization control signal V _Ini is a low level V _L , and the initialization potential provided by the second pole of the fourth transistor T4 is High level V _H . At this time, the second pole of the fourth transistor T4 can be connected to the first level terminal _VDD . Please refer to FIG.

Compared with Embodiment 1, the advantage of this embodiment is that the first level terminal VDD or the second level terminal VSS is a constant high level V _H or low level V _L , and there is no need to output an initialization potential. Timing control is easier to implement when the first level terminal VDD or the second level terminal VSS is at a constant potential.

Embodiment three:

Please refer to FIG. 6a and FIG. 6b, which are the structure diagrams of the pixel circuit disclosed in this embodiment. The difference from the above embodiment is that the second pole of the fourth transistor T4 is used to couple The initialization potential of the pole is provided by the data line DATA.

Please refer to FIG. 7 , which is a driving sequence diagram of the pixel circuit shown in FIG. 6 a in this embodiment. The driving process of the pixel circuit in this embodiment is basically the same as that in Embodiment 2. The initialization potential of C (such as low level V _L ) is provided by the data line DATA, and the data line DATA provides the reference potential V _REF and the data voltage V _DATA to the third transistor T3 respectively during the threshold compensation stage and the data writing stage.

The specific working process shown in Figure 6a is:

During the initialization phase, the initialization control signal V _Ini becomes active high level, and the fourth transistor T4 is placed in a conduction state, and the scanning signal V _Scan and the light emission control signal V _EM are also at the active high level at the same time. Transistors T2 and T3 are in the conduction state, and the initialization potential low level V _L on the data line DATA is simultaneously written into the third node C through the transistor T4, and written into the first node A and the second node through the transistors T3 and T2 In B, the potentials of the three nodes A, B, and C are all at the low level V _L .

During the threshold compensation stage, the initialization control signal V _Ini becomes low level V _L , so that the fourth transistor T4 is in a cut-off state. The scanning signal V _Scan and the light-emitting control signal V _EM continue to be at the high level of the active level, and the data line DATA outputs the reference potential V _REF , which is input to the nodes A and B through the transistors T3 and T2, so that the nodes A and B level for V _REF . The first level terminal VDD charges the node C through the driving transistor T1. The rest of the driving process is the same as that of the second embodiment, and will not be repeated here.

Compared with the second embodiment, the advantage of this implementation example is that there is one less power line that provides the initialization potential to the second electrode of the fourth transistor T4, which reduces the complexity of the process and simplifies the structure.

It should be noted that, for the pixel circuit shown in Figure 6b, its driving process is similar to the driving process principle of Figure 6a, the difference is that the effective level of the pixel circuit shown in Figure 6b is low level, and the initialization potential is high level. I won't repeat them here.

Embodiment four:

Please refer to FIG. 8a and FIG. 8b, which are the structure diagrams of the pixel circuit disclosed in this embodiment. The difference from the above embodiments is that the control electrode of the fourth transistor T4 is connected to the first electrode of the fourth transistor T4; in the initialization stage, The active level of the initialization control signal V _Ini input by the control electrode of the fourth transistor T4 is provided by the first electrode of the fourth transistor T4 .

Please refer to FIG. 9, which is a timing diagram of the driving process of the circuit shown in FIG. 8a in this embodiment. The driving process of the pixel circuit in this embodiment is roughly the same as that in Embodiment 2. Provide mode and turn-off mode of the fourth transistor T4 in the threshold compensation stage.

The specific working process is: in the initialization stage, the potential Vx input by the second pole of the fourth transistor T4 is an initialization potential such as a low level. At this time, since the control pole of the fourth transistor T4 is connected to its first pole, the second pole The fourth transistor T4 in the tube connection manner discharges the third node C, thereby pulling down the potential of the third node C, and completing the initialization of the potential of the third node C. In the threshold compensation stage and subsequent stages, the potential Vx input to the second electrode of the fourth transistor T4 becomes a high level, so that the fourth transistor T4 is in a cut-off state. The rest of the driving process is the same as that of the second embodiment, and will not be repeated here.

Compared with the second embodiment, the advantage of this implementation example is that there is one less power line, which reduces the complexity of the process and simplifies the structure.

It should be noted that, for the pixel circuit shown in Figure 8b, its driving process is similar to the driving process principle of Figure 8a, the difference is that the effective level of the pixel circuit shown in Figure 8b is low level, and the initialization potential is high level. I won't repeat them here.

Embodiment five:

Please refer to FIG. 10a and FIG. 10b, which are a structural diagram of a pixel circuit disclosed in this embodiment. The difference from the above-mentioned embodiment is that the pixel circuit disclosed in this embodiment also includes a fifth transistor T5, and the first node A The required reference potential V _REF is transmitted by the fifth transistor T5, and the data line DATA only provides the data signal V _DATA , thereby simplifying the timing control of the data line DATA. Specifically, the pixel circuit includes: a drive transistor T1 and a light-emitting element OLED connected in series between the first level terminal VDD and the second level terminal VSS, and a second transistor T2, a third transistor T3, a fourth transistor T4, a second transistor T2, and a second transistor T2. Five transistor T5 and storage capacitor C1. Wherein, in the pixel circuit shown in FIG. 10a, each transistor (driving transistor T1, second transistor T2, third transistor T3, fourth transistor T4, and fifth transistor T5) is an N-type thin film transistor; the pixel shown in FIG. 10b In the circuit, each transistor (driving transistor T1, second transistor T2, third transistor T3, fourth transistor T4 and fifth transistor T5) is a P-type thin film transistor.

The first pole of the driving transistor T1 is connected to the first end of the light-emitting element OLED to form a third node C, and the second pole of the driving transistor T1 and the second end of the light-emitting element OLED are respectively used to connect to the first level terminal VDD and the second Level terminal VSS. In one embodiment, please refer to FIG. 10a, the first terminal of the light-emitting element OLED is an anode, and the second terminal of the light-emitting element OLED is a cathode; the second electrode of the driving transistor T1 is used to connect to the first level terminal VDD to emit light The second terminal of the OLED is used to be connected to the second level terminal VSS. In another embodiment, please refer to FIG. 10b, the first terminal of the light-emitting element OLED is a cathode, and the second terminal of the light-emitting element OLED is an anode; the second pole of the driving transistor T1 is used to connect to the second level terminal VSS, The second end of the light emitting element OLED is used to be connected to the first level end VDD.

The control electrode of the driving transistor T1 is connected to the first electrode of the second transistor T2 to form a first node A, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3 to form a second node B, and the second transistor T2 The control pole of is used to input the light-emitting control signal V _EM .

The second electrode of the third transistor T3 is used to connect to the data line DATA. In a specific embodiment, the data line DATA is used to provide the data signal V _DATA , and the control electrode of the third transistor T3 is used to input the scan signal V _Scan .

The first terminal of the fifth transistor T5 is connected to the first node A, the second terminal of the fifth transistor T5 is used for inputting the reference potential V _REF , and the control terminal of the fifth transistor T5 is connected to the control terminal of the third transistor T3.

A first electrode of the fourth transistor T4 is connected to the third node C, a second electrode of the fourth transistor T4 is used for inputting an initialization potential, and a control electrode of the fourth transistor T4 is used for inputting an initialization control signal V _Ini .

The storage capacitor C1 is connected between the second node B and the third node C.

In a specific embodiment, the pixel circuit works sequentially in the first stage, the second stage and the third stage. In this embodiment, the first stage is an initialization stage, the second stage may sequentially include a threshold compensation stage and a data writing stage, and the third stage is a light emitting stage.

In the first stage, the fourth transistor T4 is turned on to initialize the potential of the third node C in response to the active level of the initialization control signal V _Ini ; or, preferably, in the first stage, the second transistor T2 also responds to the light emission control signal V _EM The first active level of the conduction initializes the potentials of the first node A and the second node B, and the end time of the first active level of the light emission control signal V _EM is earlier than the end time of the active level of the initialization control signal V _Ini .

In the second stage, the fifth transistor T5 and the third transistor T3 are turned on in response to the active level of the scanning signal V _Scan , the turned-on fifth transistor T5 transmits the reference potential V _REF to the first node A, and the turned-on third transistor T3 transmits the data signal V _DATA to the second node B; the driving transistor T1 is turned on under the action of its control electrode potential (such as the gate potential, corresponding to the potential of the first node A) V _REF , and the turned-on driving transistor T1 will transmit The electrical signal of the first level terminal VDD or the second level terminal VSS is used to adjust (could be charging or discharging) the potential of the third node C until the potential of the node C is adjusted to V _REF -V _TH , the drive transistor T1 enters the cut-off state, and at this time, the potential of the third node C is maintained at V _REF -V _TH , which is stored by the storage capacitor C1, wherein V _TH is the threshold voltage of the driving transistor T1. In the third stage, the second transistor T2 is turned on in response to the second active level of the light emission control signal V _EM , and the driving transistor T1 is turned on in response to the potential of the first node A to drive the light emitting element OLED to emit light.

It should be noted that, in one embodiment, please refer to FIG. 10a, the active level of the light emission control signal V _EM (including the first active level and the second active level), the active level of the initialization control signal V _Ini and the scan signal The effective levels of _{V Scan} are all high levels; in another embodiment, please refer to FIG. Both the active level of V _Ini and the active level of the scan signal V _Scan are low.

In this embodiment, the initialization control signal V _Ini , the active level of the scan signal V _Scan and the second active level of the light emission control signal V _EM come sequentially.

Since the effective level of the initialization control signal V _Ini is ahead of the arrival time of the effective level of the scanning signal V _Scan , when there are multiple rows of pixel circuits and emit light row by row, the initialization control signal input by the control electrode of the fourth transistor T4 V _Ini can preferably be provided by the scanning signal V _Scan of the upper pixel circuit, that is, the control electrode of the fourth transistor T4 of the pixel circuit in the current row can preferably be coupled to the control electrode of the third transistor T3 of the upper pixel circuit.

The driving process of the pixel circuit disclosed in this embodiment will be described below by taking FIG. 10a as an example. The driving process of the pixel circuit in this embodiment is divided into an initialization stage, a threshold compensation stage, a data writing stage and a light emitting stage, as shown in FIG. 11 is the signal timing of this embodiment, and the details of this embodiment are described in conjunction with FIG. 11 and FIG. 10a drive process.

In the initialization phase: the initialization control signal V _Ini is at an active high level, and the fourth transistor T4 is placed in a conduction state, and the second pole of the fourth transistor T4 inputs the initialization potential low level V _L , and passes the conduction The fourth transistor T4 writes into the third node C. Therefore, the potential of the third node C drops to the low level V _L of the initialization potential, and under the coupling of the storage capacitor C1 , the potential of the second node B is also pulled down. In a preferred embodiment, when just entering the initialization phase, the light emission control signal V _EM may be at an active high level, and after entering the initialization phase after a delay for a period of time, the light emission control signal V _EM becomes a low level. When the light emission control signal V _EM is at an effective high level, the third node C can pull down the potentials of the first node A and the second node B through the coupling effect of the storage capacitor C1, and pulling down the potential of the first node A can Prevent a large current from flowing through the light emitting element OLED.

In the data writing and threshold compensation stage: the initialization control signal V _Ini becomes low level, so that the fourth transistor T4 is in the cut-off state; the scanning signal V _Scan becomes active level high level, so that the transistors T3 and T5 are turned on state, the reference potential V _REF input by the second pole of the fifth transistor T5 is written into the first node A through the turned-on fifth transistor T5, and the data voltage V _DATA provided by the data line DATA is written into the first node A through the third transistor T3 Two Node B. At the same time, the drive transistor T1 is in the conduction state, and the first level terminal VDD charges the third node C through the drive transistor T1, so the potential of the third node C will rise slowly until it rises to V _REF - When V TH is lower than V _TH , the driving transistor T1 will enter the cut-off state, and the potential of the third node C will be maintained at V _REF -V _TH . Where V _TH is the threshold voltage of the driving transistor T1. After the data input and threshold compensation phases are over, the threshold voltage information of the driving transistor T1 is stored on the node C through the storage capacitor C1. It should be noted that V _REF -V _TH is smaller than the threshold voltage of the light emitting element OLED, so as to ensure that the light emitting element OLED does not emit light in these two stages.

In the light-emitting stage: the scanning signal V _Scan becomes low level, so that the transistors T3 and T5 are in the cut-off state; the light-emitting control signal V _EM becomes the active level high level, so that the second transistor T2 is in the conductive state, at this time, The light emitting element OLED starts to emit light, and the potential of the third node C also becomes V _OLED . V _OLED is the potential of the anode of the light-emitting element OLED when it emits light. At this time, since the second node B and the first node A are coupled and connected through the second transistor T2, the potentials of the two nodes are the same, and the node A (B) becomes:

VnodeA＝V _OLED +V _DATA -V _REF +V _TH …(4-1)

From (4-1), it can be concluded that the current flowing through the OLED during the light-emitting phase is:

Wherein, μ _n , C _ox , W and L are the effective mobility, the gate capacitance per unit area, the channel width and the channel length of the driving transistor T1 respectively. It can be seen from (4-2) that the current flowing through the light-emitting element OLED has nothing to do with the threshold voltage of the driving transistor T1 and the threshold voltage of the light-emitting element OLED itself, so the pixel circuit in this example can well compensate for the display error. Uniformity.

For an example with multiple rows of pixel circuits, the traditional progressive scanning light emitting mode can be preferably used. The first level terminal VDD is a constant potential, and the scanning signal V _Scan of each row does not need to output high level or low level at a certain moment. level pulse.

It should be noted that when the transistors use P-type thin film transistors, please refer to Figure 10b, the driving process is the same as that in Figure 10a, the difference is that the active level of each transistor is the low level V _L ; In the initialization phase, the second electrode of the fourth transistor T4 provides a high level to charge the third node C (cathode of the light-emitting element OLED) to a high level V _H .

Compared with the above-mentioned embodiments, this embodiment increases the signal lines required for driving the pixel circuit, which is beneficial to timing control.

This embodiment also discloses a display circuit driving method. The display circuit adopts the pixel circuit of the above embodiment. Each driving cycle of the pixel circuit includes an initialization stage, a threshold value compensation stage, a data writing stage and a light emitting stage. The driving method includes:

In the initialization phase, the second transistor T2 is turned on, and the potential at both ends of the storage capacitor C1 and the potential at the control electrode of the driving transistor T1 are respectively initialized. In other embodiments, the fourth transistor T4 may also be turned on to assist in initializing the potential at both ends of the storage capacitor C1.

In the threshold compensation phase, the third transistor T3 and/or the fifth transistor T5 are turned on to provide a reference potential to the control electrode of the driving transistor T1, read the threshold voltage information of the driving transistor T1 and store it through the storage capacitor C1. In one embodiment, the reference potential can be provided through the third transistor T3; in another embodiment, the reference potential can also be provided through the fifth transistor T5.

In the data writing phase, the third transistor T3 is turned on to transmit the data voltage V _DATA and store it in the storage capacitor C1.

It should be noted that, in a specific embodiment, the threshold compensation stage and the data writing stage can also be performed simultaneously, for example, the third transistor T3 and the fifth transistor T5 are turned on at the same time, the fifth transistor T5 provides a reference potential, and the third transistor T5 provides a reference potential. The transistor T3 transmits the data voltage V _DATA , so that the compensation of the threshold voltage of the driving transistor T1 and the writing of the data voltage V _DATA are realized simultaneously.

In the light-emitting phase, the first transistor T1 is driven to generate a driving current according to the voltage difference across the storage capacitor C1, and drives the light-emitting element OLED to emit light.

Embodiment six:

This embodiment also discloses a display device. Please refer to FIG. 12 , which is a structural schematic diagram of the display device disclosed in this embodiment. The display device includes:

The display panel 100, the display panel 100 includes the pixel circuits Pixel[1][1]...Pixel[n][m] provided in the above embodiment arranged in a matrix of n rows and m columns, wherein n and m are integers greater than 0 , Pixel[n][m] characterizes the pixel circuit in the nth row and m column; multiple scan lines Gate[1]...Gate[n] in the first direction (for example, horizontal direction) connected to each pixel, wherein, Gate [n] indicates the scanning line corresponding to the pixel circuit in the nth row, which is used to provide scanning control signals to the pixel circuit in the row, such as initialization control signal V _Ini , scanning signal V _Scan , light emission control signal V _EM , etc.; and the second A plurality of data lines Data[1]...Data[m] in a direction (for example, vertical direction), wherein Data[m] represents the data line corresponding to the pixel circuit in the mth column, and is used to provide the data voltage V _DATA of each pixel circuit. The display panel may be a liquid crystal display panel, an organic light emitting display panel, an electronic paper display panel, etc., and the corresponding display device may be a liquid crystal display, an organic light emitting display, an electronic paper display, etc. It should be noted that, in other embodiments, some scanning control signals required by the pixel circuit can also be provided through global lines, such as the power supply line required for the first level end, the initialization required for the initialization control signal V _Ini Those skilled in the art can adjust the control line, threshold value extraction control line and light emission control line according to the requirements of specific pixel circuits.

The gate driving circuit 200 is used for generating scan pulse signals, and providing required control signals to the pixel circuits through each row of scan lines Gate[1]...Gate[n] formed along the first direction.

A data drive circuit 300, the signal output end of the data drive circuit 300 is coupled to the corresponding data lines Data[1]...Data[m] in the display panel 100, and the data voltage signal V _DATA generated by the data drive circuit 300 passes through the data lines Data[1]...Data[m] are transmitted to the corresponding pixel unit to achieve image grayscale.

The controller 400 is used for providing control timing to the gate driving circuit and the data driving circuit.

The above uses specific examples to illustrate the present invention, which is only used to help understand the present invention, and is not intended to limit the present invention. For those skilled in the technical field to which the present invention belongs, some simple deduction, deformation or replacement can also be made according to the idea of the present invention.

Claims (8)

1. A pixel circuit, comprising:

a driving transistor (T1) and a light emitting element (OLED) for being connected in series between a first level terminal (VDD) and a second level terminal (VSS), and a second transistor (T2), a third transistor (T3) and a storage capacitor (C1);

a first pole of the driving transistor (T1) is connected to a first terminal of the light emitting element (OLED) to form a third node (C), and a second pole of the driving transistor (T1) and a second terminal of the light emitting element (OLED) are respectively for connection to the first level terminal (VDD) and the second level terminal (VSS);

a control electrode of the driving transistor (T1) is connected to a first electrode of the second transistor (T2) to form a first node (a), a second electrode of the second transistor (T2) is connected to a first electrode of the third transistor (T3) to form a second node (B), and a control electrode of the second transistor (T2) is used for inputting the light emission control signal (V) to the display panel_EM)；

A second pole of the third transistor (T3) is coupled to provide the data signal (V)_DATA) Or a reference potential (V)_REF) And a control electrode of the third transistor (T3) for inputting the scan signal (V)_Scan)；

A storage capacitor (C1) is connected between the second node (B) and the third node (C);

in the first stage, the second transistor (T2) and the third transistor (T3) are respectively responsive to the light emission control signal (V)_EM) And the first active level of (V) and the scanning signal (V)_Scan) Is turned on, and transmits a reference potential (V) to the first node (A) and the second node (B)_REF) Initializing potentials of the first node (A) and the second node (B), supplying the initialization potential to the third node (C) through corresponding signal sources, and reading a threshold voltage (V1) of the driving transistor (T1)_TH)；

In the second stage, the second transistor (T2) is controlled by the light emission control signal (V)_EM) Controlled to be in an off state, the third transistor (T3) responds to the scan signal (V)_Scan) To a second node (B) for transmitting a data signal (V)_DATA)；

In the third stage, the third transistor (T3) is driven by the scan signal (V)_Scan) Controlled to be in an off state, the second transistor (T2) responds to the light emission control signal (V)_EM) The driving transistor (T1) is turned on in response to the potential of the first node (a) to drive the light emitting element (OLED) to emit light.

2. The pixel circuit of claim 1, wherein the first stage comprises, in order: an initialization stage and a threshold compensation stage;

a second pole of the driving transistor (T1) is connected to the first level terminal (VDD), a second pole of the light emitting element (OLED)A terminal for connection to a second level terminal (VSS); in the initialization phase, the second pole of the driving transistor (T1) transmits the initialization potential of the first level terminal (VDD) to initialize the potential of the third node (C); in the threshold compensation phase, the second pole of the driving transistor (T1) transmits the active level of the first level terminal (VDD), and the storage capacitor (C1) reads the threshold voltage (V1) of the driving transistor (T1) according to the potential of the second node (B) and the potential of the third node (C)_TH) (ii) a Or,

a second terminal of the driving transistor (T1) is for connection to the second level terminal (VSS), and a second terminal of the light emitting element (OLED) is for connection to the first level terminal (VDD); in the initialization phase, the second pole of the driving transistor (T1) transmits the initialization potential of the second level terminal (VSS) to initialize the potential of the third node (C); in the threshold compensation phase, the second pole of the driving transistor (T1) transmits the active level of the second level terminal (VSS), and the storage capacitor (C1) reads the threshold voltage (V1) of the driving transistor (T1) according to the potential of the second node (B) and the potential of the third node (C)_TH)。

3. A pixel circuit as claimed in claim 1, further comprising a fourth transistor (T4), the first stage comprising in sequence: an initialization stage and a threshold compensation stage;

a first pole of the fourth transistor (T4) is connected to the third node (C), a second pole of the fourth transistor (T4) is used for inputting an initialization potential, and a control pole of the fourth transistor (T4) is used for inputting an initialization control signal (V)_Ini)；

In the initialization phase, the fourth transistor (T4) responds to the initialization control signal (V)_Ini) Is turned on, the initialization potential of the second pole input of the fourth transistor (T4) is transferred to the third node (C).

4. The pixel circuit according to claim 3, wherein the driving transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are N-type thin film transistors;

a second terminal of the driving transistor (T1) for connecting to the first level terminal (VDD), and a second terminal of the light emitting element (OLED) for connecting to the second level terminal (VSS);

a second pole of the fourth transistor (T4) is connected to the second level terminal (VSS), and the initialization potential inputted to the second pole of the fourth transistor (T4) is provided by the second level terminal (VSS) during the initialization phase; or,

the second pole of the fourth transistor (T4) is used to connect to the DATA line (DATA), and the initialization potential of the second pole input of the fourth transistor (T4) is provided by the DATA line (DATA) during the initialization phase.

5. The pixel circuit according to claim 3, wherein the driving transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are P-type thin film transistors;

a second terminal of the driving transistor (T1) is for connection to the second level terminal (VSS), and a second terminal of the light emitting element (OLED) is for connection to the first level terminal (VDD);

a second pole of the fourth transistor (T4) is connected to the first level terminal (VDD), and an initialization potential of a second pole input of the fourth transistor (T4) is provided by the first level terminal (VDD) during an initialization phase; or,

the second pole of the fourth transistor (T4) is used to connect to the DATA line (DATA), and the initialization potential of the second pole input of the fourth transistor (T4) is provided by the DATA line (DATA) during the initialization phase.

6. A pixel circuit according to any one of claims 3-5, wherein a control electrode of the fourth transistor (T4) is connected to the first electrode of the fourth transistor (T4); in the initialization phase, an initialization control signal (V) is inputted to the gate of the fourth transistor (T4)_Ini) Is provided by the first pole of the fourth transistor (T4).

7. A display device, comprising:

a pixel circuit matrix comprising pixel circuits according to any of claims 1-6 arranged in a matrix of n rows and m columns, n and m being integers greater than 0;

a gate driving circuit for generating a scan pulse signal and supplying a required control signal to the pixel circuit through each row scan line formed in a first direction;

a data driving circuit for generating data voltage signals representing gray scale information and supplying the data signals to the pixel circuits through the data lines formed in the second direction;

and a controller for providing control timing to the gate driving circuit and the data driving circuit.

8. A pixel circuit driving method for the pixel circuit according to any one of claims 1 to 6, wherein each driving period of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, and a light emission phase, the driving method comprising:

in the initialization phase, the second transistor (T2) is conducted, and the potential of the two ends of the storage capacitor (C1) and the potential of the control electrode of the driving transistor (T1) are respectively initialized;

in the threshold compensation phase, the third transistor (T3) and/or the fifth transistor (T5) are/is turned on, a reference potential is provided for a control electrode of the driving transistor (T1), and threshold voltage information of the driving transistor (T1) is read and stored through the storage capacitor (C1);

the third transistor (T3) turns on the transmission data voltage V in the data writing phase_DATAAnd stored in a storage capacitor (C1);

in the light emitting stage, the first transistor (T1) generates a driving current according to a voltage difference driving across the storage capacitor (C1), and drives the light emitting element (OLED) to emit light.