CN104700900B - A kind of detecting system and method for memory Single event upset effecf - Google Patents

Abstract

The invention relates to a detection system and method for the single-event flipping effect of a memory. In the process of reading back the logic state of a storage node, two or more read-back verification methods are used, and the two read-back data are compared before and after to judge Whether the state of the storage node is in a disturbed state, if so, read back again until the storage state is stable or give up reading back under the condition of the total measurement error allowed, and accept the previous read back data. The present invention effectively solves the problem that single event reversal and transient interference cannot be distinguished in current single event effect detection, enables the test system to have the ability to carry out single event effect testing in a strong interference environment, and improves the anti-single event reversal ability of devices confidence in the estimate.

Description

A detection system and method for memory single event upset effect

technical field

The invention belongs to the field of radiation effect research, and relates to a method for detecting the single-event flipping effect of a memory, in particular to a method for distinguishing between the single-event flipping effect of the memory and the external instantaneous disturbance effect.

Background technique

The space electronics system is affected by the radiation environment, which may change the logic state in the digital circuit. Changes in these logic states can lead to abnormal operation of the system, which is the content that the space microelectronics system must focus on testing and protecting. The generation process of single event upset effect (SEU) is: various high-energy particles (high-energy protons, alpha particles, heavy ions, etc.) in space are incident on the sensitive nodes of the memory, and radiation-induced charges are generated at the nodes. These induced charges After being collected by the electrodes of the nodes, an interference current is generated, which is similar to the writing process of the memory. When the interference current is strong enough, the original stored logic state of the node will be reversed, such as the stored state changes from "0" to "1", or from "1" to "0"; when the interference current is weak, The logic state originally stored by the node is restored after a short period of fluctuation, that is, the single-event transient disturbance process.

In addition to single-event transient disturbance factors, state transitions of digital circuits, state transitions of peripheral high-power devices, and electrostatic discharge phenomena will all affect the working state of the measurement system, which will have a greater impact on the test results.

When choosing a memory for a space electronics system, it is necessary to understand the anti-single event effect capability of the device. The single event flipping effect test in a radiation environment is the main technical means to evaluate the anti-single event effect ability of the device. During the test, it is necessary to continuously detect the storage state in the memory unit and compare it with the correct storage state to determine whether the storage state is reversed. Since it is impossible to synchronize the detection of the state of the memory with the particle incident in the radiation environment, the result of the state detection of the memory is affected by the instantaneous disturbance, which affects the evaluation of the ability of the device to resist the single event effect.

In the previous tests of the single event upset effect, the logic state of the storage node was directly read, and the instantaneous interference factor of ion incident was not considered. Since the transient interference factor occurs randomly, ignoring this factor will lead to an underestimation of the device's ability to resist single event effects.

For example, when reading the data of a certain unit of the memory, due to the effect of strong external interference, the read data has a bit error, which affects the statistical flip data (related to the number of bits that the data code has logical flip, the actual situation is that the storage unit Single-event upsets due to high-energy particle incidence did not occur, only reading process errors under strong interference occurred). When the data of the unit is read again, the read data is inconsistent with the previous bit error data, so that the reading process error caused by strong interference is recorded again, that is, one interference can produce two error statistics.

Contents of the invention

Aiming at the shortcomings of the above-mentioned single event effect test method, the purpose of the present invention is to provide a single event upset effect test method suitable for memory, which can effectively separate the influence of transient disturbances caused by other interference sources on test results.

A method for detecting a memory single event flipping effect, which is special in that it includes the following steps:

Step 1] Initialize memory:

Write known data to all nodes in the memory;

Step 2] Prepare for testing:

Initialize the global measurement parameters during the test;

Step 3] Prepare for readback verification:

Set the readback control counter to 0;

Step 4] Read back data:

Take out the real-time state of the data from the node at the specified address of the memory, and store it in the real-time data buffer;

Step 5] Accumulate the readback control counter:

Add 1 to the readback control counter;

Step 6] The first readback judgment:

Judging whether the readback control counter is 1; if it is 1, then it is the first readback, and enters step 11; if it is not 1, then enters step 7;

Step 7] Maximum readback judgment:

Judging whether the accumulative readback control counter is the maximum readback number; if yes, it is the last readback, and enters step 9; if no, then enters step 8;

Step 8] Node status judgment:

Judging whether the node state is stable by comparing the data in the real-time data buffer with the previous data buffer; if the data in the two buffers is the same, it is stable, and the data in the real-time data buffer is sent to the readback data buffer , jump to step 9; if the data is different, it is an interference state, store the data in the real-time data buffer into the previous data buffer, and jump to step 4;

Step 9] Statistics:

Compare the readback data buffer with the initially written data, analyze and count the total number of error bits;

Step 10] Task completion judgment:

Judge whether the test task is completed according to the current address; if not, prepare the next test address and jump to step 4; otherwise, stop the test;

Step 11] Prepare to read back again:

Store the data in the current data buffer into the previous data buffer, and jump to step 4.

The above global measurement parameters include:

The flip counter ErrorCounter is used to record the total number of single event flips in each test task;

The operation start address BeginAddr, the current address CurrentAddr, and the stop address EndAddr are used to control the start and end of the test task;

The start time TimeBegin of the readback test and the end time TimeStop of the readback test are used to record the duration of the test process;

Readback control counter RereadCounter, used to record the number of readbacks under each test vector;

The maximum number of readbacks Nmax is a constant, Nmax≥3;

The data BusData on the data bus, the real-time data buffer CurrentData, the previous data buffer LastData and the readback data buffer RereadBuffer are respectively used to represent the memory data bus data, the real-time data collected in the memory, the last collected data and the final Definitely read back data.

A detection system for the single event flip effect of memory, which is special in that it includes a host computer and a test system located in the measurement room;

The test system includes a test controller, a read-back controller, a write controller and a timing controller;

The host computer sends the specific information of the measurement task to the test controller, including the test chip object, the test start address, the operation category, and the correct matching data;

The test controller forms a set of test vector lists based on the specific information of the measurement task, each test vector points to a measurement address of the memory under test, and calls the readback controller and the write controller respectively according to the operation category to realize the measurement Task management and control; the operation category is divided into readback operation and write operation;

The read-back controller and the write controller are control units that use a test vector as a unit, combined with a specific test operation, to implement read and write operations on the target device through a timing controller;

The concrete steps of described specific test operation are:

Step 1] Prepare for readback verification:

Set the readback control counter to 0;

Step 2] Read back data:

Take out the real-time state of the data from the node at the specified address of the memory, and store it in the real-time data buffer;

Step 3] Accumulate the readback control counter:

Add 1 to the readback control counter;

Step 4] The first readback judgment:

Determine whether the readback control counter is 1; if it is 1, then it is the first readback, and enter step 8; if it is not 1, then enter step 5;

Step 5] Maximum readback judgment:

Judging whether the accumulative readback control counter is the maximum readback number; if yes, it is the last readback, and enters step 7; if no, then enters step 6;

Step 6] Node status judgment:

Judging whether the node state is stable by comparing the data in the real-time data buffer with the previous data buffer; if the data in the two buffers is the same, it is stable, and the data in the real-time data buffer is sent to the readback data buffer , jump to step 7; if the data is different, it is an interference state, store the data in the real-time data buffer into the previous data buffer, and jump to step 2;

Step 7] Statistics:

Compare the readback data buffer with the initially written data, analyze and count the total number of error bits;

Step 8] Prepare to read back again:

Store the data in the current data buffer into the previous data buffer and jump to step 2;

The timing controller is used to generate the excitation signal required for the operation of the memory, and the control unit for collecting the data of the memory unit in an appropriate manner is the interface between the measurement system and the memory under test.

The above readback operation includes the following steps: the test controller obtains the readback data under the given measurement address, compares and analyzes it with the correct matching data, and counts the error data; when all the test vectors are executed, the final statistical The result is returned to the host computer.

Compared with the prior art, the present invention has beneficial effects as follows:

The present invention adopts the screening technology of single event flipping and transient disturbance to detect the transient disturbance phenomenon introduced by the existence of other disturbance sources in the test process, and is characterized in that in the process of reading back the logic state of the storage node, the Two or more readback verification methods, through the comparison of the two readback data before and after, judge whether the state of the storage node is in a disturbed state, if so, read back again until the storage state is stable or within the allowable total measurement error Under the condition of giving up the readback again, accept the previous readback data.

The present invention effectively solves the problem that single event reversal and transient interference cannot be distinguished in current single event effect detection, enables the test system to have the ability to carry out single event effect testing in a strong interference environment, and improves the anti-single event reversal ability of devices confidence in the estimate.

The detection method of the invention can effectively discriminate the transient disturbance caused by other interference sources in the measurement process of the single event flipping effect, and reduce the measurement uncertainty.

Description of drawings

Figure 1 is a memory single event upset effect test system and its test system composition diagram;

Fig. 2 is a step diagram of a single event effect flipping test method.

detailed description

As shown in Fig. 2, the present invention is applicable to the single event flipping effect test under strong interference conditions, and the test system includes a host computer and a test system in the measurement room, a measured memory and a particle beam in the irradiation room. Wherein, the method for measuring the single event upset effect of the present invention is implemented on the test system hardware in the measurement room. The relevant system hardware is mainly composed of test controller, read-back controller, write controller and timing controller.

The test controller is used to realize the management and control of the measurement task. The upper computer sends the specific details of the measurement task to the test controller, such as the test chip object, the test start address, the operation category (divided into readback and write), Correct matching data and other information. Based on the detailed parameters of these measurement tasks, the test controller forms a set of test vector lists, each test vector points to a measurement address of the memory under test, and calls the readback controller and write controller to complete specific operations according to the operation category. If it is a readback operation, the test controller will obtain the readback data under the given measurement address, compare and analyze it with the correct matching data, and count the error data. After all the test vectors are executed, the final statistical results are returned to the host computer.

The readback controller and the write controller are the control units that use the test vector as the unit, combined with the specific test operation, to realize the read and write operation of the target device through the timing controller, and are the executive agencies that mainly implement the test logic and test method. The method of the present invention improves the discrimination of single event reversal effect and single event transient disturbance effect in the readback control process by solidifying a specific method in the actuator.

The timing controller is used to generate the excitation signal required for the memory operation, and the control unit that collects the data of the memory unit in an appropriate way is the interface between the measurement system and the device under test.

In the present invention, mainly aiming at the random single event transient disturbance phenomenon in the data read-back process, a single-event flipping effect test method is designed, and the method is solidified in the read-back controller.

The key parameters are:

The ErrorCounter flip counter is used to record the total number of single event flips in each test task.

BeginAddr, CurrentAddr, EndAddr operate the start address, current address, and stop address, which are used to control the start and end of the test task.

TimeBegin, TimeStop readback test start time, end time, used to record the duration of the test process.

RereadCounter readback control counter, used to record the number of readback under each test vector.

Nmax is the maximum number of readbacks, which is a constant. The larger Nmax is, the stronger the ability to discriminate between single event flipping and transient disturbances is. However, in order to avoid system false death (system test tasks cannot be completed normally under the action of long-period interference sources), it is considered that under certain system measurement errors, Nmax ≥3.

BusData, CurrentData, LastData, and RereadBuffer are respectively: data on the data bus, real-time data buffer, previous data buffer, and readback data buffer, which are respectively used to represent the memory data bus data, the real-time data collected in the memory, Last acquisition data and finalized readback data.

The specific implementation steps are as follows:

1) Initialize memory.

Write known data to all nodes in the memory (for example, 8-bit memory can write 0x55H, 0xAAH, 0x00H, 0xFFH, etc.);

2) Prepare for the test.

Initialize the global measurement parameters during the test, error counter ErrorCounter=0, set the readback start address BeginAddr, current readback address CurrentAddr=BeginAddr, readback stop address EndAddr, set the start time TimeBegin of the readback test, etc. ;

3) Prepare for readback verification.

Readback control counter RereadCounter=0;

4) Read back the data.

Through the timing controller, provide the memory with the necessary read operation excitation signal (determined by the operation manual of the memory), and take out the node storage data (sampling data bus BusData encoding), and store in the real-time data buffer CurrentData=BusData;

5) Accumulate the readback control counter.

Readback control counter RereadCounter=RereadCounter+1;

6) The first readback judgment.

Determine whether the readback control counter RereadCounter is 1. If it is 1, it is the first readback, go to step 11); if it is not 1, go to step 7);

7) Maximum readback judgment.

Determine whether the accumulative readback control counter RereadCounter is Nmax. If yes, it is the last readback, go to step 9); if no, go to step 8);

8) Node status judgment.

By comparing the real-time data buffer CurrentData with the previous data buffer LastData whether the data is consistent to determine whether the node state is stable. If the data in the two buffers is the same, then it is stable, and the data in the real-time data buffer is sent to the readback data buffer (RereadBuffer=CurrentData, jump to step 9); if the data is different, then it is an interference state, and the real-time The data in the data buffer is stored in the previous data buffer LastData=CurrentData, jump to step 11);

9) Statistics.

The read-back data buffer RereadBuffer is compared with the correct matching data, and the number of wrong flipped bits N is obtained by analysis, and the total number of updates ErrorCounter=ErrorCounter+N.

10) Task completion judgment.

Judging whether the CurrentAddr is equal to the stop address EndAddr, to judge whether the test task is completed. If they are equal, it means that the test task has not been completed, and the next test address is prepared, usually by address auto-increment, that is, CurrentAddr=CurrentAddr+1, jump to step 4); otherwise, stop this test.

11) Prepare to read back again.

Store the data in the current data buffer into the last data buffer LastData=CurrentData, jump to step 4).

Claims (4)

1. a kind of detection method of memory Single event upset effecf, it is characterised in that comprise the following steps：

Step 1】Initialize memory：

To all node write-in given datas in memory；

Step 2】Setup test：

Global measuring parameter in test process is initialized；

Step 3】Prepare retaking of a year or grade checking：

Retaking of a year or grade control register is set to 0；

Step 4】Back read data：

Data real-time status is taken out in the node for specifying address from memory, and is stored in real time data buffer；

Step 5】Cumulative retaking of a year or grade control register：

Retaking of a year or grade control register adds 1 counting；

Step 6】First time retaking of a year or grade judges：

Judge whether retaking of a year or grade control register is 1；Then it is first time retaking of a year or grade, into step 11 if 1；If not being 1, Into step 7；

Step 7】Maximum retaking of a year or grade judges：

Judge whether cumulative retaking of a year or grade control register is maximum retaking of a year or grade number；If it is, being last time retaking of a year or grade, into step 9； If NO, then into step 8；

Step 8】Node state judges：

Whether by comparing the data of real time data buffer and previous data buffer, whether unanimously to carry out decision node state steady It is fixed；If data are identical in two buffers, for stabilization, the data in real time data buffer are sent to back read data buffer In, jump to step 9；If data are different, for disturbance state, the data in real time data buffer are stored in previous data In buffer, step 4 is jumped to；

Step 9】Statistics：

Compare back read data buffer and the data being originally written into, analytic statistics always malfunctions digit；

Step 10】Task completes to judge：

Judge whether test assignment completes according to current address；If do not completed, prepare next test address, jump to step Rapid 4；Otherwise this test is stopped；

Step 11】Prepare retaking of a year or grade again：

Data in current data buffer are stored in previous data buffer, step 4 is jumped to.

2. the detection method of memory Single event upset effecf according to claim 1, it is characterised in that：

The global measuring parameter includes：

Register ErrorCounter is overturn, for recording in each test assignment, the total bit of single-particle inversion occurs；

Initial address BeginAddr, current address CurrentAddr, halt address EndAddr are operated, for controlling test to appoint The beginning and end of business；

TimeBegin, the end time TimeStop of retaking of a year or grade test between at the beginning of retaking of a year or grade test, for recording test process Duration；

Retaking of a year or grade controls register RereadCounter, the number of times for recording retaking of a year or grade under each test vector；

Maximum retaking of a year or grade times N max, is constant, Nmax >=3；

Data BusData on data/address bus, real time data buffer CurrentData, previous data buffer LastData and Back read data buffer RereadBuffer, is respectively used to represent what is collected in memory data bus data, memory When real data, last time gathered data and the back read data finally determined.

3. a kind of detecting system of memory Single event upset effecf, it is characterised in that including the host computer between measurement and Test system；

The test system includes test controller, retaking of a year or grade controller, writing controller and time schedule controller；

Specifying information from the host computer to test controller sending measuring task, including test chip object, test originate Location, class of operation, correct matched data；

The test controller forms one group of test vector list based on the specifying information of measurement task, each test Vector points to a measurement address of memory under test, is called retaking of a year or grade controller to be realized with writing controller respectively according to class of operation Management and control to measurement task；The class of operation is divided into read back operation and write operation；

The retaking of a year or grade controller and writing controller are in units of test vector, with reference to specific test operation, to pass through sequential control Device processed realizes the control unit to the read-write operation of target devices；

The specific test operation is comprised the concrete steps that：

Step 1】Prepare retaking of a year or grade checking：

Retaking of a year or grade control register is set to 0；

Step 2】Back read data：

Data real-time status is taken out in the node for specifying address from memory, and is stored in real time data buffer；

Step 3】Cumulative retaking of a year or grade control register：

Retaking of a year or grade control register adds 1 counting；

Step 4】First time retaking of a year or grade judges：

Judge whether retaking of a year or grade control register is 1；Then it is first time retaking of a year or grade, into step 8 if 1；If being not 1, enter Enter step 5；

Step 5】Maximum retaking of a year or grade judges：

Judge whether cumulative retaking of a year or grade control register is maximum retaking of a year or grade number；If it is, being last time retaking of a year or grade, into step 7； If NO, then into step 6；

Step 6】Node state judges：

Whether by comparing the data of real time data buffer and previous data buffer, whether unanimously to carry out decision node state steady It is fixed；If data are identical in two buffers, for stabilization, the data in real time data buffer are sent to back read data buffer In, jump to step 7；If data are different, for disturbance state, the data in real time data buffer are stored in previous data In buffer, step 2 is jumped to；

Step 7】Statistics：

Compare back read data buffer and the data being originally written into, analytic statistics always malfunctions digit；

Step 8】Prepare retaking of a year or grade again：

Data in current data buffer are stored in previous data buffer, step 2 is jumped to；

The time schedule controller is used to produce the pumping signal required for storage operation, and gathers storage list in appropriate mode The control unit of metadata, is the interface of measuring system and memory under test.

4. the detecting system of memory Single event upset effecf according to claim 3, it is characterised in that：

The read back operation comprises the following steps：Test controller obtains the back read data under given measurement address, and with it is correct Matched data be compared, mistake of statistics data；After the completion of all test vectors are performed, by final statistics knot Fruit is back to host computer.