CN104700891B - Resistive memory device and writing method thereof - Google Patents
Resistive memory device and writing method thereof Download PDFInfo
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- CN104700891B CN104700891B CN201310665231.XA CN201310665231A CN104700891B CN 104700891 B CN104700891 B CN 104700891B CN 201310665231 A CN201310665231 A CN 201310665231A CN 104700891 B CN104700891 B CN 104700891B
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Abstract
本发明公开了一种电阻式存储器装置及其写入方法，其中，电阻式存储器装置包括存储单元阵列以及存储器控制器。存储器控制器在设定期间及重置期间的其一提供未连接至选中电阻式存储单元的未选中位元线第一位元线电压及未选中字线第一字线电压，其中，第一位元线电压等于写入电压VW乘以(n‑1)/n，第一字线电压等于VW×1/n。存储器控制器在设定期间及重置期间的另一提供未连接至选中电阻式存储单元的未选中位元线第二位元线电压，并提供未连接至该选中电阻式存储单元的未选中字线第二字线电压，其中，第二位元线电压等于VW×1/n，第二字线电压等于VW×(n‑1)/n。
The present invention discloses a resistive memory device and a writing method thereof, wherein the resistive memory device comprises a memory cell array and a memory controller. The memory controller provides a first bit line voltage of an unselected bit line not connected to a selected resistive memory cell and a first word line voltage of an unselected word line during one of a setting period and a reset period, wherein the first bit line voltage is equal to a write voltage V W multiplied by (n-1)/n, and the first word line voltage is equal to V W ×1/n. The memory controller provides a second bit line voltage of an unselected bit line not connected to a selected resistive memory cell during the other of the setting period and the reset period, and provides a second word line voltage of an unselected word line not connected to the selected resistive memory cell, wherein the second bit line voltage is equal to V W ×1/n, and the second word line voltage is equal to V W ×(n-1)/n.
Description
Technical field
The invention relates to a kind of resistive memory device and its wiring methods, and interlock in particular to one kind
Formula (cross bar) resistance-type memory and its wiring method.
Background technique
Based on the demand for secondary generation non-volatility memorizer, a kind of resistance-type memory is suggested.This resistance-type
Memory can be into row stochastic access action, and is substituted for NAND-flash memory.In order to promote the density of memory,
A kind of three-dimensional resistance formula memory of highdensity vertical arrangement is also suggested.
In alternating expression resistance-type memory, the main subject under discussion being concerned about is, stores for alternating expression resistance-type
When storage unit in device carries out data write activity, same memory line again is arranged with the storage unit chosen and storage arranges, and
Not selected storage unit can cause it because of voltage difference caused by the voltage value transmitted in bit line and wordline
Resistance value is adjusted in the region being reset, and causes the mistake of storage data.
Above-mentioned situation is that a kind of resistive memory cell without asymmetric characteristic is particularly acute.Such resistance
The current-voltage correlation characteristic that current-voltage correlation characteristic and its of the Reset Status of formula storage unit set state is not symmetrical.
Therefore, for resistive memory cell, to be reset and set all be directed to using the practice of identical voltage by existing
Resistive memory cell with asymmetric characteristic carries out data write-in, it is clear that is more inappropriate.
Summary of the invention
The purpose of the present invention is to provide a kind of resistive memory device and the wiring methods of resistance-type memory, can
Effectivelying prevent its resistive memory cell, there is a phenomenon where write errors, effectively maintain the correctness of data.
Resistive memory device of the invention includes memory cell array and Memory Controller.Memory cell array
Including most memory cells, each memory list includes the majority resistive memory cell being stacked with.Resistance-type storage
Unit is respectively coupled to most wordline, and memory cell is simultaneously respectively coupled to most bit lines.Memory Controller coupling
To memory cell array, wherein Memory Controller during setting and resetting during one of provide be not connected to select
Unselected the first bit of the bit line line voltage of most items of middle resistive memory cell, and provide and be not connected to that resistance-type is chosen to deposit
The first word line voltage of most unselected word lines of storage unit, wherein the first bit line voltage is equal to write-in voltage VWMultiplied by (n-
1)/n, the first word line voltage are equal to VW× 1/n, and n is greater than 3.Memory Controller is another during setting and during resetting
The unselected bit line second bit line voltage for being not connected to choose resistive memory cell is provided, and provides and is not connected to the choosing
The second word line voltage of unselected word line of middle resistive memory cell, wherein second bit line voltage is equal to VW× 1/n, second
Word line voltage is equal to VW×(n-1)/n。
The wiring method of resistance-type memory of the invention, step include: to provide to be not connected to one during a setting
The unselected one first bit line voltage of bit line of most items of resistive memory cell is chosen, and offer is not connected to this and chooses electricity
One first word line voltage of most unselected word lines of resistive memory cell, wherein the first bit line voltage is equal to a write-in electricity
Press VWMultiplied by (n-1)/n, the first word line voltage is equal to VW× 1/n, n are greater than 3；And it is provided during a resetting and is not connected to select
The one second bit line voltage of unselected bit line of middle resistive memory cell, and provide and be not connected to choose resistance-type storage single
The second word line voltage of unselected word line of member, wherein second bit line voltage is equal to VW× 1/n, the second word line voltage are equal to VW×
(n-1)/n。
Based on above-mentioned, the present invention provides different wordline by resetting and setting for resistive memory cell
Voltage and bit line voltage, so that the resistance value of unselected resistive memory cell can not be by the word line voltage received
And bit line voltage is influenced, and change its original stored data, keep the correctness of data.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawings
It is described in detail below.
Detailed description of the invention
Figure 1A is painted the structural schematic diagram of the memory cell array of the resistance-type of one embodiment of the invention.
Figure 1B is painted the enlarged diagram of the memory cell of the embodiment of the present invention.
Fig. 2 is painted the schematic diagram of the resistive memory device of one embodiment of the invention.
Fig. 3 A is painted the schematic diagram of the setting means of the resistive memory cell of the embodiment of the present invention.
Fig. 3 B is painted the schematic diagram of the reset mode of the resistive memory cell of the embodiment of the present invention.
The current-voltage correlation curve graph of the resistive memory cell for the embodiment of the present invention that Fig. 4 is painted.
Fig. 5 A and Fig. 5 B be painted respectively the resistive memory cell of the embodiment of the present invention setting and resetting movement it is another
Embodiment schematic diagram.
Fig. 6 is painted the flow chart of the wiring method of the resistance-type memory of one embodiment of the invention.
Wherein, the reference numerals are as follows:
100,210: memory cell array
110: memory cell
BL1~BL3: bit line
WLA1~WLA3: word line group
WL1~WL3: wordline
111,112,113,114: insulating layer
RC1, RC2, RC3: resistive memory cell
RSL: resistive layer
BL1~BL3: bit line BL1
200: resistive memory device
220: Memory Controller
SRC: resistive memory cell is chosen
410~430: curve
RP: conductor resistance
UNRC1~UNRC4, HSRC1~HSRC4: unselected resistive memory cell
VW: write-in voltage
RESET, SET: arrow
S610~S620: write step
Specific embodiment
Figure 1A is please referred to, Figure 1A is painted the structural schematic diagram of the memory cell array of the resistance-type of one embodiment of the invention.
Memory cell array 100 includes the memory cell 110 of most column structures, and memory cell 110 is arranged in array fashion
Column, and it is respectively coupled to majority bit line BL1~BL3.Memory cell 110 is simultaneously coupled with word line group WLA1~WLA respectively,
It include three wordline in each word line group WLA1~WLA3 in Fig. 1, and with memory cell 110 for example, it is coupled
Word line group WLA3 include wordline WL1~WL3.
Below and referring to Figure 1A and Figure 1B, wherein Figure 1B is painted the memory cell 110 of the embodiment of the present invention
Enlarged diagram.In fig. ib, the intersection of insulating layer 111,112,113 and 114 be stacked on as wordline WL1, WL2 and
The conductive interlayer of WL3, resistive layer RSL cover insulating layer 111,112,113 and 114 and wordline WL1, WL2 and WL3, position
First line BL1 then covers resistive layer RSL.In fig. ib, shape is then distinguished in the region between bit line BL1 and wordline WL1, WL2 and WL3
At resistive memory cell RC1, RC2 and RC3.
Referring to figure 2., Fig. 2 is painted the schematic diagram of the resistive memory device of one embodiment of the invention.Resistance-type storage
Device device 200 includes memory cell array 210 and Memory Controller 220.Memory cell array 210 can be such as Figure 1A institute
The memory cell array 100 being painted.Memory Controller 220 is coupled to memory cell array 210, and to provide bit line electricity
Pressure and word line voltage are to memory cell array 210.
In embodiments of the present invention, Memory Controller 220 can provide word of the word line voltage into memory cell array 210
Line, and transmit by the bit line in memory cell array 210 bit line voltage or by the position in memory cell array 210
First line receives the data information of reading.It is worth noting that, about for the resistance-type storage in memory cell array 210
When unit carries out the movement of data write-in, it can be divided into and the resetting (reset) of resistance value is carried out to resistive memory cell and is set
Fixed (set) two ways.
Below referring to Fig. 2 and Fig. 3 A, wherein Fig. 3 A is painted the resistive memory cell of the embodiment of the present invention
The schematic diagram of setting means.In figure 3 a, using 3 × 3 memory cell array as example, choose resistance-type storage single when to be directed to
When first SRC carries out the setting of resistance value, Memory Controller 220 can provide during setting and choose resistive memory cell SRC
Reference ground voltage of the selected word line WL3 connected for example equal to 0 volt, and provide and choose resistive memory cell SRC institute
Connection chooses bit line BL3 that voltage V is writtenW.In addition, Memory Controller 220 and providing unselected word line WL1 and WL2 etc.
Voltage V is written in 1/4WWord line voltage, and unselected bit line BL1 and BL2 is provided and is equal to 3/4 write-in voltage VWBit line
Voltage.Wherein, unselected bit line BL1 and BL2 and unselected word line WL1 and WL2 and resistive memory cell SRC is chosen not
It is connected.
It is noted that there are many conductor resistance RP on wordline WL1~WL3 and bit line BL1~BL3.Staggeredly
Under the structure of formula (cross bar) resistance-type memory, these conductor resistances RP is distributed between each resistive memory cell.
The current-voltage correlation curve of the resistive memory cell referring to Fig. 4 embodiment of the present invention being painted please be synchronize herein
Figure.Wherein, curve 410~430 is painted reset voltage required for resistive memory cell equal to -4V, -5V and -6V respectively
Different relation curves, arrow RESET and SET be then respectively the resistive memory cell electric current that is reset and set with
Voltage relationship variation tendency.The current-voltage correlation characteristic and resistance-type of the Reset Status for the resistive memory cell that Fig. 4 is painted
The current-voltage correlation characteristic of the setting state of storage unit is not symmetrical.
Under the conditions described above, the curve graph that is painted of cooperation Fig. 4, unselected resistive memory cell UNRC1~UNRC4 its
Voltage difference between the bit line and wordline that are born is equal to 1/2 write-in voltage VW.And to be set to resistive memory cell
Required write-in voltage is about that 5V is example, 1/2 write-in voltage VWIt is approximately equal to 2.5V, and does not enter the area effectively set
Domain.Therefore, the resistance value of unselected resistive memory cell UNRC1~UNRC4 can't be set.Opposite, choose resistance
What formula storage unit SRC was born chooses the voltage difference between bit line BL3 and selected word line WL3 to be equal to write-in voltage VWAnd it can
Effectively to set its resistance value.
It is especially noted that the unselected electricity for one of being connected to selected word line WL3 and choosing bit line BL3
Resistive memory cell HSRC1~HSRC4.Wherein, using unselected resistive memory cell HSRC4 as example, unselected resistance-type
Storage unit HSRC4 is equal to write-in voltage V by choosing bit line BL3 to receiveWBit line voltage, and pass through unselected word line
WL1, which is received, is equal to 1/4 write-in voltage VWWord line voltage.In this way, the bit line of resistive memory cell HSRC4 connection and
Voltage difference between wordline is equal to 3/4 write-in voltage VW, it is equal to 3.75V.The curve that foundation Fig. 4 is painted is it is known that unselected electricity
The resistance value of resistive memory cell HSRC4 will not be set.Remaining unselected resistive memory cell HSRC1~HSRC3 with
The case where unselected resistive memory cell HSRC4, is similar, and resistance value will not be set and generate data write error
Phenomenon.
Below and referring to Fig. 2 and Fig. 3 B, wherein Fig. 3 B is painted the resistive memory cell of the embodiment of the present invention
Reset mode schematic diagram.In figure 3b, using 3 × 3 memory cell array as example, resistance-type is chosen to store when to be directed to
When cell S RC carries out the resetting of resistance value, Memory Controller 220 can provide during resetting and choose resistive memory cell
Reference ground voltage of the selected word line WL3 that SRC is connected for example equal to 0 volt, and provide and choose resistive memory cell SRC
What is connected chooses bit line BL3 that voltage V is writtenW.In addition, Memory Controller 220 and providing unselected word line WL1 and WL2
Equal to 3/4 write-in voltage VWWord line voltage, and unselected bit line BL1 and BL2 is provided and is equal to 1/4 write-in voltage VWBit
Line voltage.
The curve graph that is painted of cooperation Fig. 4, its bit line for being born of unselected resistive memory cell UNRC1~UNRC4
And the voltage difference between wordline is equal to -1/2 write-in voltage VW.And electricity to be written required for being reset to resistive memory cell
Pressure is about that -6V is example, -1/2 write-in voltage VWEqual to -3.0V, and the region effectively set is not entered.Therefore, unselected
The resistance value of resistive memory cell UNRC1~UNRC4 can't be reset.Opposite, choose resistive memory cell SRC institute
The voltage difference chosen between bit line BL3 and selected word line WL3 born is equal to negative write-in voltage VW(- 6V) and can be effective
Resetting its resistance value.
And it is especially noted that is one of be connected to selected word line WL3 and choose bit line BL3 is unselected
Resistive memory cell HSRC1~HSRC4.Wherein, using unselected resistive memory cell HSRC4 as example, unselected resistance
Formula storage unit HSRC4 is equal to write-in voltage V by choosing bit line BL3 to receiveWBit line voltage, and pass through unselected word
Line WL1, which is received, is equal to 3/4 write-in voltage VWWord line voltage.In this way, the bit line of resistive memory cell HSRC4 connection
And the voltage difference between wordline is equal to -1/4 write-in voltage VW, it is approximately equal to -1.5V.The curve that foundation Fig. 4 is painted is it is known that unselected
The resistance value of middle resistive memory cell HSRC4 will not be reset.Remaining unselected resistive memory cell HSRC1~
The case where HSRC3 is with unselected resistive memory cell HSRC4 is similar, and resistance value will not be reset and generate data write-in
The phenomenon of mistake.
Subsidiary one mentions, when carrying out the resetting and setting of resistance value to resistive memory cell pair of the embodiment of the present invention
It is not connected to that the voltage of the unselected bit line of resistive memory cell and unselected word line is chosen to can be interchanged in offer.Example
Such as, when to be directed to the resetting for choosing resistive memory cell SRC to carry out resistance value, unselected word line WL1 and WL2 also be can provide
Equal to 1/4 write-in voltage VWWord line voltage, and unselected bit line BL1 and BL2 is provided and is equal to 3/4 write-in voltage VWBit
Line voltage.And when to be directed to the setting for choosing resistive memory cell SRC to carry out resistance value, it also can provide unselected word
Line WL1 and WL2 are equal to 3/4 write-in voltage VWWord line voltage, and unselected bit line BL1 and BL2 is provided and is equal to 1/4 write-in electricity
Press VWBit line voltage.
A and Fig. 5 B, Fig. 5 A and Fig. 5 B are painted the resistive memory cell of the embodiment of the present invention respectively referring to figure 5. below
Setting and resetting movement another embodiment schematic diagram.In fig. 5, dynamic when to carry out setting to resistive memory cell
When making, it can provide and choose the selected word line WL3 of resistive memory cell SRC connection to be equal to 0 volt of reference during setting
Ground voltage, and provide and choose what resistive memory cell SRC connect to choose bit line BL3 write-in voltage VW.Meanwhile for
The unselected word line WL1 and WL2 for being not connected to resistive memory cell SRC, which are then provided, is equal to 1/n write-in voltage VWWordline electricity
Pressure, and (n-1)/n write-in voltage V is provided for the unselected bit line BL1 and BL2 for being not connected to resistive memory cell SRCW
Bit line voltage, so as to choose other unselected resistive memory cells outside resistive memory cell SRC can be shielded
(inhibited).Wherein, n is the real number greater than 3.
In figure 5B, when to carry out resetting movement to resistive memory cell, electricity can be provided and chosen during resetting
The selected word line WL3 of resistive memory cell SRC connection is equal to 0 volt of reference ground voltage, and provides and deposit with resistance-type is chosen
Storage unit SRC connection chooses bit line BL3 that voltage V is writtenW.Meanwhile for being not connected to resistive memory cell SRC not
Selected word line WL1 and WL2, which are then provided, is equal to (n-1)/n write-in voltage VWWord line voltage, and deposit for being not connected to resistance-type
The unselected bit line BL1 and BL2 of storage unit SRC provides 1/n and voltage V is writtenWBit line voltage, so as to which resistance-type is chosen to deposit
Other unselected resistive memory cells outside storage unit SRC can be shielded (inhibited).
Certainly, above-mentioned Fig. 5 A can be applied to carry out resetting movement to resistive memory cell, and Fig. 5 B then can be applied to
Set action is carried out to resistive memory cell.
Subsidiary one mentions, and the array for utilizing 3 × 3 resistive memory cells to be constituted in previous embodiment is merely model
Example, not to limit scope of the invention.The resistive memory cell array of any dimension can apply technology of the invention
Feature carries out write activity.
Fig. 6 is please referred to below, and Fig. 6 is painted the flow chart of the wiring method of the resistance-type memory of one embodiment of the invention.
Wherein, it in step S610, by providing during setting and one of during resetting is not connected to that resistance-type is chosen to deposit
Unselected the first bit of the bit line line voltage of most items of storage unit, and provide and be not connected to choose the more of resistive memory cell
Several first word line voltages of unselected word line, wherein the first bit line voltage is equal to write-in voltage VWMultiplied by (n-1)/n, first
Bit line voltage is equal to VW× 1/n, n are the real number greater than 3.Also, in step S620, by during setting and resetting the phase
Between another offer therein be not connected to choose the unselected bit line second bit line voltage of resistive memory cell, and mention
For being not connected to choose the second word line voltage of unselected word line of resistive memory cell, wherein second bit line voltage is equal to
VW× 1/n, second bit line voltage are equal to VW×(n-1)/n。
About the implementation detail of above-mentioned steps, embodiment has detailed explanation immediately for the implementation stated before this invention,
Below without repeating more.
In conclusion the present invention resets and sets the different wordline of offer using for resistive memory cell
Voltage and bit line voltage, so that the resistance value for the resistive memory cell chosen correctly can be set or be reset,
And unchecked resistive memory cell is effectively interdicted, without being set or being reset.In this way, number
According to can be effectively correctly written in resistive memory cell, also, the data originally stored are in the feelings for not needing to update
Under condition, also it is unlikely to be written over because of the write activity of other resistive memory cells, maintains the correctness of data.
Claims (5)
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| US20120069626A1 (en) * | 2010-09-17 | 2012-03-22 | Takashi Nakano | Semiconductor memory device |
| US20130223126A1 (en) * | 2012-02-27 | 2013-08-29 | Samsung Electronics Co., Ltd. | Resistive memory device and memory system including the same |
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| CN1507631A (en) * | 2001-03-21 | 2004-06-23 | ����뵼��ɷ�����˾ | Method and apparatus for biasing selected and unselected array lines when writing to a memory array |
| CN1527321A (en) * | 2003-03-07 | 2004-09-08 | 三洋电机株式会社 | Memory |
| CN1574077A (en) * | 2003-06-17 | 2005-02-02 | 夏普株式会社 | Nonvolatile semiconductor memory device, and programming method and erasing method thereof |
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