CN104700888A - Three-dimensional three-port bit cell and method of assembling same - Google Patents

Abstract

Provided is a three-dimensional three-port bit cell, comprising a reading portion of a cell on a first hierarchy. The reading portion comprises a plurality of reading port elements. The three-port bit cell also comprises a writing portion which is arranged on a cell of a second hierarchy, the second hierarchy being vertically piled relative to the first hierarchy. The first hierarchy and the second hierarchy use at least hole coupling. The writing portion comprises a plurality of writing port elements. The invention also provides a method of assembling the three-dimensional three-port bit cell.

Description

Three-dimensional three-port bit cell and its assembly method

Cross application of related application

This application is a continuation-in-part of U.S. Patent Application No. 14/098,567, filed December 6, 2013, entitled "THREE DIMENSIONALDUAL-PORT BIT CELL AND METHOD OF ASSEMBING SAME," the entire contents of which are hereby incorporated by reference.

technical field

The systems and methods of the present invention relate to static random access memory ("SRAM") arrays, and more particularly, to three-port bit cells usable with SRAM arrays.

Background technique

Static Random Access Memory ("SRAM") or semiconductor memory includes a plurality of cells arranged in rows and columns to form an array. An SRAM cell includes a plurality of transistors coupled to bit lines and word lines for reading data from and writing data to the memory cell. A single-port SRAM is capable of writing a single bit of data to or reading a bit of data from a bit cell at a specific time. In contrast, multi-port SRAMs are capable of multiple reads or multiple writes substantially simultaneously. Conventional multi-port SRAM structures include word lines ("WL") in different metal lines, resulting in different capacitive loading due to different metal lengths for user SRAM signal routing. Compared with the single-port SRAM structure, the multi-port SRAM structure is larger and wider in the WL direction. Since multi-port SRAMs are larger and wider in the WL direction, the aspect ratio of the SRAM array can be affected during heavy WL loads, especially for wide input/output ("I/O") designs. When compared to a single-port SRAM, the peripheral logic circuits of the multi-port SRAM are doubled. As such, multi-port SRAMs can occupy a larger area and create signal routing complexity.

Contents of the invention

In order to solve the defects existing in the prior art, according to one aspect of the present invention, a three-dimensional three-port bit cell is provided, including: a write part, arranged on the first level, the write part includes a plurality of write port elements and a read portion disposed on a second level, the second level being vertically stacked with respect to the first level and coupled to the first level using at least one via, the second level comprising a plurality of read ports element.

In the three-dimensional three-port bit cell, the writing part further includes a plurality of writing bit lines, each of which extends along the first direction in the first conductive layer of the first level, and the reading The portion also includes a plurality of read bit lines each extending along the first direction in the first conductive layer of the second level.

In the three-dimensional three-port bit cell, the writing part further includes at least one writing word line extending along a second direction different from the first direction in the second conductive layer of the first level , and the read part further includes at least one read word line extending along the second direction in the second conductive layer of the second level.

In the three-dimensional three-port bitcell, the plurality of read port elements includes a plurality of read port gates.

In the three-dimensional three-port bit cell, the read portion further includes at least one latched inverter disposed on the second level and coupled to the plurality of read port gates.

In the three-dimensional three-port bitcell, the plurality of write portion elements includes a plurality of write port gates.

In the three-dimensional three-port bitcell, the three-port bitcell includes ten transistor cells, the read port element includes four transistor structures and the write port element includes six transistor structures.

In the three-dimensional three-port bit cell, each of the plurality of read port gates and the plurality of write port gates is one of an NMOS device and a PMOS device.

The three-dimensional three-port bit cell further includes: a write control circuit disposed on the first level; and a read control circuit disposed on the second level.

In the three-dimensional three-port bit cell, the read control circuit includes a read port control circuit and a read word line decoder, and the write control circuit includes a write port control circuit and a write word line decoder.

According to another aspect of the present invention, there is provided a semiconductor memory comprising: a first level including a first port array portion; a second level vertically stacked relative to the first level using at least one via hole, the second level Level two includes a second port array portion; and at least one three-dimensional three-port bitcell comprising: a first portion disposed on the first port array portion, the first portion including a plurality of write port elements; and a second portion, Disposed on the second port array portion, the second portion includes a plurality of read port elements.

In the semiconductor memory, the first part further includes a plurality of write bit lines, each of which extends along the first direction in the first conductive layer of the first level, and the second part further includes A plurality of read bit lines are included, and each read bit line extends along the first direction in the first conductive layer of the second level.

In the semiconductor memory, the first part further includes at least one write word line, each write word line extends along a second direction different from the first direction in the second conductive layer of the first level, and The second portion also includes at least one read word line, each read word line extending along the second direction in the second conductive layer of the second level.

In this semiconductor memory, the plurality of read port elements includes a plurality of read port gates.

In the semiconductor memory, the second portion further includes at least one latched inverter coupled to the plurality of read port gates.

The semiconductor memory further includes: a write port control circuit disposed on the first level and a read port control circuit disposed on the second level.

The semiconductor memory also includes: a write driver and a write word line decoder disposed on the first level and a read input/output (I/O) circuit and a read word line decoder disposed on the second level.

According to yet another aspect of the present invention, a method is provided, comprising: arranging a write portion of a three-dimensional three-port bit cell on a first level, the write portion comprising a plurality of write port elements; A read portion of the three-dimensional three-port bitcell is disposed on a vertically stacked second level, the read portion including a plurality of read port elements; and at least one via is used to couple the first level to the second level.

The method also includes communicating a first set of signals for the plurality of write port elements within the first level; and communicating a second set of signals for the plurality of read port elements within the second level.

The method also includes: disposing at least one latching inverter on the second level; and coupling the at least one latching inverter to the plurality of read port elements.

Description of drawings

Aspects of the invention are better understood from the following detailed description when read with the accompanying figures. Note that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a perspective view of an example of a three-dimensional semiconductor integrated circuit according to some embodiments.

2 is a circuit diagram of one example of a three-dimensional static random access memory (SRAM) array used by the three-dimensional semiconductor integrated circuit shown in FIG. 1, according to some embodiments.

3 is a circuit diagram of one example of a three-dimensional dual-port bit cell used by the SRAM array shown in FIG. 2, according to some embodiments.

FIG. 4 is a block diagram of the three-dimensional dual-port bit cell shown in FIG. 3 .

5 is a flowchart of one example of a method of assembling the three-dimensional dual-port bitcell shown in FIG. 3 .

FIG. 6 is a circuit diagram of an example of a three-dimensional SRAM array used by the three-dimensional semiconductor integrated circuit shown in FIG. 1 according to some embodiments.

7 is a circuit diagram of one example of a three-dimensional three-port bit cell including an NMOS pass-gate structure for use with the SRAM array shown in FIG. 6, according to some embodiments.

FIG. 8 is a block diagram of the three-dimensional three-port bit cell shown in FIG. 7 .

9 is a circuit diagram of one example of a three-dimensional three-port bit cell including a PMOS transfer gate structure for use with the SRAM array shown in FIG. 6 in accordance with some embodiments.

FIG. 10 is a block diagram of the three-dimensional three-port bit cell shown in FIG. 9 .

FIG. 11 is a circuit diagram of an example of a three-dimensional three-port bit cell including a plurality of latch inverters provided on a read portion.

Detailed ways

The description of the exemplary embodiments is to be read in conjunction with the accompanying drawings which are considered a part of this entire specification.

The following disclosure provides many different embodiments, or examples, for implementing different features of the inventive subject matter. Specific examples of components or configurations are described below to simplify the present invention. Of course, these are merely examples and not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which the first feature and the second feature may be formed in direct contact. An embodiment in which an additional part is formed between parts such that the first part and the second part are not in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in various instances. These repetitions are for simplicity and clarity and do not in themselves indicate a relationship between the various embodiments and/or structures discussed.

In addition, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," etc.) may be used to describe the relationship between one element or component and another shown in the figures. A relationship of an element or part. Spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein should be interpreted similarly accordingly.

Some embodiments of the three-dimensional bitcells described herein have structures and designs that facilitate a reduced footprint while improving overall cell performance and inhibiting the loss of the corresponding semiconductor memory or static random access memory ("SRAM") array in which the cell is used. Signal routing complexity. For example, in some embodiments, a three-dimensional bitcell is configured such that one set of port elements of a portion of the latch is disposed on one layer of a three-dimensional ("3D") semiconductor integrated circuit ("IC") and another layer of the latch is A portion of another set of port elements is disposed on a different layer of the IC that is vertically adjacent to the aforementioned layer. Having two different sets of port elements on different layers of the IC facilitates a reduction in footprint and also reduces word line ("WL") parasitic resistance and capacitance. Thus, the overall performance of the unit is greatly improved.

FIG. 1 shows an example of a 3D semiconductor IC 10. The 3D IC 10 includes multiple layers 12-1, 12-2, 12-3, 12-n ("layers 12") that are stacked on top of each other in the z-direction. In some embodiments, layer 12 is formed using at least one through-substrate via (“TSV”) or interlayer via (“ILV”) or inter-device via (“ILD”) (not shown in FIG. 1 ). The individual dies are electrically coupled to each other. It should be noted that, as used herein, "coupling" is not limited to direct mechanical, thermal, communicative and/or electrical connections between components, but may also include indirect mechanical, thermal, communicative and/or electrical connection.

In some embodiments, each layer 12 of 3D IC 10 is a corresponding "level," each level including a corresponding active device layer and a corresponding interconnect structure (which may include multiple conductive layers (e.g., M1 , M2, etc.). As understood by those skilled in the art, an interlayer dielectric ("ILD") layer (not shown) may be disposed between immediately adjacent levels.

One example of a semiconductor memory or SRAM array 100 is shown in FIG. 2 . In some embodiments, SRAM array 100 is included in 3D IC 10 (shown in FIG. 1 ). For example, SRAM array 100 may be arranged across two layers or tiers (such as bottom layer 12-1 and upper layer 12-2), which are arranged vertically relative to each other and pass through, for example, one or more ILVs 102 (only shown in FIG. 2 ). a) coupled together.

In some embodiments, the bottom layer 12-1 includes one port (such as an A port), and the upper layer 12-2 includes another port (such as a B port). As such, in some embodiments, input/output ("I/O") circuitry for the A-port and B-port is disposed on two separate conductive layers. For example, in some embodiments, bottom layer 12 - 1 includes A-Port components such as A-Port array section 106 and A-Port word line ("WL") decoder and driver section 108 . In some embodiments, A-port array portion 106 is coupled to A-port I/O circuitry 110 by complementary bit lines (“BL”) located therebetween, such as BL_A and its complement, BLB_A. In some embodiments, A-port I/O circuit 110 is configured to receive input signals and transmit data output signals to the outside of SRAM 100.

As used herein, the term "circuit" generally refers to any programmable system, including systems and microcontrollers, reduced instruction set circuits ("RISCs"), application specific integrated circuits ("ASICs"), programmable logic circuits ( "PLC") and any other circuitry capable of performing the functions described herein. The above examples are exemplary only, and thus do not limit in any way the definition and/or meaning of the term "circuitry".

In some embodiments, the A-port WL decoder and driver section 108 is coupled to the A-port control circuit 112 . The A-port control circuit 112 may be configured to receive a clock signal of the A-port and write an enable signal (negative enable). A-port control circuit 112 may also be configured to receive address signals.

Top layer 12 - 2 includes B-port array section 116 and B-port WL decoder and driver section 118 . In some embodiments, B-port array portion 116 is coupled to B-port I/O circuitry 120 with a complementary BL positioned therebetween, such as BL_B and its complement, BLB_B. In some embodiments, B-port I/O circuitry 120 is configured to receive data input signals and transmit data output signals out of array 100 . In some embodiments, B-port WL decoder and driver section 118 is coupled to B-port control circuit 122, which may be configured to receive a B-port clock signal and a write enable signal (negative enable). B-port control circuit 122 may also be configured to receive address signals.

SRAM array 100 includes at least one three-dimensional dual port bit cell 150 including a first portion 152 disposed on a first layer (eg, bottom layer 12-1). For example, first portion 152 is disposed on at least a portion of A-port array portion 106 . Dual port bit cell 150 also includes a second portion 154 disposed on a second layer (eg, upper layer 12 - 2 of SRAM array 100 ), where the second layer is disposed vertically relative to the first layer. For example, second portion 154 is included in at least a portion of B-port array portion 116 . As will be explained in more detail below with reference to FIGS. 3 and 4 , dual-port bitcell 150 has a structure and design that facilitates reducing footprint while improving overall cell performance and suppressing signal routing complexity of SRAM array 100 .

In some embodiments, the A-port array section 106 and the A-port WL decoder and driver section 108 are disposed on the bottom layer 12-1 such that the A-port array section 106 and the A-port WL decoder and driver section 108 are connected to the B-port array section 108, respectively. Section 116 and B-port WL decoder and driver section 118 are symmetrical. Similarly, the A-port I/O circuit 110 and the A-port control circuit 112 are provided on the bottom layer 12-1 such that the A-port I/O circuit 110 and the A-port control circuit 112 communicate with the B-port I/O circuit 120 and the B-port circuit 120, respectively. Port control circuit 122 is symmetrical.

FIG. 3 is a circuit diagram of one example of a dual port bit cell 150 in accordance with some embodiments. FIG. 4 is a layout diagram of the dual port bit cell 150 . Referring to FIG. 3, in some embodiments, the dual-port bit cell 150 is a high-density dual-port bit cell, and as described above, the first portion 152 of the cell 150 is disposed on the first layer of the SRAM array 100 (FIG. 2), e.g. Bottom layer 12-1 (as shown in Figure 1 and Figure 2). For example, first portion 152 is disposed on at least a portion of A-port array portion 106 (shown in FIG. 2 ). Accordingly, the first portion 152 includes an A-port element. Second portion 154 of bitcell 150 is disposed on a second layer of SRAM array 100 (FIG. 2), such as upper layer 12-2 (shown in FIGS. 1 and 2), which is vertically disposed relative to the first layer. For example, second portion 154 is disposed on at least a portion of B-port array portion 116 (shown in FIG. 2 ), such that second portion 154 includes B-port elements.

3 and 4, in some embodiments, each portion 152 and 154 includes a plurality of wires or layers (e.g., M1, M2, M3, etc.) (“ML”) in which BL and WL are disposed such that BL at least one conductive layer (e.g., M1, M2, M3) in each of the upper and lower layers or levels 12-2 (as shown in FIGS. 1 and 2 ) and level 12-1 (as shown in FIGS. 1 and 2 ). ) along a first direction, and the word line WL extends along a second direction in the upper and lower layers or at least one second conductive layer (eg M1, M2, M3) of the level 12, wherein the first direction is different from the first Two directions. For example, the first portion 152 includes at least one WL, such as WL_A extending horizontally (ie, along the x-direction) across the bottom layer 12-1 (as shown in FIGS. 1 and 2). The first portion 152 also includes at least one pair of complementary bit lines BL extending vertically (ie, along the y-direction) across the bottom layer 12-1. For example, the first part 152 may include at least one pair of complementary BLs, such as BL_A and BLB_A shown in FIGS. 3 and 4 . As shown in FIG. 4, the bit lines BL_A and BLB_A extend parallel to each other, and a power supply line (eg, VSS) is set between them and extends parallel to the bit lines BL_A and BLB_A. The second power supply line (eg VDD) is also disposed in the same conductive layer (eg M1 , M2 , M3 ) as BL_A, BLB_A and VSS. A line for VDD is provided adjacent to BLB_A and extends parallel to bit lines BL_A and BLB_A and VSS. In some embodiments, the first portion 152 also includes an A-port element that includes at least two pass-gate (PG) transistor devices (such as PGA0 and PGA1 ), which are coupled to WL and BL. In some embodiments, the PG transistor devices are NMOS or PMOS devices. In some embodiments, additional interconnect structures 290 are used to connect active devices of the first portion 152 and active devices (eg, transistors) of the second portion 154 .

In some embodiments, the first portion 152 also includes at least one inverter 302, where each inverter 302 may include at least one pull-up (PU) transistor device (such as PU_A, FIG. 4 ) and at least one pull-down (PD ) transistor device (such as PD_A, Figure 4). In some embodiments, the PU transistor device and the PD transistor device are NMOS or PMOS devices. The first portion 152 may have any number of PG, PU and PD transistor devices.

Similar to the first portion 152, the second portion 154 may also include at least one WL, such as WL_B extending horizontally (ie, along the x-direction) across the upper layer 12-2. The second portion 154 also includes at least one pair of complementary bit lines BL extending vertically (ie, along the y-direction) across the upper layer 12-2. For example, the second part 154 may include at least one pair of complementary BLs, such as BL_B and BLB_B. In some embodiments, the second portion 154 also includes a B-port element that includes at least two PG transistor devices (such as PGB0 and PGB1 ), which are coupled to WL and BL. In some embodiments, the PG transistor devices are NMOS or PMOS devices.

In some embodiments, the second portion 154 also includes at least one inverter 304 , where the inverter 304 may include at least one PU transistor device (such as PU_B) and at least one PD transistor device (such as PD_B). In some embodiments, the PU transistor device and the PD transistor device are NMOS or PMOS devices. The second portion 154 may have any number of PG, PU and PD transistor devices.

As shown in FIG. 4, each transistor device PGA0, PGA1, PD_A, PU_A, PGB0, PGB1, PD_B, PU_B includes a gate 310, which may include a polysilicon (“poly”)/silicon oxynitride (“SION”) structure , high-k/metal gate structures, or combinations thereof. Examples of semiconductor substrates include, but are not limited to, bulk silicon, silicon phosphorous ("SiP"), silicon germanium ("SiGe"), silicon carbide ("SiC"), germanium ("Ge"), silicon-on-insulator ("SiGe") SOI-Si"), silicon-germanium-on-insulator ("SOI-Ge"), or combinations thereof. In some embodiments, gate 310 may be formed over one or more active regions ("OD") of a semiconductor substrate using various techniques. For example, gate 310 may be formed as a bulk planar metal oxide field effect transistor ("MOSFET"), a bulk FinFET with one or more fins or fingers, a semiconductor-on-insulator ("SOI") planar MOSFET, with SOI FinFETs with one or more fins or fingers or combinations thereof.

In some embodiments, PGA0, PGA1, PD_A, and PU_A transistor devices are disposed on bottom layer 12-1 such that PGA0, PGA1, PD_A, and PU_A transistor devices are symmetrical to PGB0, PGB1, PD_B, and PU_B, respectively. For example, in some embodiments, ports such as the A port and the B port (shown in FIG. 2 ) are substantially parallel to each other such that the PGA0 and PGA1 transistor devices are parallel to the PD_A and PU_A transistor devices on the same layer 12 - 1 . Similarly, the PGB0 and PGB1 transistor devices are parallel to the PD_B and PU_B transistor devices on the same layer 12-2.

In some embodiments, various vias are used for connections within each of layers 12-1 and 12-2 or between layers 12-1 and 12-2. For example, as shown in FIG. 4, in some embodiments, one ILV 102 is used to connect via 312 in layer 12-2 to via 336 in layer 12-1. Similarly, another ILV 102 is used to connect via 324 in layer 12-2 to via 347 in layer 12-1. Vias 314 and 316 respectively connect the PU_B transistor device to transistor PGA0 and power supply line VDD. Via 317 connects the PGB1 transistor device to BLB_B. Vias 318, 325 and 328 connect the PD_B transistor device to the power supply line VSS. Vias 320 and 322 and interconnect 290 connect the PGB0 transistor device to the PD_B transistor device. Via 319 connects the PGB0 transistor device to BL_B, and via 326 and interconnect 290 connects the PGB0 transistor device to via 324 . Via 321 connects the PGB0 transistor device to WL_B.

In some embodiments, via 330 connects the PGAO transistor device to WL_A. Via 334 connects the PGA0 transistor device to BL_A. Via 337 and interconnect 290 connect PD_A transistor device and PGA0 to ILV 102. Vias 336 and 338 and interconnect 290 connect the PGA0 transistor device to the PD_A transistor device. Vias 339 , 342 and 344 and interconnect 290 connect the PD_A transistor device to power supply line VSS. Via 340 connects the PGA1 transistor device to BLB_A. Vias 346 and 347 and interconnect 290 connect the PU_A transistor device to ILV 290. Via 345 connects transistor PU_A to power line VDD.

When using the above structure of the dual-port bit cell 150, one set of port elements (such as the A port) is disposed on the bottom layer 12-1 of the SRAM array 100, and another set of port elements (such as the B port) is disposed on the bottom layer 12-1 of the SRAM array 100. On the upper level 12-2. This design and structure facilitates the reduction of the occupied area of the unit and the reduction of the overall unit area. Due to the structure of the dual port bit cell 150 with two sets of port elements on separate layers, the WL parasitic resistance and capacitance are reduced. As such, the overall performance of the dual port unit 150 is greatly improved. Furthermore, by having two sets of port elements on separate layers, the power wiring and signal wiring of each of the A port and the B port are dispersed among two layers. For example, in some embodiments, the power supply for the A port may be routed within the bottom layer 12-1 for the PU_A or PD_A transistor devices, while the first set of signals for the A port (WL_A, BL_A, and BLB_A) may be routed in Bottom layer 12-1 internal routing for PGA0 and PGA1 transistor devices. Similarly, the power supply for the B port can be routed within the upper layer 12-2 for the PU_B or PD_B transistor devices, while the second set of signals (WL_B, BL_B, and BLB_B) for the B port can be routed in the upper layer 12-2 for the PGB0 and PGB1 The upper layer 12-2 of the transistor devices is wired.

5 is a flowchart of one example of a method 500 for assembling a three-dimensional dual-port bit cell (such as cell 150 (shown in FIG. , shown in Figure 3 and Figure 4)). In step 502, a first portion of latches is disposed on a first layer. For example, the first part 152 (shown in Figures 2, 3 and 4) is arranged on the A-port array on the bottom layer 12-1 (shown in Figures 1 and 2) of the 3D IC 10 (shown in Figure 1) At least a portion of portion 106 (shown in FIG. 2 ). In some embodiments, the active devices of first portion 152 are formed in a semiconductor substrate (not shown) using semiconductor processing techniques. A port WL decoder and driver section 108 (shown in FIG. 2 ), A port I/O circuit 110 (shown in FIG. 2 ) and A port control circuit 112 (shown in FIG. 2 ) are also formed on the bottom layer 12- 1 in and bottom 12-1 on.

In step 504, a second portion of the latches is disposed on a second layer adjacent to the first layer. For example, the second part 154 (shown in Figures 2, 3 and 4) is disposed on the B array part 116 (shown in Figure 2) of the upper layer 12-2 (shown in Figures 1 and 2) of the 3D IC 10 ) on at least a part of it. B-port WL decoder and driver section 118 (shown in FIG. 2 ), B-port I/O circuit 120 (shown in FIG. 2 ), and B-port control circuit 122 (shown in FIG. 2 ) are also formed on the upper layer 12- 2 middle and upper tiers 12-2.

In step 506, the first layer and the second layer are coupled together using at least one via such that the second layer is vertically stacked with respect to the first layer. For example, if layers 12-1 and 12-2 are separate semiconductor chips, layers 12-1 and 12-2 are vertically stacked, aligned and bonded to each other. In some embodiments, such as embodiments where layers 12-1 and 12-2 are hierarchical, the layers are stacked on top of each other to create a 3D stacked CMOS IC. Those skilled in the art will appreciate that, in some embodiments, one or more layers may be disposed between layers 12-1 and 12-2. In some embodiments, circuits formed in and/or on layer 12-1 are coupled to circuits formed on layer 12-2 using at least one via, such as ILV 102 (shown in FIGS. 2 , 3, and 4 ). in and/or on the circuit. For example, in some embodiments, as shown in FIG. 4, one ILV 102 is used to connect via 312 in layer 12-2 to via 336 in layer 12-1. Similarly, as shown in FIG. 4, another ILV 102 is used to connect via 324 in layer 12-2 to via 347 in layer 12-1. In addition, as shown in FIG. 4, various vias are used for connections in each layer 12-1 and 12-2.

One example of a semiconductor memory or SRAM array 600 is shown in FIG. 6 . In some embodiments, the SRAM array 600 is included in the 3D IC 10 (shown in FIG. 1 ). For example, SRAM array 600 may be arranged across two (or more) layers or levels (e.g., bottom layer 12-1 and upper layer 12-2 (shown in FIG. The ILVs 602a, 602b are coupled together.

In some embodiments, SRAM array 600 includes a write layer 604a and a read layer 604b. Write layer 604a includes write port elements such as write port array section 606 and write port word line decoder 608 . In some embodiments, the write port array portion 606 is coupled to the write port driver 610 through a complementary bit line 614 (eg, WBL and its complementary line WBLB). In some embodiments, write port driver 610 is configured to receive input signals for SRAM 600. Write port control circuitry 612 may be coupled to write port word line decoder 608 . The write port control circuit 612 is configured to receive a clock signal of the write port and a write enable signal (eg, a negative enable signal). Write port control circuit 612 may also be configured to receive address signals.

In some embodiments, SRAM 600 includes a read layer 604b. Read layer 604b includes read port elements such as read port array section 616 and read port word line decoder and driver 618 . In some embodiments, read port array portion 616 is coupled to read port I/O circuitry 620 through complementary bit lines 624 (eg, RBL and its complement, RBLB). In some embodiments, read port I/O circuitry 620 is configured to receive data input signals and/or transmit data output signals out of SRAM 600. In some embodiments, read port word line decoder 608 is coupled to read port control circuit 622 . The read port control circuit 622 may also be configured to receive a clock signal and a read enable signal of the read port. Read port control circuit 622 may also be configured to receive address signals.

SRAM array 600 includes at least one three-dimensional three-port bitcell 650, which includes a first portion 652 (eg, write port array portion 606) disposed on a first layer and a second portion 654 (eg, read port array portion 606) disposed on a second layer. part 616) (see FIG. 7). As explained in more detail below, the three-port bitcell 650 has a structure and design that facilitates smaller cell footprint, faster speed, and adjustable and flexible WL decoder layout, which is simple and wiring friendly.

In some embodiments, write port array portion 606 and write port WL decoder 608 are disposed on write layer 604a such that write port array portion 606 and write port WL decoder 608 decode with read port array portion 616 and read port WL respectively. The driver and driver sections 618 are symmetrical. Similarly, write port driver 610 and write port controller 612 may be symmetrical to read port I/O circuitry 620 and read port controller 622, respectively.

FIG. 7 is a circuit diagram of one example of a three-dimensional three-port bitcell 650 according to some embodiments. FIG. 8 is a layout diagram of a three-port bit cell 650 . Referring to FIG. 7 , in some embodiments, a three-port bit cell 650 includes a high-density three-port cell that includes a write portion 652 and a read portion 654 . The write portion 652 of the three-port bit cell 650 is disposed on at least a portion of the first layer of the SRAM array 600 (eg, the write layer 604a). The read portion 654 of the three-port bit cell 650 is disposed on at least a portion of the second layer of the SRAM array 600 (eg, the read layer 604b).

In some embodiments, each portion 652, 654 of the three-port bitcell 650 includes a plurality of conductive lines or layers in which a bitline (BL) and a wordline (WL) are disposed such that the bitline is in at least one conductive layer. extending along a first direction, and the word lines extend along a second direction in the at least one second conductive layer, wherein the first direction is different from the second direction. For example, in the embodiment shown in FIG. 7, write portion 652 includes a set of complementary bit lines WBL and WBLB. Bit lines are disposed in the first conductive layer of the writing portion 652 . Write portion 652 also includes write word lines WWL. The WWL is disposed in the second conductive layer of the writing portion 652 . WBL and WBLB extend along a first direction, such as a vertical direction, and WWL extends along a second direction, such as a horizontal direction. The read part 654 includes a set of bit lines RBL_1 and RBL_2 disposed in a first conductive layer of the read part 654 . A set of bit lines RBL_1 and RBL_2 may include complementary bit lines RBL and RBLB. The read portion 654 also includes at least one read word line disposed in the second conductive layer of the read portion 654 . In the illustrated embodiment, read portion 654 includes first and second read word lines, RWL_1 and RWL_2, respectively. RBL_1 and RBL_2 extend along a first direction, such as a vertical direction, and RWL_1 and RWL_2 extend along a second direction, such as a horizontal direction. In some embodiments, RWL_1 and RWL_2 may comprise a single read word line.

In some embodiments, write section 652 and/or read section 654 include multiple pass gate (PG) transistor devices, such as WPG1 and WPG2 disposed in write section 652 and RPG1 and RPG2 disposed in read section 654 . WPG1 and WPG2 are coupled to WBL and WBLB, respectively, and both are coupled to WWL. RPG1 is coupled to RBL_1 (or RBL) and RWL_1, and RPG2 is coupled to RBL_2 (or RBLB) and RWL_2. PG transistor devices may include PMOS or NMOS transistor devices. For example, FIGS. 7 and 8 illustrate one embodiment of a bit cell 650 including an NMOS transfer gate structure. As another example, FIGS. 9 and 10 illustrate an embodiment of a bit cell 750 in which transfer gates WPG1 and WPG2 comprise PMOS transfer gate structures.

In some embodiments, write portion 652 and/or read portion 654 may include one or more additional transistor devices. For example, in some embodiments, the write portion 652 includes a plurality of latches 656a, 656b. The plurality of latches 656a, 656b includes a self-reinforcing configuration. A plurality of latches 656 a , 656 b are coupled to WPG1 and WPG2 of write portion 652 . In some embodiments, the read portion 654 includes a plurality of gates 658a, 658b coupled to RPG1 and RPG2. In some embodiments, the read layer 654 includes a plurality of latching inverters (see FIG. 11 ).

As shown in FIG. 8, in some embodiments, the plurality of latches 656a, 656b disposed on the write layer 652 includes a plurality of pull-up (PU) transistor devices and a plurality of pull-down (PD) transistor devices. In various embodiments, the PU transistor device and the PD transistor device comprise NMOS and/or PMOS devices. In the illustrated embodiment, each latch includes a PU transistor device and a PD transistor device.

In some embodiments, multiple vias are formed to facilitate connections within each layer 652, 654 and between the write layer 652 and the read layer 654, one or more interlayer vias (ILVs) allowing the write layer 652 to read Connections between layers 654 . For example, in one embodiment, first ILV 602a is configured to electrically couple via 628 in write layer 652 to via 614 in read layer 654, and second ILV 602b is configured to couple Via 637 is electrically coupled to via 621 in read layer 654 . Vias 626 and 635 are configured to couple PG transistor devices such as WPG1 and WPG2 to WWL. Vias 631, 632, 639 and 640 couple the power supply VDD to the PU transistor devices of each latch 656a, 656b. Vias 629 and 638 couple the power supply VSS to the PD transistor device of each latch 656a, 656b.

In some embodiments, the read layer 654 includes a plurality of vias configured to facilitate connections within the read layer 654 . Vias 612 and 613 couple RPG1 to RWL_1 . Vias 619 and 620 couple RPG2 to RWL_2. Vias 615 and 622 couple power supply VSS to pull-down transistors 658a, 658b, shown as RPD1 and RPD2, respectively. Vias 624 and 625 couple RBL_1 to RPG1 , and vias 617 and 618 couple RBL_2 to RPG2 . Those skilled in the art will appreciate that more or fewer vias may be included in the write layer 652 and/or the read layer 654 .

In some embodiments, three-port bitcell 650 comprises a three-dimensional three-port ten-transistor (3D10T) bitcell. 3D 10T bit cells are configured for SRAM memory structures. The 3D 10T bit cell includes a write portion 652 and a read portion 654 disposed on different layers of the SRAM array 600, such as write port array portion 606 and read port array portion 616, respectively. In some embodiments, write portion 652 includes a six-transistor (6T) NMOS SRAM structure, and read portion 654 includes a four-transistor structure. In some embodiments, the write portion 652 includes a 6T PMOS transfer gate (PPG) SRAM structure. The write section 652 and the read section 654 are coupled through a plurality of ILVs 602a, 602b. The 3D10T bitcell facilitates a smaller footprint and eliminates wasted empty front-end area, resulting in a simple and routing-friendly 3D 10T bitcell periphery.

In various embodiments, three-port bitcell 650 may include three-port or two-port operations. In three-port operation, the first port RPG1 and the second port RPG2 are independent. For example, as shown in FIG. 7 , RPG1 is coupled to the first read word line RWL_1 , and RPG2 is coupled to the first read word line RWL_2 . Read port operations for RPG1 and RPG2 may include single-ended reads while maintaining ("holding") the value of the cell. In two-port operation, RPG1 and RPG2 are coupled, for example, through a single read word line (not shown). A two-port read port operation may include a voltage difference sense amplifier scheme.

The above-described structure of the three-port bit cell 650 facilitates a reduction in the cell footprint as well as a reduction in the overall cell area. For example, in one embodiment, the 3D 10T bitcell described above can reduce the macroscopic area by almost 50% relative to conventional 3D 10T bitcells. In addition, since the three-port bit cell 650 has the write port 652 and the read port 654 disposed on different layers, the WL parasitic resistance and capacitance are reduced, thereby improving the overall performance of the three-port bit cell 650 . By having the write port 652 and the read port 654 on different layers, the power supply wiring and signal wiring for each of the write and read sections can be dispersed between the two layers, resulting in a simple and well-routable peripheral .

9 and 10 illustrate an embodiment of a three-dimensional three-port bit cell 750, wherein the write layer 752 includes a first PMOS transfer gate structure WPG1 and a second PMOS transfer gate structure WPG2. Three-dimensional three-port bitcell 750 is similar to bitcell 650 described in connection with FIGS. 7 and 8 . FIG. 10 shows a block diagram of the three-dimensional three-port bit cell 750 shown in FIG. 9 . Bitcell 750 includes a plurality of vias to facilitate connections between layers 752 , 754 and within each layer 752 , 754 . Vias 729, 730, 738 and 739 couple the PU transistors of the latches 656a, 656b to the power supply VDD. Vias 731, 732, 740, and 741 couple the PD transistors of latches 656a, 656b to power supply VSS. The block diagram of FIG. 10 is similar to the block diagram shown in FIG. 8 .

FIG. 11 shows one embodiment of a bit cell 850 including a plurality of latching inverters 856 a and 856 b disposed on a read portion 854 . The plurality of latching inverters 856a and 856b may comprise a plurality of NMOS and/or PMOS devices. In some embodiments, transistor devices WPG1 , WPG2 and latches 856a and 856b are disposed on write layer 852 such that they are symmetrically disposed relative to transistors RPG1 , RPG2 and inverting latches 856a and 856b of read portion 854 .

Embodiments of the three-dimensional dual-port bitcells described herein have structures and designs that facilitate a reduced footprint while improving overall cell performance and suppressing signal routing complexity for corresponding static random access memory ("SRAM") arrays used by the cell . For example, in some embodiments, a 3D dual-port cell is configured such that one set of port elements for a portion of the latch is disposed on one layer of the 3D semiconductor IC, and another set of port elements for another portion of the latch is disposed on on a different layer of the IC vertically adjacent to the above layer. Having two different sets of port elements on different layers of the IC facilitates footprint reduction and also reduces WL parasitic resistance and capacitance. Thus, the overall performance of the unit is greatly improved.

In some embodiments, a three-dimensional dual-port bitcell includes a first portion of latches disposed on a first level, wherein the first portion includes a plurality of first port elements. A second portion of the latch is disposed on a second level vertically stacked relative to the first level using at least one via, wherein the second level includes a plurality of second port elements.

In some embodiments, a semiconductor memory includes a first level that includes a first port array portion. The semiconductor memory also includes a second level vertically stacked with respect to the first level using at least one via, wherein the second level includes a second port array portion. The semiconductor memory also includes at least one three-dimensional dual port cell including a first portion of the latch disposed on the first port array portion, wherein the first portion includes a plurality of first port elements. The dual port bitcell also includes a second portion of the latch disposed on the second array portion, wherein the second portion includes a plurality of second port elements.

In some embodiments, a method of using a three-dimensional dual-port bitcell includes arranging a first portion of latches of the three-dimensional dual-port bitcell on a first level, the first portion including a plurality of first port elements. The method also includes disposing a second portion of the latch of the three-dimensional dual-port bitcell on a second level vertically stacked with respect to the first level using at least one via, the second portion including a plurality of second port elements.

Embodiments of the three-dimensional three-port bitcells described herein have structures and designs that facilitate a reduced footprint while improving overall cell performance and suppressing signal routing complexity for corresponding static random access memory ("SRAM") arrays used by the cell . For example, in some embodiments, a 3D three-port cell is configured such that a set of write port elements is disposed on a first layer of a 3D semiconductor IC, and a set of read port elements is disposed on a second layer of the IC vertically adjacent to the first layer. layer. Having two different sets of port elements on different layers of the IC facilitates footprint reduction and also reduces WL parasitic resistance and capacitance. Thus, the overall performance of the unit is greatly improved.

In some embodiments, a three-dimensional three-port bitcell includes a read portion disposed on a first level. The read section includes a plurality of read port elements. The three-port bitcell also includes a write portion disposed on a second level vertically stacked relative to the first level. The first and second levels are coupled using at least one via. The write section includes a plurality of write port elements.

In some embodiments, a semiconductor memory includes a first level that includes a first port array portion. The semiconductor memory also includes a second level stacked vertically with respect to the first level. The first and second levels are coupled using at least one via. The second level includes a second port array section. The semiconductor memory also includes at least one three-dimensional three-port cell. The three-dimensional three-port bitcell includes a write portion disposed on the first port array portion of the first level. The write section includes a plurality of write port elements. The three-dimensional three-port bitcell also includes a read portion disposed on the second port array portion of the second level. The read section includes a plurality of read port elements.

In some embodiments, methods of forming three-dimensional three-port bitcells are disclosed. In a first step, a read portion of a three-dimensional three-port bit cell is provided on a first level of the semiconductor structure. The read portion of the three-dimensional three-port bitcell includes a plurality of read port elements. In a second step, a write portion of the bit cell is provided on a second level of the semiconductor structure. The write section includes a plurality of write port elements. The first level and the second level are vertically stacked and coupled through at least one via.

The foregoing discussion of features of various embodiments enables those skilled in the art to better understand the various aspects of the invention. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims (10)

1. a three-dimensional three port bit location, comprising:

Write part, be arranged in the first level, described in write part comprise multiple write port element; And

Read part, be arranged in the second level, described second level is relative to described first level vertical stacking and use at least one through hole to be coupled to described first level, and described second level comprises multiple read port element.

2. three-dimensional three port bit locations according to claim 1, wherein, described part of writing also comprises many write bit lines, every bar write bit line all extends along first direction in the first conductive layer of described first level, and described in read part also comprise many sense bit lines, every bar sense bit line all extends along described first direction in the first conductive layer of described second level.

3. three-dimensional three port bit locations according to claim 2, wherein, described part of writing also comprises at least one write word line, described write word line extends along the second direction being different from described first direction in the second conductive layer of described first level, and described in read part also comprise at least one readout word line, described readout word line extends along described second direction in the second conductive layer of described second level.

4. three-dimensional three port bit locations according to claim 1, wherein, described multiple read port element comprises multiple read port grid.

5. three-dimensional three port bit locations according to claim 4, wherein, described in read part and also comprise and be arranged in described second level and be coupled at least one latch inverters of described multiple read port grid.

6. three-dimensional three port bit locations according to claim 4, wherein, describedly multiplely write subelement and comprise multiple write port grid.

7. three-dimensional three port bit locations according to claim 6, wherein, described three port bit locations comprise ten transistor units, and described read port element comprises four transistor arrangements and described write port element comprises six transistor arrangements.

8. three-dimensional three port bit locations according to claim 6, wherein, each in described multiple read port grid and described multiple write port grid is the one in nmos device and PMOS device.

9. a semiconductor memory, comprising:

First level, comprises the first port array portion;

Second level, use at least one through hole relative to described first level vertical stacking, described second level comprises the second array of ports part; And

At least one three-dimensional three port bit location, comprising:

Part I, be arranged on described first port array portion, described Part I comprises multiple write port element; With

Part II, be arranged in described second array of ports part, described Part II comprises multiple read port element.

10. a method, comprising:

What the first level arranged three-dimensional three port bit locations writes part, described in write part comprise multiple write port element;

What the second level relative to described first level vertical stacking arranged described three-dimensional three port bit locations reads part, described in read part comprise multiple read port element; And

Use at least one through hole by grade coupled for described ground floor to described second level.