CN104685977B - 装载装置及其制造方法 - Google Patents
装载装置及其制造方法 Download PDFInfo
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- CN104685977B CN104685977B CN201480002581.0A CN201480002581A CN104685977B CN 104685977 B CN104685977 B CN 104685977B CN 201480002581 A CN201480002581 A CN 201480002581A CN 104685977 B CN104685977 B CN 104685977B
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- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000956 alloy Substances 0.000 claims abstract description 105
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 105
- 239000011159 matrix material Substances 0.000 claims abstract description 91
- 239000010949 copper Substances 0.000 claims abstract description 63
- 239000012528 membrane Substances 0.000 claims abstract description 59
- 229910052802 copper Inorganic materials 0.000 claims abstract description 48
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 20
- 239000003365 glass fiber Substances 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 239000007788 liquid Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 8
- 229920000647 polyepoxide Polymers 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 7
- 239000013077 target material Substances 0.000 claims description 7
- 238000005477 sputtering target Methods 0.000 claims description 6
- 150000001768 cations Chemical class 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 74
- 229920005989 resin Polymers 0.000 abstract description 36
- 239000011347 resin Substances 0.000 abstract description 36
- 230000006978 adaptation Effects 0.000 abstract description 17
- 239000010408 film Substances 0.000 description 56
- 239000002356 single layer Substances 0.000 description 37
- 239000010409 thin film Substances 0.000 description 33
- 239000007789 gas Substances 0.000 description 15
- 238000002203 pretreatment Methods 0.000 description 15
- 239000011230 binding agent Substances 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 11
- 239000010410 layer Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000005086 pumping Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052756 noble gas Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000008187 granular material Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910000714 At alloy Inorganic materials 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- -1 Ti is sputtered Chemical class 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
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- H—ELECTRICITY
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- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
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- C22C9/00—Alloys based on copper
- C22C9/01—Alloys based on copper with aluminium as the next major constituent
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- C23C14/14—Metallic material, boron or silicon
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- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
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- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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Abstract
本发明提供一种在树脂基板上形成不会剥落的导电膜的装载装置。通过溅射法在由树脂构成的基体3上形成含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al并与基体3的表面接触的合金薄膜4、5,在合金薄膜4、5的表面形成由铜构成的导电膜6、7,得到二层构造的布线膜9、填充连接孔2的金属插塞8。合金薄膜4、5与树脂的密合性高,布线膜9、金属插塞8不会剥离。
Description
技术领域
本发明涉及具有被图案化的布线膜的装载装置、制造该装载装置的制造方法以及在该制造方法中使用的溅射靶材。
背景技术
在现在,LSI等半导体元件被装载于层叠有多层在树脂的基体形成有布线膜的单层基板的装载基板,因此,谋求在树脂的表面形成密合性高的金属膜的技术。特别地,铜薄膜具有低电阻的优点的另一面为与树脂的密合性低,因此,在树脂与铜薄膜之间形成由其他金属构成的密合层。
图7的符号100为那样的现有技术的装载装置,层叠有多个单层基板1111、1112。
该装载装置100的各单层基板1111、1112具有由树脂构成的基体103,在基体103的表面设置有布线膜110。此外,在基体103设置有连接孔102,在连接孔102的内部设置有连接层叠的单层基板1111、1112的布线膜110彼此的金属插塞119。
在图5(a)中,为在单层基板1111之上粘贴有最上层的单层基板1112的基体103的状态。在基体103设置有连接孔102,在连接孔102的底面露出下层的单层基板1111的布线膜110的表面。
首先,如图(5)b所示那样,对含有Ti等密合用的金属的溅射靶材进行溅射,形成与基体103的表面、连接孔102的内周侧面、以及在底面露出的布线膜110接触的Ti薄膜等密合层118,接着,对铜的溅射靶材进行溅射,在密合层118的表面形成由铜薄膜构成的种子层115。
将被图案化的抗蚀膜配置在种子层115的表面上,使连接孔102的内部的种子层115和基体103的表面上的规定位置的种子层115露出,并浸渍到电镀液中来使露出的种子层115与电镀液接触,在种子层115与电镀液之间施加相对于电镀液而使种子层115成为负电位的电压,通过电镀法使铜析出于露出的种子层115的表面,在连接孔102的内部和基体103的表面上如图5(c)所示那样形成铜薄膜106、107。在该状态下,铜薄膜106、107接触,连接孔102的内部被由铜构成的铜薄膜106填充,铜薄膜106、107形成得比种子层115厚。该图(c)的符号128为抗蚀膜。
在该状态下,密合层118和种子层115具有位于铜薄膜106和107的下方的部分和位于抗蚀膜128的下方的部分,在剥离抗蚀膜128而使位于抗蚀膜128的下方的种子层115露出之后,首先,浸渍到铜的蚀刻液中,如该图(d)所示那样,一边在铜薄膜106、107的下方使被图案化的种子层105残留一边蚀刻除去露出的种子层115,使密合层118露出于所除去的部分。
接着,当浸渍到使Ti溶解的Ti蚀刻液中时,如图7所示那样,一边使位于铜薄膜106、107和种子层105的下方的密合层108残留一边蚀刻除去露出的密合层118,使基体103露出于所除去的部分。
通过连接孔102内的密合层108、种子层105和铜薄膜106构成填充连接孔102的金属插塞119,此外,通过基体103的表面上的密合层108、种子层105和铜薄膜107构成布线膜110。
铜薄膜106、107与在基体103表面露出的树脂之间的密合性低,铜薄膜106、107容易从树脂剥离,但是,作为Ti薄膜的密合层108在与树脂之间密合性高,此外,与作为铜薄膜的种子层105之间的密合性也高,因此,种子层105和铜薄膜106、107不会从基体103剥离。
可是,从上述制造工序可知,为了形成铜薄膜106、107而需要形成密合层108和种子层105这二层,布线膜110成为三层构造,制造工序增加。
此外,密合层108大量含有铜以外的Ti等元素,因此,密合层118和作为铜薄膜的种子层115不能在相同的蚀刻液中进行蚀刻,蚀刻工序复杂。
现有技术文献
专利文献
专利文献1:日本特开平8-332697号公报。
发明内容
发明要解决的课题
本发明是为了解决上述现有技术的问题而制作的,其目的在于提供一种能够在树脂露出的基体上简单地形成不会剥离的导电膜的技术。
用于解决课题的方案
用于解决上述课题的本发明是一种装载装置,具有基体和至少与在所述基体的表面露出的树脂接触且形成为规定图案的布线膜,并使电子部件与所述布线膜电连接而装载在所述基体上,其中,所述布线膜具有:合金薄膜,含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al,与所述基体的表面接触;以及导电性的导电膜,与所述合金薄膜的表面接触,含有比所述合金薄膜多的Cu。
此外,本发明是一种装载装置,其中,所述基体含有玻璃纤维,在所述基体的表面露出所述树脂和所述玻璃纤维。
此外,本发明是一种装载装置,其中,在所述基体形成有贯通表面和背面之间的连接孔,在所述连接孔的内周面露出所述树脂和所述玻璃纤维,所述合金薄膜与所述连接孔的内周面接触,在由位于所述连接孔的内周面的所述合金薄膜所包围的部分,与所述合金薄膜接触地填充有所述导电膜。
本发明是一种装载装置的制造方法,制造装载装置,所述装载装置具有基体和形成为规定图案的布线膜并使电子部件与所述布线膜电连接而装载在所述基体上,其中,所述布线膜具有:合金薄膜,至少与在所述基体的表面露出的树脂接触;以及导电性的导电膜,与所述合金薄膜接触地配置,所述装载装置的制造方法具有:合金薄膜形成工序,在真空气氛中配置所述基体,在所述真空气氛中导入溅射气体,对配置在所述真空气氛中并且含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al的溅射靶材进行溅射,在所述基体的表面形成与所述靶材相同组成的所述合金薄膜;以及导电膜形成工序,在所述合金薄膜的表面形成Cu的体积含有率比所述合金薄膜多的所述导电膜。
此外,本发明是一种装载装置的制造方法,其中,所述导电膜形成工序具有生长工序,在所述生长工序中,将形成有所述合金薄膜的所述基体浸渍到电镀液中,相对于所述电镀液而对所述合金薄膜施加负电压,使所述电镀液所含有的包括铜的金属的正离子附着于所述合金薄膜的表面而使所述导电膜生长。
此外,本发明是一种装载装置的制造方法,其中,具有蚀刻工序,在所述蚀刻工序中,使在所述合金薄膜形成工序中形成的所述合金薄膜与一种蚀刻液接触,使与所述蚀刻液接触的部分的所述合金薄膜溶解并除去,对所述合金薄膜进行图案化。
此外,本发明是一种溅射靶材,其中,具有含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al的合金组成并被溅射,在树脂露出的基体的表面形成所述合金组成的合金薄膜。
发明效果
在基体的表面形成合金薄膜,在合金薄膜的表面形成铜的含有量多的导电膜,因此,由于导电膜不与树脂接触并且与合金薄膜之间的密合性高,所以导电膜不会从基体剥离。
能够通过一种蚀刻液对合金薄膜进行蚀刻,因此,能够将分离配置的铜膜利用一次蚀刻工序使用一种蚀刻液来形成被图案化的布线膜。
附图说明
图1是用于说明本发明的装载装置的图。
图2是用于说明用于形成装载装置的溅射装置的图。
图3(a)~(d)是用于说明本发明的装载装置的制造工序的图(1)。
图4(e)~(g)是用于说明本发明的装载装置的制造工序的图(2)。
图5(a)~(d)是用于说明现有技术的装载装置的制造工序的图。
图6是用于说明基体的图。
图7是示出现有技术的装载装置的图。
图8是密合力的测定值的图表。
具体实施方式
图1的符号10表示本发明的装载装置,符号20表示装载装置10被电连接的底板(motherboard)。
该装载装置10具有支承基板14和分别配置于支承基板14的两面的第一、第二多层基板11、12,第一、第二多层基板11、12分别具有多个单层基板111~113、121~123。
当将各单层基板111~113、121~123之中靠近支承基板14的那方称为下层、将远的那方称为上层时,其他的单层基板111、112、121、122或支承基板14位于各单层基板111~113、121~123的下一层的位置,在图4(g)中示出了第一多层基板11的最上层的单层基板113和该单层基板113的下一层的单层基板112的一部分。
各单层基板111~113、121~123的结构是相同的,这些单层基板111~113、121~123分别具有:板状的基体3、在基体3形成的多个连接孔2、配置于基体3的单侧的表面(连接孔2的内周面和底面除外)的多个布线膜9、以及填充各连接孔2的金属插塞8。连接孔2为形成在基体3并且贯通基体3的表面和背面之间的贯通孔。
支承基板14具有:由树脂构成的树脂基板14a、形成在树脂基板14a的多个支承基板贯通孔14b、填充各支承基板贯通孔14b的内部的连接体14c、以及配置在树脂基板14a的两面的多个布线膜14d。连接体14c具有导电性,与至少一个布线膜14d电连接。
各单层基板111~113、121~123的金属插塞8与具有该金属插塞8位于的连接孔2的基体3的布线膜9在设置有布线膜9的表面电连接。
而且,各单层基板111~113、121~123的连接孔2位于下层的单层基板111、112、121、122的布线膜9或支承基板14的布线膜14d上,各单层基板111~113、121~123的金属插塞8与下层的单层基板111、112、121、122的布线膜9或支承基板14的布线膜14d电连接。
因此,第一、第二多层基板11、12的最上层的单层基板113、123的布线膜9分别与支承基板14的一个面的布线膜14d和另一个面的布线膜14d的任一个电连接,支承基板14的两面的布线膜14d之间经由连接体14c连接,因此,最上层的单层基板113、123的布线膜9与布线膜9之间也通过金属插塞8和连接体14c彼此电连接。
底板20具有底板主体20a和配置在底板主体20a上的布线膜20b。
在第一多层基板11的最上层的单层基板113的布线膜9固定有半导体装置13的端子13b,第二多层基板12的最上层的单层基板123的布线膜9经由金属体24与底板20的布线膜20b电连接。
半导体装置13的端子13b与配置在半导体装置主体13a的内部的半导体元件的集成电路电连接,因此,集成电路经由装载装置10和金属体24与底板20的布线膜20b电连接。
当对这样的各单层基板111~113、121~123的金属插塞8和布线膜9进行说明时,首先,各单层基板111~113、121~123的基体3通过由树脂构成的基板来构成,或者,由在编有玻璃纤维的布状基板中浸渍有树脂的复合材料来构成。
关于图6的基体3,在树脂25中包括玻璃纤维26,在该基体3的表面和连接孔2的内周面,通过树脂25的表面和玻璃纤维26的表面构成,并露出树脂25和玻璃纤维26。
金属插塞8具有与连接孔2的内周表面接触地配置的合金薄膜4和与该合金薄膜4的表面接触地配置的导电膜6。此外,布线膜9分别具有与基体3的表面接触地配置的合金薄膜5和与该合金薄膜5的表面接触地配置的导电膜7。
合金薄膜4、5在基体3的表面或连接孔2的内周表面至少与构成基体3的树脂接触,在基体3含有玻璃纤维的情况下,与构成基体3的树脂和玻璃纤维接触。
对上述装载装置10的制造工序进行说明。在此,已经在支承基板14的单面形成有第二多层基板12,在相反的面形成而配置有成为最上层的单层基板113以外的单层基板111、112。
图3(a)示出该状态下的在制基板31,在表面露出该在制基板31的最上层的单层基板112。
首先,如该图(b)所示那样将基体3粘贴在该单层基板112的表面上。
关于粘贴的基体3,可以在粘贴之前形成连接孔2,也可以在粘贴基体3之后形成连接孔2。
在该状态下的在制基板32中,在成为最上层的基体3的连接孔2的底面露出下一层的单层基板112的布线膜9,接着,在基体3的表面以及连接孔2的内周侧面和底面形成合金薄膜4、5。
在图2中示出形成合金薄膜4、5的溅射装置50。
该溅射装置50具有:搬出搬入室51a、前处理室51b、以及成膜室51c。
真空排气装置58a~58c分别连接于各室51a~51c,关闭各室51a~51c之间的闸门阀59a、59b,使真空排气装置58b、58c工作来对前处理室51b的内部和成膜室51c的内部进行真空排气,在前处理室51b的内部和成膜室51c的内部分别形成了真空气氛。
在搬出搬入室51a的内部配置有输送装置54,将基体3露出的在制基板32搬入到搬出搬入室51a的内部并安装于输送装置54。
关闭搬出搬入室51a的门,将内部气氛与大气隔断并使真空排气装置58a工作来对搬出搬入室51a的内部进行真空排气。
在搬出搬入室51a的内部配置有加热装置56,一边进行真空排气一边通过加热装置56对配置在输送装置54的在制基板32进行加热。
当在制基板32被升温至规定温度之后,打开闸门阀59a,将在制基板32与输送装置54一起从搬出搬入室51a的内部移动到前处理室51b的内部。
在前处理室51b的内部配置有离子枪57,当在关闭搬出搬入室51a与前处理室51b之间的闸门阀59a之后从气体导入系统向离子枪57供给稀有气体(在此为Ar)时,在离子枪57的内部生成稀有气体离子。将所生成的稀有气体的离子放出到前处理室51b的内部。
当在制基板32的基体3在前处理室51b的真空气氛中被露出并搬入到前处理室51b内时,被朝向离子枪57,并且稀有气体离子被放出。稀有气体离子被照射到基体3的表面、连接孔2的内周侧面、以及在连接孔2的底面露出的下层的单层基板112的导电膜7的表面,经照射的部分被清洁而成为活性的状态。
当照射离子规定时间时结束前处理,打开与成膜室51c之间的闸门阀59b,将进行了前处理的在制基板32与输送装置54一起从前处理室51b的内部移动到成膜室51c的内部,关闭闸门阀59b。
在成膜室51c的内部配置有靶材55。
该靶材55为含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al的靶材。
在成膜室51c的内部设置有气体放出装置53,一边继续通过真空排气装置58c对成膜室51c的内部进行真空排气来维持真空气氛一边从气体供给装置52向气体放出装置53供给溅射气体(氩气等稀有气体),使溅射气体从气体放出装置53放出到成膜室51c的内部并对靶材55施加电压来生成溅射气体的等离子体。
当经前处理的基体3的表面被做成与靶材55对面并且通过生成的等离子体对靶材55进行溅射时,溅射粒子附着于基体3的经前处理的表面,Cu、Ni和Al的含有率与靶材55相同的合金薄膜在该表面生长。
图3(c)的符号33为该合金薄膜15被形成为规定膜厚的在制基板,在合金薄膜15中,Cu、Ni和Al的含有率分别为比50原子%多的含有率、5原子%以上30原子%以下的含有率、3原子%以上10原子%以下的含有率,即,合金薄膜15为与靶材55相同的组成的薄膜。
合金薄膜15与基体3的表面(连接孔2的内周面除外。)、连接孔2的内周面、以及连接孔2的底面的导电膜7接触,在连接孔2的底面与下一层的单层基板112的布线膜9接触并电连接。下一层的单层基板112的布线膜9由合金薄膜5和导电膜7构成。
再有,由于最上层的合金薄膜15形成于被离子枪57照射离子后的表面,所以,当与未照射的情况相比时,密合强度变高。
在合金薄膜15被形成为规定膜厚之后,停止向靶材55的电压施加和溅射气体导入,结束溅射。
接着,打开闸门阀59a、59b,形成了合金薄膜15的在制基板33通过前处理室51b,移动到内部被做成真空气氛的搬出搬入室51a。
在关闭闸门阀59a、59b之后,向搬出搬入室51a导入气体,在搬出搬入室51a的内部变为大气压之后,从搬出搬入室51a取出形成了合金薄膜15的在制基板33。
接着,如图3(d)所示那样,在合金薄膜15的表面配置被图案化的抗蚀膜28。
在该抗蚀膜28中,在最上层的基体3的各连接孔2的上方和该基体3的表面上的合金薄膜15的规定位置的上方形成有开口29,在开口29的底面下露出被配置在各连接孔2的底面和内周侧面的合金薄膜15或者位于基体3的表面上的合金薄膜15。
在该状态下的在制基板33的开口29底面下露出的合金薄膜15的表面与合金薄膜15接触地形成由Cu的含有率(原子%)比合金薄膜15高且电阻率小的材料构成的导电膜。
关于导电膜的具体的形成方法,例如,将合金薄膜15在抗蚀膜28的开口29底面和基体3的表面的规定位置上露出的状态下的在制基板33浸渍到包括铜离子的电镀液中,使露出的合金薄膜15与电镀液接触,将被浸渍到电镀液中的铜电极和合金薄膜15与电源连接,使电源工作来经由铜电极对合金薄膜15与电镀液之间施加电压,使电镀液中的正的金属离子附着于合金薄膜15的与电镀液接触的部分而使含有比合金薄膜15多的铜的导电膜生长,从而制作如图4(e)所示那样在连接孔2上的开口29的底面下和基体3的表面上的开口29的底面下形成有导电膜6、7的在制基板34。
通常,与溅射法相比电镀法的生长速度更大,与通过溅射法形成的合金薄膜15的膜厚相比通过电镀法形成的导电膜6、7的膜厚更厚,在该在制基板34中,形成于连接孔2内的合金薄膜15的表面的导电膜6填充连接孔2的内部,其上部位于比基体3的表面上的合金薄膜15的表面上方。
接着,如图4(f)所示那样,当剥离抗蚀膜28时,在导电膜6、7露出的部分之间,合金薄膜15露出。
连接孔2的内部的导电膜6与基体3的表面上的导电膜7连接,但是,存在与基体3的表面上的导电膜7彼此分离的导电膜7,不过,在剥离了抗蚀膜28的状态下,各导电膜6、7为通过合金薄膜15彼此电连接的状态。
接着,当将该状态下的在制基板34浸渍到对铜进行蚀刻的蚀刻液中时,露出且与蚀刻液接触的部分的合金薄膜15溶解于蚀刻液而被蚀刻除去,如图4(g)所示那样,在合金薄膜15被除去的部分,位于合金薄膜15之下的基体3的表面露出,而形成导电膜6、7被图案化的最上层的单层基板113。
在各单层基板111~113、121~123中,在连接孔2的内部,通过连接孔2的内部的导电膜6和位于该导电膜6与连接孔2的内周面之间的合金薄膜4来构成金属插塞8,在基体3上,通过导电膜7和位于该导电膜7之下的合金薄膜5来构成布线膜9。由形成在连接孔2的内周面的合金薄膜4所包围的空间被导电膜6填充,因此,连接孔2被金属插塞8填充。
对在基体3的表面露出的树脂,纯铜的薄膜的密合性不好。
在本申请发明中,在使与树脂接触的合金薄膜4、5的含有比50原子%多的Cu的薄膜材料如下述实验所示那样含有Cu以外的元素来测定密合力时,含有5原子%以上30原子%以下的Ni并且含有3原子%以上10原子%以下的Al的薄膜材料与纯铜或氧化铜的薄膜相比,对树脂的密合性比铜薄膜的密合性高。
特别地,关于与环氧树脂的密合性,即使使铜薄膜含有Mg,密合性也不会提高,此外,即使使铜薄膜含有氧,密合性也不会提高,但是,关于本发明的布线膜9,合金薄膜4、5与树脂之间的密合性提高。
此外,由于该合金薄膜4、5的铜含有率比50原子%大,所以与纯铜的薄膜的密合性也高,金属插塞8或布线膜9不会从基体3剥离,此外,导电膜6、7与合金薄膜4、5相比,铜的含有率高,因此,导电膜6、7也不会从合金薄膜4、5剥离。
实施例
在铜靶材上配置Ni颗粒(pellet)、Al颗粒,通过溅射法在由含有玻璃纤维的环氧树脂构成的基体3的进行了前处理的表面形成组成不同的合金薄膜,通过电镀法在合金薄膜的表面形成纯铜的导电膜,对由该合金薄膜和导电膜这二层构成的布线膜的密合性进行测定。合金薄膜的组成除了Ni和Al以外,还包括不可避免地含有的杂质和铜,杂质的含有量小,因此,可以说在该合金薄膜中,除了Ni和Al以外还由铜构成。合金薄膜的膜厚为500nm,导电膜的膜厚为30μm。
关于密合性,将形成有由合金薄膜和导电膜构成的布线膜的基体3的一部分切出并在切出部分保持从基体3剥离了的布线膜的端部,测定以一定速度(20mm/min)向上方拿起以使其剥离时的力。当将该力设为密合力时,下述表1为实验的组成的合金薄膜的密合力的测定结果,表1中的“测定值”的栏为合金薄膜的每单位宽度(cm)的值。
[表1]
在使用Ti薄膜作为密合层并且在Ti薄膜上形成铜膜的布线膜的情况下,密合力为800gf/cm。
在表1的“剥落强度”的栏中,由于将与使用了Ti薄膜的布线膜同等以上的布线膜作为合格品,所以将“测定值”的栏的值为800以上的情况作为能够使用的合格品而记入“O”。此外,将“测定值”的栏的值为450以下的情况作为不能使用而记入“×”,将比450大且比800小的情况作为不应使用而记入“△”。
再有,关于添加元素的含有率,Ni和Al为零原子%的情况为由纯铜薄膜构成的合金薄膜的情况(测定值为220gf/cm)。
根据表1的测定结果,可知:为了使剥离强度的值为800以上而需要Ni为5原子%以上30原子%以下并且Al为3原子%以上10原子%以下。
图8是表1的测定结果的图表,处于虚线以上的位置的点所示的组成包括在本发明中。
再有,在作为比较对象而测定含有2原子%的Mg、含有8原子%的Al、剩下由Cu构成的布线膜的密合力时,为320gf/cm。根据此情况,可知:与添加了Al和Ni的合金膜相比,在添加了Al和Mg的合金膜中,密合力的提高较小。
再有,上述基体3是由含有玻璃纤维的环氧树脂构成的硬质的基板,但是,也可以是环氧树脂以外的树脂。此外,不含有玻璃纤维而含有树脂的基体也包括在本发明的基体3中。此外,基体3也可以是由软质树脂构成而具有柔软性的膜。
附图标记的说明
2……连接孔
3……基体
4、5……合金薄膜
6、7……导电膜
8……金属插塞
9……布线膜
10……装载装置
55……靶材。
Claims (6)
1.一种装载装置,具有基体和至少与在所述基体的表面露出的环氧树脂接触且形成为规定图案的布线膜,并使电子部件与所述布线膜电连接而使其装载在所述基体上,其中,
所述布线膜具有:
合金薄膜,含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al,与所述基体的表面接触;以及
导电性的导电膜,与所述合金薄膜的表面接触,含有比所述合金薄膜多的Cu。
2.根据权利要求1所述的装载装置,其中,
所述基体含有玻璃纤维,
在所述基体的表面露出所述环氧树脂和所述玻璃纤维。
3.根据权利要求2所述的装载装置,其中,
在所述基体形成有贯通表面和背面之间的连接孔,在所述连接孔的内周面露出所述环氧树脂和所述玻璃纤维,
所述合金薄膜与所述连接孔的内周面接触,
在由位于所述连接孔的内周面的所述合金薄膜所包围的部分,与所述合金薄膜接触地填充有所述导电膜。
4.一种装载装置的制造方法,制造装载装置,所述装载装置具有基体和形成为规定图案的布线膜并使电子部件与所述布线膜电连接而使其装载在所述基体上,其中,
所述布线膜具有:
合金薄膜,至少与在所述基体的表面露出的环氧树脂接触;以及
导电性的导电膜,与所述合金薄膜接触地配置,
所述装载装置的制造方法具有:
合金薄膜形成工序,在真空气氛中配置所述基体,在所述真空气氛中导入溅射气体,对配置在所述真空气氛中并且含有比50原子%多的Cu、含有5原子%以上30原子%以下的Ni、含有3原子%以上10原子%以下的Al的溅射靶材进行溅射,在所述基体的表面形成与所述靶材相同组成的所述合金薄膜;以及
导电膜形成工序,在所述合金薄膜的表面形成Cu的体积含有率比所述合金薄膜多的所述导电膜。
5.根据权利要求4所述的装载装置的制造方法,其中,所述导电膜形成工序具有生长工序,在所述生长工序中,将形成有所述合金薄膜的所述基体浸渍到电镀液中,相对于所述电镀液而对所述合金薄膜施加负电压,使所述电镀液所含有的包括铜的金属的正离子附着于所述合金薄膜的表面而使所述导电膜生长。
6.根据权利要求5所述的装载装置的制造方法,其中,具有蚀刻工序,在所述蚀刻工序中,使在所述合金薄膜形成工序中形成的所述合金薄膜与一种蚀刻液接触,使与所述蚀刻液接触的部分的所述合金薄膜溶解并除去,对所述合金薄膜进行图案化。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03236952A (ja) * | 1989-12-13 | 1991-10-22 | Bridgestone Corp | ゴムの複合化方法 |
JP2004193546A (ja) * | 2002-10-17 | 2004-07-08 | Mitsubishi Materials Corp | 半導体装置配線シード層形成用銅合金スパッタリングターゲット |
WO2009131035A1 (ja) * | 2008-04-25 | 2009-10-29 | 株式会社アルバック | 薄膜トランジスタの製造方法、薄膜トランジスタ |
CN102550138A (zh) * | 2009-09-28 | 2012-07-04 | 京瓷株式会社 | 结构体及其制造方法 |
JP2013133489A (ja) * | 2011-12-26 | 2013-07-08 | Sumitomo Metal Mining Co Ltd | Cu合金スパッタリングターゲット、この製造方法及び金属薄膜 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05308107A (ja) * | 1991-07-01 | 1993-11-19 | Sumitomo Electric Ind Ltd | 半導体装置及びその製作方法 |
JPH08332697A (ja) | 1995-06-08 | 1996-12-17 | Mitsui Toatsu Chem Inc | 金属ポリマーフィルム |
JP4247863B2 (ja) * | 1999-07-12 | 2009-04-02 | ソニー株式会社 | 電子部品用金属材料、電子部品用配線材料、電子部品用電極材料、電子部品、電子機器、金属材料の加工方法及び電子光学部品 |
US6871396B2 (en) * | 2000-02-09 | 2005-03-29 | Matsushita Electric Industrial Co., Ltd. | Transfer material for wiring substrate |
JP3754011B2 (ja) * | 2002-09-04 | 2006-03-08 | デプト株式会社 | 電子部品用金属材料、電子部品、電子機器、金属材料の加工方法、電子部品の製造方法及び電子光学部品 |
JP4299601B2 (ja) * | 2003-01-23 | 2009-07-22 | 京セラ株式会社 | 多層配線基板 |
JP4271684B2 (ja) * | 2003-10-24 | 2009-06-03 | 日鉱金属株式会社 | ニッケル合金スパッタリングターゲット及びニッケル合金薄膜 |
JP4567091B1 (ja) * | 2009-01-16 | 2010-10-20 | 株式会社神戸製鋼所 | 表示装置用Cu合金膜および表示装置 |
JP6135275B2 (ja) * | 2013-04-22 | 2017-05-31 | 三菱マテリアル株式会社 | 保護膜形成用スパッタリングターゲット |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03236952A (ja) * | 1989-12-13 | 1991-10-22 | Bridgestone Corp | ゴムの複合化方法 |
JP2004193546A (ja) * | 2002-10-17 | 2004-07-08 | Mitsubishi Materials Corp | 半導体装置配線シード層形成用銅合金スパッタリングターゲット |
WO2009131035A1 (ja) * | 2008-04-25 | 2009-10-29 | 株式会社アルバック | 薄膜トランジスタの製造方法、薄膜トランジスタ |
CN102550138A (zh) * | 2009-09-28 | 2012-07-04 | 京瓷株式会社 | 结构体及其制造方法 |
JP2013133489A (ja) * | 2011-12-26 | 2013-07-08 | Sumitomo Metal Mining Co Ltd | Cu合金スパッタリングターゲット、この製造方法及び金属薄膜 |
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