CN104682701A - Voltage booster circuit - Google Patents

Abstract

The invention discloses a booster circuit, comprising: a power rail for providing a supply voltage; a switching transistor for controlling an output of a boosted voltage signal outputted from a source of the switching transistor; and a timing and voltage control circuit for generating an Equalization signal to be applied to the gate of the switching transistor. The EQ signal has a level, which is an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamp level between the EQ low level and the EQ high level.

Description

boost circuit

technical field

The present invention relates to a boosting circuit, and in particular to a boosting circuit with a control circuit for avoiding the breakdown of the boosting circuit, and a method for avoiding the breakdown of the boosting circuit.

Background technique

In a semiconductor circuit, it may sometimes be necessary to apply a specific voltage value to a certain portion of the semiconductor circuit (such as a specific substrate or a word line) in order for the semiconductor circuit to function correctly. In some cases, the specific voltage is a relatively high voltage. This high voltage can be generated by a charge pump circuit, which boosts a relatively low input voltage to a relatively high output voltage. In general, charge pump circuits need to work with frequency signals that have higher voltage levels than those normally used in other parts of the semiconductor circuit. For example, if the supply voltage V _DD on the power rail of the semiconductor circuit is about 1.8V, the voltage level of the frequency signal in the semiconductor circuit is also about 1.8V. In order for the charge pump circuit to generate a voltage higher than the supply voltage V _DD , a high voltage frequency signal having a voltage level approximately twice the supply voltage V _DD (ie approximately 3.6V) is required.

The boost circuit can be used to "boost" the voltage of an input clock signal and generate a high voltage clock signal (ie, a boosted clock signal) having a level approximately twice the supply voltage V _DD . The boost circuit may include a plurality of semiconductor devices, including Field-Effect Transistors (FETs), such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). When the voltage of the input frequency signal is boosted higher than V _DD , a boosted high voltage approximately twice the supply voltage V _DD may also be applied to one or more FETs.

Sometimes, a semiconductor circuit may need to switch between a low V _DD condition and a high V _DD condition (eg, between an operating condition where V _DD is about 1.8V and an operating condition where V _DD is about 3.3V). During operation when V _DD is about 3.3V, the boost frequency signal is about 6.6V, which may be higher than the breakdown voltage of one or more FETs in the boost circuit, thus causing one or more FETs to collapse.

Contents of the invention

According to the present invention, a boost circuit is provided. The boost circuit includes: a power rail for providing a supply voltage; a switch transistor for controlling the output of a boost signal, and the boost signal is output from the source of the switch transistor; and a timing and voltage control circuit for An EQ signal is generated to be applied to the gate of the switching transistor. The EQ signal has a level which is an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamp level between the EQ low level and the EQ high level.

Also according to the present invention, a method for controlling the output of a boost signal is provided. The method includes generating an EQ signal having a level of an EQ high level, an EQ low level lower than the EQ high level, and an EQ low level between the EQ low level and the EQ high level One of the EQ clamping levels. The method further includes applying an EQ signal to a gate of a switch transistor to control the output of the boost signal.

The features and advantages according to the invention will be set forth in part in the following description, and in part will be obvious from the description, or can be learned by practice of the description. The features and advantages will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

It should be understood that both the above-mentioned general description and the following detailed description are only for illustration and description of the present invention, and do not limit the scope of claims of the present invention.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Description of drawings

FIG. 1 is a diagram illustrating a boost circuit according to an exemplary embodiment.

FIG. 2 is a waveform diagram of the input clock signal CLK, the first clock signal PCLK1 and the second clock signal PCLK2 according to an exemplary embodiment.

FIG. 3 is a circuit diagram of a voltage boosting block of the boosting circuit according to an exemplary embodiment.

FIG. 4 is a waveform diagram of the first boosted source signal BST1 , the second boosted source signal BST2 , the first boosted signal BT1 and the second boosted signal BT2 according to an exemplary embodiment.

FIG. 5 is a diagram illustrating a segment of a timing and voltage control block of a boost circuit according to an exemplary embodiment.

FIG. 6 shows waveforms of the first clock signal PCLK1 , the delayed first clock signal PCLK1 , the first boost source signal BST1 and the first EQ input signal EQIN1 according to an exemplary embodiment.

FIG. 7 is a circuit diagram of an EQ generating element of a timing and voltage control block according to an exemplary embodiment.

8A and 8B illustrate waveform diagrams of the first EQ input signal EQIN1, the power control signal PWCTL, the first equalization signal EQ1, and the second equalization signal EQ2 during low V _DD operation according to an exemplary embodiment, and Waveform diagrams of the first EQ input signal EQIN1 , the second signal PB2 , the power control signal PWCTL , the first equalization signal EQ1 , and the second equalization signal EQ2 during high V _DD operation.

9A and 9B illustrate the first equalization signal _{EQ1 ,} the second equalization signal EQ2, the first boost source signal BST1, the second boost Waveform diagrams of the source signal BST2 , the first boosted signal BT1 , the second boosted signal BT2 , the first boosted clock signal CK1 and the second boosted clock signal CK2 .

【Symbol Description】

BST1: first boost source signal

BST2: second boost source signal

BT1: The first boost signal

BT2: Second boost signal

C1, C2: Capacitors

CK1: the first boost frequency signal

CK2: The second boost frequency signal

CLK: input frequency signal

EQ1: the first EQ signal

EQ2: Second EQ signal

EQIN1: The first EQ input signal

EQIN2: Second EQ input signal

M31 to M38: Transistors

M71 to M77: Transistors

PB1: First signal

PB2: second signal

PCLK1: the first frequency signal

PCLK2: second frequency signal

PWCTL: power control signal

V _BOOST : boost high level

V _BOOST -CK: boost high frequency level

V _CLAMP : EQ clamping level

V _DD : supply voltage

V _HIGH1 : first high level

V _HIGH2 : second high level

V _ref : Reference voltage

V _SHARE : voltage drop

100: Boost circuit

102: Non-overlapping frequency generation block

104: Timing and voltage control block

106: Voltage boost block

302: Power rail

304: ground terminal

500: section

502: Time delay element

503: Logic Circuits

504: AND grid

506: OR grid

508: EQ generating element

702: First Circuit Branch

704: second circuit branch

706: Third Circuit Branch

708: EQ output terminal

710: Inverter

Detailed ways

Embodiments in accordance with the present invention include a boost circuit capable of maintaining a high output voltage and a method for avoiding collapse of the boost circuit.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 1 illustrates an exemplary boost circuit 100 according to an embodiment of the present invention. The boost circuit 100 is used to generate a boosted frequency signal, which has a boosted high frequency level, which is higher than the high frequency level of the input frequency signal (the boosted high frequency level is, for example, about twice the input frequency signal high frequency level), where the high frequency level of the input frequency signal is approximately the same as the supply voltage V _DD . In some embodiments, as shown in FIG. 1 , the boost circuit 100 generates two boosted clock signals, namely a first boosted clock signal CK1 and a second boosted clock signal CK2 .

According to an embodiment of the present invention, the boost circuit 100 is configured to operate under both a low V _DD operating condition and a high V _DD operating condition, and to switch between the two operating conditions. As used in this specification, a low V _DD means such a V _DD will not cause the boosted high frequency level of the boosted frequency signal to be higher than the breakdown voltage of the electronic components in the boost circuit 100, while a high V _DD means such V _DD may cause the boost high frequency level of the boost frequency signal to be higher than the breakdown voltage of the electronic components in the boost circuit 100 . For example, the low V _DD can be about 1.65V to about 2V, and the high V _DD can be about 2.7V to about 3.6V. In some embodiments, the low V _DD may be approximately 1.8V and the high V _DD may be approximately 3.3V.

Please refer to FIG. 1 , the boost circuit 100 includes a non-overlapping frequency generation block 102 , a timing and voltage control block 104 and a voltage boost block 106 . The non-overlapping clock generating block 102 is used for generating a first clock signal PCLK1 and a second clock signal PCLK2 based on the input clock signal CLK.

FIG. 2 shows exemplary waveforms of the input clock signal CLK, the first clock signal PCLK1 and the second clock signal PCLK2. According to an embodiment of the present invention, the input frequency signal CLK, the first frequency signal PCLK1 and the second frequency signal PCLK2 all have a high level approximately equal to V _DD and a low level approximately equal to the ground voltage (that is, 0V), and the period is, for example, All are 40ns. Hereinafter, unless otherwise stated, the high level of a waveform is ideally considered to be about V _DD , but may be a little lower than V _DD , for example because of parasitic resistances. Also, the low level of a waveform is considered to be approximately 0V, but may be a little higher than 0V, for example due to parasitic resistance. The differences between the high level and V _DD and between the low level and 0V are small because they result from voltage drops such as parasitic capacitances. As shown in FIG. 2 , the first clock signal PCLK1 and the second clock signal PCLK2 do not overlap each other, that is, the first clock signal PCLK1 and the second clock signal PCLK2 do not go high at the same time. Within one cycle, the first frequency signal PCLK1 rises from low level to high level after a time delay after the input frequency signal CLK rises from low level to high level, and the first frequency signal PCLK1 falls from high level Going to low level is about the same time as the input frequency signal CLK falls from high level to low level. Similarly, the rise of the second frequency signal PCLK2 from the low level to the high level is after a time delay after the input frequency signal CLK falls from the high level to the low level, and the second frequency signal PCLK2 falls from the high level to the low level The level is about the same time as the input frequency signal CLK rises from low level to high level. Hereinafter, the transition of a waveform from one level to another is also referred to as the edge of the waveform. The transition of the waveform from low level to high level is also called the rising edge of the waveform, and the transition of the waveform from high level to low level is also called the falling edge.

Please refer to FIG. 1 again, the first frequency signal PCLK1 and the second frequency signal PCLK2 are input to the timing and voltage control block 104, and the timing and voltage control block 104 generates the first boost source signal BST1 and the second boost source signal BST2 is boosted by the voltage boost block 106 . The first boost source signal BST1 and the second boost source signal BST2 are also involved in controlling the operation of the voltage boost block 106 . The timing and voltage control block 104 further generates a first equalization (EQ) signal EQ1 and a second EQ signal EQ2 , which are also used to control the operation of the voltage boost block 106 . As will be discussed later in this specification, the first EQ signal EQ1 and the second EQ signal EQ2 are used to control the conduction and non-conduction operations of a switching element (such as a switching transistor) outputting a boost frequency signal.

FIG. 3 illustrates an exemplary voltage boosting block 106 according to an embodiment of the present invention. The exemplary voltage boosting block 106 shown in FIG. 3 has a "mirror" structure (ie, a symmetrical structure) including transistors M31 - M38 and capacitors C1 and C2 . Transistors M31-M38 are metal oxide semiconductor field effect transistors (MOSFETs), wherein transistors M31, M32, M35, M36, M37 and M38 are n-channel MOSFETs (n-MOS), and transistors M33 and M34 are p-channel MOSFETs (p -MOS). As will be seen from FIG. 3 and the discussion that follows in this specification, even during high VDD operation, for each of transistors M31, M32, M35, and M36, the voltage applied between the gate and source/drain is The voltage difference is relatively low, and the voltage difference does not exceed the breakdown voltage of the oxide, ie, the voltage at which the gate oxide of the transistor is destroyed. Hereinafter, unless otherwise specified, the oxide breakdown voltage of the transistor is also referred to as the breakdown voltage of the transistor. Therefore, for transistors M31, M32, M35, and M36, a thin oxide n-MOS with a lower threshold voltage can be used to reduce power consumption and charge sharing time.

As shown in FIG. 3 , the drains of transistors M31 and M32 are connected to power rail 302 , which provides a supply voltage V _DD . The transistors M31 and M32 form a charging path, and the charging path, together with the capacitors C1 and C2, takes the first boost source signal BST1 and the second boost source signal BST2 as inputs to generate the first boost signal BT1 and the second boost signal bt2. FIG. 4 shows exemplary waveforms of the first boosted source signal BST1 , the second boosted source signal BST2 , the first boosted signal BT1 and the second boosted signal BT2 . This specification will further discuss the generation of the first boost source signal BST1 and the second boost source signal BST2 later. It can be seen from FIG. 4 that when the second boost source signal BST2 rises from low level to high level, the first boost signal BT1 is charged to the first high level V _HIGH1 through the power rail 302 and maintained at this voltage level. level until the first boost source signal BST1 rises from low level to high level, at this time the first boost signal BT1 is boosted from the first high level V _HIGH1 to the boosted high level V _BOOST , boosting The high level V _BOOST may be approximately 1.8 times to approximately 2 times V _DD . Ideally, the first high level V _HIGH1 will be the same as V _DD . However, as mentioned above, due to the parasitic resistance and capacitance of the electronic components in the boost circuit 100 , the first high level V _HIGH1 is lower than V _DD . When the first boost source signal BST1 drops from a high level to a low level, the first boost signal BT1 drops from a boosted high level V _BOOST to a second high level V _HIGH2 . Likewise, because of parasitic resistance and capacitance, the second high level V _HIGH2 is higher than the ground level but lower than V _DD and the first high level V _HIGH1 . The change of the second boost signal BT2 over time is similar to that of the first boost signal BT1 but has a different phase, so it is not described in detail here.

Please refer to FIG. 3 again, the sources of transistors M37 and M38 are connected to the ground terminal 304, the drains of transistors M37 and M38 are connected to the sources of transistors M35 and M36, and the gates of transistors M37 and M38 are connected by the second Controlled by the boost source signal BST2 and the first boost source signal BST1. Furthermore, the gates of transistors M35 and M36 are connected to the power supply rail 302 , thus, transistors M35 and M36 are always on during operation of the boost circuit 100 . Transistors M35, M36, M37 and M38 form a discharge path. The discharge path is used to pull the first boosted frequency signal CK1 to a low level when the second boosted source signal BST2 rises to a high level to turn on the transistor M37. Similarly, the discharge path is also used to pull the second boosted frequency signal CK2 to a low level when the first boosted source signal BST1 rises to a high level to turn on the transistor M38 . Transistors M35 and M36 are inserted in the discharge path to avoid large peak discharge currents and to prevent transistors M37 and M38 from collapsing, respectively.

The transistors M33 and M34 serve as charge-sharing switching elements, and the charge-sharing switching elements respectively control the output of the first boosted clock signal CK1 and the second boosted clock signal CK2 . That is, the transistors M33 and M34 are switching transistors in the voltage boosting block 106 . For example, as shown in FIG. 3, when the second EQ signal EQ2 is at the level of turning on the transistor M33, the transistor M33 receives the first boost signal BT1 at its drain, and outputs the first boost frequency at its source. Signal CK1. Likewise, when the first EQ signal EQ1 is at a level that turns on the transistor M34, the transistor M34 receives the second boosted signal BT2 at its drain and outputs the second boosted frequency signal CK2 at its source. Exemplary waveforms of the first EQ signal EQ1 , the second EQ signal EQ2 , the first boosted clock signal CK1 and the second boosted clock signal CK2 will be described later in this specification.

As mentioned above, the first boost source signal BST1 , the second boost source signal BST2 , the first EQ signal EQ1 and the second EQ signal EQ2 are generated by the timing and voltage control block 104 . According to an embodiment of the present invention, the timing and voltage control block 104 includes two substantially identical segments. One of the two sections is used to generate the first boosted source signal BST1 and the first EQ signal EQ1 , and the other section is used to generate the second boosted source signal BST2 and the second EQ signal EQ2 . For example, FIG. 5 shows an exemplary section 500 of the timing and voltage control block 104, which is used to generate the first boost source signal BST1 and the first EQ signal EQ1. In the timing and voltage control block 104 , another section for generating the second boost source signal BST2 and the second EQ signal EQ2 is similar to the section 500 , so it is not depicted here.

As shown in FIG. 5 , the section 500 includes a time delay element 502 for generating a delayed signal based on an input signal. For example, the time delay element 502 delays the first clock signal PCLK1 to generate a delayed first clock signal PCLK1. That is, the output of the time delay element 502 (ie, the delayed first clock signal PCLK1 ) has a waveform similar to the first clock signal PCLK1 , but is delayed by, for example, about 2 ns. Both the first clock signal PCLK1 and the delayed first clock signal PCLK1 are input to a logic circuit 503 to generate a first boost source signal BST1 and a first EQ signal EQ1 . In some embodiments, as shown in FIG. 5 , the logic circuit 503 includes an AND gate 504 , an OR gate 506 and an EQ generating element 508 . Specifically, the delayed first clock signal PCLK1 is input to the AND gate 504 together with the first clock signal PCLK1 to generate the first boost source signal BST1. Similarly, the delayed first frequency signal PCLK1 is also input to the OR gate 506 together with the first frequency signal PCLK1 to generate the first EQ input signal EQIN1, and the first EQ input signal EQIN1 is then input to the EQ generating element 508 to generate the first EQ Signal EQ1.

FIG. 6 shows exemplary waveforms of the first clock signal PCLK1, the delayed first clock signal PCLK1, the first boost source signal BST1, and the first EQ input signal EQIN1, each of which is at a high level and a low level. transition between. It can be seen from FIG. 6 that within one cycle, the rising edge of the first boost source signal BST1 coincides with the rising edge of the delayed first clock signal PCLK1 . That is, when the delayed first clock signal PCLK1 rises from a low level to a high level, the first boost source signal BST1 rises from a low level to a high level at about the same time. The falling edge of the first boost source signal BST1 coincides with the falling edge of the first clock signal PCLK1 . That is, when the first clock signal PCLK1 drops from a high level to a low level, the first boost source signal BST1 drops from a high level to a low level at about the same time. Also, the rising edge of the first EQ input signal EQIN1 coincides with the rising edge of the first frequency signal PCLK1 , and the falling edge of the first EQ input signal EQIN1 coincides with the falling edge of the delayed first frequency signal PCLK1 . That is, the first EQ input signal EQIN1 rises before the first boost source signal BST1 rises and falls after the first boost source signal BST1 falls. One can notice that two edges that coincide with each other do not mean that they rise or fall at exactly the same time due to system delays. For example, the rising edge of the first boost source signal BST1 can be slightly behind the rising edge of the delayed first clock signal PCLK1 , and this delay is generally smaller than the intentional delay caused by the time delay element 502 .

FIG. 7 illustrates an exemplary EQ generating element 508 according to an embodiment of the present invention. The EQ generating element 508 includes a first circuit branch 702, a second circuit branch 704 and a third circuit branch 706, for generating different parts of the waveform of the first EQ signal EQ1, the first EQ signal EQ1 is output from the EQ output terminal 708 output. As shown in FIG. 7, the first circuit branch 702 and the second circuit branch 704 are connected between the power supply rail 302 and the EQ output terminal 708, and the third circuit branch 706 is connected between the ground terminal 304 and the EQ output terminal 708. .

In the example shown in FIG. 7, the EQ generating element 508 includes an inverter 710 and transistors M71-M77 controlled by different signals. In FIG. 7, transistors M71, M74, M75, and M76 are p-MOS, and transistors M72, M73, and M77 are n-MOS. The first circuit branch 702 includes a transistor M71. The second circuit branch 704 includes transistors M74, M75 and M76. The third circuit branch 706 includes transistors M72, M73 and M77.

According to an embodiment of the present invention, the EQ generating element 508 is configured to operate under both low V _DD operating conditions (eg, about 1.65V to about 2V) and high V _DD operating conditions (eg, about 2.7V to about 3.6V) Work. In the example shown in FIG. 7, transistors M72 and M76 are controlled by a power control signal PWCTL, which keeps transistor M72 on and transistor M76 off during operation under low V _DD operating conditions, while at high V DD During operation under _DD operating conditions transistor M72 is kept off and transistor M76 is turned on. That is, when the EQ generating element 508 is operating under the low V _DD operating condition, the second circuit branch 704 is cut off, thereby not affecting the generation of the first EQ signal EQ1 . When the EQ generating element 508 is operating under a high V _DD operating condition, the second circuit branch 704 kicks in to affect the generation of the first EQ signal EQ1 .

FIG. 8A shows the waveforms of the first EQ input signal EQIN1 , the power control signal PWCTL and the first EQ signal EQ1 when the exemplary EQ generating element 508 shown in FIG. 7 operates under the low V _DD operating condition. Although FIG. 8A does not show the waveform of the first signal PB1 (ie, the output of the inverter 710), those skilled in the art will know that the first signal PB1 is only the inversion signal of the first EQ input signal EQIN1. In this example, the power control signal PWCTL is set to a high level to keep the transistor M72 on and the transistor M76 off. As shown in FIG. 8A, under the low V _DD operating condition, the first EQ signal EQ1 has the level of EQ high level or EQ low level, and its level is the same as the high level and low level of the first EQ input signal EQIN1. Flat same. According to an embodiment of the present invention, the EQ high level is approximately equal to V _DD , and the EQ low level is approximately equal to 0V.

When the EQ generating element 508 is operating under a high V _DD operating condition, as shown in FIG. 8B , the power control signal PWCTL is set to a low level to keep the transistor M72 off and the transistor M76 on. According to an embodiment of the present invention, the transistor M74 in the second circuit branch 704 is controlled by a reference voltage Vref, so that the transistor M74 remains in a partially turned-on state, and there is a voltage drop V _SHARE (for example, about 2V) across The drain and source of transistor M74. Therefore, when the transistor M75 is turned on, the voltage applied to the EQ output terminal is not a voltage of about V _DD but a voltage of about V _DD -V _SHARE . That is, the transistor M74 controlled by the reference voltage V _ref acts as a voltage clamping element, clamping the voltage output from the EQ output terminal to the EQ clamping level V _CLAMP , which is approximately equal to V _DD −V _SHARE .

In some embodiments, other electronic components may be used as voltage clamping elements instead of _Vref controlled transistor M74. For example, a FET coupled to a diode, or a decoupling capacitor, can also be used as a voltage clamping element. Using a FET coupled to the diode can reduce the area of the boost circuit 100 because no circuit is needed to generate the reference voltage V _ref .

As mentioned above, during the high V _DD operation, the power control signal PWCTL is set to a low level, making the transistor M72 non-conductive during this operation, equivalent to the third circuit branch 706 not including the transistor M72 but only the transistor M73 and M77. It can be seen from FIG. 7 that both the transistor M77 in the third circuit branch 706 and the transistor M75 in the second circuit branch 704 are controlled by the same second signal PB2 (ie, the inverted signal of the second EQ input signal EQIN2). control. Since transistors M75 and M77 are of opposite types (in the example shown in FIG. 7, one is p-MOS and the other is n-MOS), they are sequentially turned on and off. That is, when the transistor M75 is turned on, the transistor M77 is not turned on, and vice versa. Likewise, the transistors M71 and M73 are also of the opposite type and are controlled by the same first signal PB1 (ie the inverse signal of the first EQ input signal EQIN1 ), so as to be sequentially turned on and off. That is, when the transistor M71 is turned on, the transistor M73 is not turned on, and vice versa. This mechanism ensures that during high V _DD operation, the first circuit branch 702, the second circuit branch 704 and the third circuit branch 706 are sequentially output to the EQ output terminal 708 to generate the level of the first EQ signal EQ1 in sequence as EQ high level (about V _DD ), EQ clamp level (about V _DD -V _SHARE ) and EQ low level (about 0V).

FIG. 8B shows an illustration of the first EQ input signal EQIN1, the second signal PB2, the power control signal PWCTL, and the first EQ signal EQ1 when the exemplary EQ generating element 508 shown in FIG. 7 operates under a high V _DD operating condition. waveform. According to an embodiment of the present invention, the second signal PB2 has a waveform similar to that of the first signal PB1 and is generated by another section of the timing and voltage control block 104 . That is, the second signal PB2 is substantially an inverted signal of the second EQ input signal EQIN2 . 8A and 8B also show the waveforms of the second EQ signal EQ2 during the low V _DD operation period and the high V _DD operation period for comparison.

The waveforms discussed above (ie, the first boost source signal BST1, the second boost source signal BST2, the first EQ signal EQ1, and the second EQ signal EQ2) are input to the voltage booster as shown in FIG. Block 106, for generating the first boosted clock signal CK1 and the second boosted clock signal CK2. _9A and _9B respectively illustrate the first EQ signal EQ1, the second EQ signal EQ2, the first boost source signal BST1, the second boost source signal BST2, the first boost Example waveforms of the voltage boost signal BT1, the second boost signal BT2, the first boost clock signal CK1 and the second boost clock signal CK2. When the first boosted signal BT1 is at the boosted high level V _BOOST , the first boosted clock signal CK1 is also at the boosted high frequency level V _BOOST −CK , which is approximately equal to the boosted high level V _BOOST . Actually, due to, for example, the parasitic resistance and capacitance of the transistor M33, the boosted high frequency level V _BOOST- CK at the first boosted clock signal CK1 may be lower than the boosted high level V _BOOST at the first boosted signal BT1 . Similarly, when the second boost signal BT2 is at the boost high level V _BOOST , the second boost frequency signal CK2 is also at the boost high frequency level V _BOOST -CK, which is approximately equal to the boost high level V _BOOST . Actually, due to, for example, the parasitic resistance and capacitance of the transistor M34, the boosted high frequency level V _BOOST -CK at the second boosted clock signal CK2 may be lower than the boosted high level V _BOOST at the second boosted signal BT2 .

It can be seen from FIG. 9B that during high V _DD operation, the time period during which the second EQ signal EQ2 is at the EQ clamping level V _CLAMP is to encompass (encompass) the first boosted frequency signal CK1 at the boosted high frequency level V _BOOST -CK time period. Likewise, the time period when the first EQ signal EQ1 is at the EQ clamping level V _CLAMP covers the time period when the second boosted frequency signal CK2 is at the boosted high frequency level V _BOOST -CK. That is, a voltage equal to the EQ clamp level V _CLAMP is applied whenever the output boost signal is at a boost high frequency level that would cause the switching element (i.e., the switching transistor in the example shown in Figure 3) to collapse To the gate of the switching transistor, this can reduce the voltage drop between the gate and the source of the switching transistor, thereby preventing the switching transistor from collapsing. According to an embodiment of the present invention, the EQ clamping level V _CLAMP can be controlled by controlling the voltage drop V _SHARE across a voltage clamping element (eg, transistor M74 shown in FIG. 7 ). The voltage drop V _SHARE across transistor M74 can be controlled by controlling the reference voltage V _ref .

For simplicity of illustration, each edge of each waveform shown in the drawings of the present invention is depicted as a straight vertical line. One can notice that the edges cannot be straight vertical lines but may be meandered, curved or slanted lines due to delays such as parasitic RC circuits, gate delays or frequency counter controlled delays. Furthermore, in the present invention, it is assumed that the voltage boost block 106 is symmetrical, so the outputs from the left and right halves of the voltage boost block 106 are similar to each other except that their respective phases are different. For example, as shown in FIG. 9A and FIG. 9B , the waveforms of the first boosted signal BT1 and the second boosted signal BT2 are identical to each other except for their respective phases, and the first boosted frequency signal CK1 and the second boosted frequency signal CK1 Compression frequency signals CK2 are identical to each other except for their respective phases. In practice, however, due to differences between identically labeled electronic components in the boost circuit 100 , the outputs from the left and right halves of the voltage boosting block 106 may be different from each other. For example, the boosted high level of the first boosted signal BT1 may be different from the boosted high level of the second boosted signal BT2, and the boosted high frequency level of the first boosted frequency signal CK1 may be different. The boosted high frequency level of the second boosted clock signal CK2.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. A step-up circuit, comprising: a power rail for providing a supply voltage; a switching transistor controlling the output of a boost signal, the switching transistor having a gate; and A timing and voltage control circuit for generating an equalization (Equalization, EQ) signal, the EQ signal is applied to the gate of the switching transistor, the EQ signal has a level, the level is an EQ high level One of level, an EQ low level and an EQ clamping level, the EQ low level is lower than the EQ high level, and the EQ clamping level is between the EQ low level and the EQ high level between. 2. The boost circuit according to claim 1, Wherein the boost signal has a boosted high level during a first time period, and has a low level during a second time period; The timing and voltage control circuit includes: a first circuit branch connected between the power rail and an output terminal coupled to the gate of the switching transistor, the first circuit branch is used to generate the EQ high level to the output terminal; a second circuit branch connected between the power rail and the output terminal, the second circuit branch is used to generate the EQ clamp level to the output terminal during a fourth time period; and A third circuit branch, connected between a ground terminal and the output terminal, the third circuit branch is used to generate the EQ low level to the output terminal during a fifth time period; Wherein, the switching transistor is not turned on when the EQ signal is at the EQ high level, and is turned on when the EQ signal is at the EQ low level or the EQ clamping level, and Wherein, the fourth time period covers the first time period. 3. The boost circuit according to claim 2, wherein: the first circuit branch includes a transistor that is turned on during the third time period such that the output terminal is electrically coupled to the power rail, and The EQ high level is equal to the supply voltage. 4. The boost circuit according to claim 2, wherein: The second circuit branch includes: a transistor that is turned on during the fourth time period; and a voltage clamping element electrically coupled to the transistor, the voltage clamping element clamps the voltage output from the output terminal to the EQ clamping level, and The EQ clamp level is lower than the supply voltage. 5. The boost circuit according to claim 4, wherein: the transistor is a first transistor, and The voltage clamping element includes a second transistor controlled by a reference voltage such that the second transistor is partially turned on and a voltage drop across the second transistor is high enough to cause the output terminal to output a voltage of is clamped at the EQ clamp level. 6. The boost circuit according to claim 1, further comprising a discharge path electrically coupled between the switching transistor and a ground terminal, the discharge path comprising: a discharge transistor, electrically coupled to the ground terminal, the discharge transistor is turned on to pull the boost signal to a low level; and A low-threshold transistor is electrically coupled between the discharge transistor and the switch transistor, and a gate of the low-threshold transistor is electrically coupled to the power rail. 7. The boost circuit according to claim 1, wherein: The boost signal is a first boost signal, the first boost signal has a first boost high level during a first time period, and has a first low level during a second time period, the first boost high level is higher than a breakdown voltage of the switching transistor, and The switch transistor is further used to control the output of a second boost signal, the second boost signal is output from the source of the switch transistor, the second boost signal has a second boost signal during a third time period The high level has a second low level during a fourth time period, the second boosted high level is lower than the breakdown voltage of the switching transistor. 8. A method of controlling the output of a boost signal, comprising: generating an EQ signal with a level, the level being one of an EQ high level, an EQ low level and an EQ clamping level, the EQ low level being lower than the EQ high level, the EQ clamping level is between the EQ low level and the EQ high level; and The EQ signal is applied to a gate of a switch transistor to control the output of the boost signal. 9. The method of claim 8, wherein: The boost signal has a boost high level during a first time period, and has a low level during a second time period, Generating this EQ signal involves: generating the EQ high level during a third time period, generating the EQ clamp level during a fourth time period, and generating the EQ low level during a fifth time period, Wherein applying the EQ signal to the gate of the switching transistor comprises: applying the EQ high level to the gate of the switch transistor during the third time period, so that the switch transistor is not turned on, applying the EQ clamp level to the gate of the switching transistor during the fourth time period to turn on the switching transistor, and applying the EQ low level to the gate of the switch transistor during the fifth time period to turn on the switch transistor, and The fourth time period covers the first time period. 10. The method of claim 8, further comprising: generating a boosted source signal to be boosted to generate the boosted signal; and An EQ input signal is generated for generating the EQ signal.