CN104681674A - GaN-based high-voltage direct-current LED insulation isolating process - Google Patents

Abstract

The present invention relates to a GaN-based high-voltage DC LED insulation isolation process, which includes the following steps: a. providing a sapphire substrate with an epitaxial layer, and defining a MESA pattern of an LED subunit on the epitaxial layer; b. using the above-mentioned MESA pattern Perform dry etching on the epitaxial layer to obtain the MESA mesa of the LED subunit; c, deposit an etching mask layer, and the etching mask layer covers the MESA mesa; d, use the pulsed laser spot ablation of the laser The epitaxial layer between the LED sub-unit MESA mesas and the etching mask layer to form isolation trenches between the MESA mesas of the LED sub-units to isolate the LED sub-units from each other through the isolation trenches; The pulsed laser spot ablates the impurities to smooth the surface of the side wall of the isolation trench; f, removing the above-mentioned etching mask layer. The invention can effectively improve the insulation and isolation performance among multiple LED sub-units, greatly improve the production efficiency, ensure the production yield, improve the performance of the high-voltage direct-current LED, and is safe and reliable.

Description

GaN-based HVDC LED Insulation and Isolation Technology

technical field

The invention relates to an isolation process, in particular to a GaN-based high-voltage DC LED insulation isolation process, belonging to the technical field of DC high-voltage LED manufacturing process.

Background technique

The key to the popularization of LED lighting lies in the development of high-efficiency, low-cost device structures. The integrated packaging (COB-LED) that has appeared in recent years is just one of the potential device structures. COB-LED is composed of multiple LEDs fixed on a large-area heat dissipation substrate (heat sink) and connected in series and parallel. COB-LED can significantly improve the heat dissipation problem, use low current drive to give full play to the advantages of high light efficiency of LED, and greatly save packaging cost compared with single LED packaging. Considering that the current mainstream COB-LED is composed of a single LED chip, it also has the following shortcomings: 1), each LED needs to be bonded and interconnected one by one, the production efficiency is relatively low, the equipment cost is increased, and the product yield is affected; 2) The arrangement of LED grains should not be too compact, which is not conducive to reducing the cost of packaging materials. In response to the above shortcomings, GaN-based high-voltage DC LEDs emerged as the times require.

Unlike the integration of COB-LEDs in the packaging process, GaN-based high-voltage DC LEDs are composed of multiple LED subunits. The insulation isolation and electrode interconnection of each unit are completed in the chip manufacturing process, which greatly improves production efficiency and yield; each subunit The arrangement between them is very compact (~10-20 μm), which can maintain the advantages of COB-LED, and can flexibly adapt to various existing packaging specifications to achieve the purpose of cost optimization.

Compared with traditional LEDs, the process of making GaN-based high-voltage DC LEDs is more complicated, and the insulation and isolation of LED subunits is the difficulty. The usual method is to use dry etching to remove the excess epitaxial layer between the subunits. Although this method can obtain insulation isolation, it is not an ideal method from the perspective of actual production, because the entire GaN-based LED epitaxy The layer thickness is generally around 6-10 μm (thicker μ-GaN needs to be grown to obtain better growth quality), which is bound to greatly increase the etching time, and requires additional deposition of a thick SiO ₂ mask, which greatly occupies ICP and PECVD equipment capacity; in addition, there are certain process uncertainties in the dry deep etching of GaN-based epitaxial layers, such as rough sidewall morphology, which may easily lead to failure of interconnect electrode adhesion; conductive substances may remain in the etching trench, resulting in device optoelectronic characteristics abnormal. In order to avoid the above potential problems as much as possible, the trench width is generally relaxed, causing the device to lose part of the light-emitting area. Therefore, it is urgent to develop a new GaN-based high-voltage DC LED insulation isolation processing method.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a GaN-based high-voltage DC LED insulation and isolation process, which can effectively improve the insulation and isolation performance between multiple LED subunits, greatly improve production efficiency, and ensure production yield , improve the performance of high-voltage DC LED, safe and reliable.

According to the technical solution provided by the present invention, the GaN-based high-voltage DC LED insulation isolation process includes the following steps:

a. Provide a sapphire substrate grown with an epitaxial layer, and define the MESA pattern of the LED subunit on the epitaxial layer;

b. Dry etching the epitaxial layer by using the above MESA pattern to obtain the MESA mesa of the LED sub-unit;

c. Depositing an etching mask layer on the MESA mesa forming the LED subunit, the etching mask layer covering the MESA mesa;

d. Use the pulsed laser spot of the laser to ablate the epitaxial layer and the etching mask layer between the MESA mesas of the LED subunits to form isolation trenches between the MESA mesas of the LED subunits, so as to connect the LED subunits to each other through the isolation trenches isolation;

e. Remove impurities in the isolation trench after being ablated by the pulsed laser spot to smooth the side wall surface of the isolation trench;

f. Removing the above etching mask layer.

The epitaxial layer includes a μ-GaN layer grown on a sapphire substrate, an N-GaN layer grown on the μ-GaN layer, a multiple quantum well grown on the N-GaN layer, and a multiquantum well grown on the P-GaN layer on multiple quantum wells.

Set the ITO transparent electrode, P-type metal electrode and passivation layer on the MESA mesa forming the isolation trench, the ITO transparent electrode covers the P-GaN layer, the passivation layer covers the ITO transparent electrode, and surrounds the outer wall of the epitaxial layer , the P-type metal electrode is electrically connected to the ITO transparent electrode through the passivation layer, and the N-type metal electrode is in ohmic contact with the N-GaN layer through the passivation layer; adjacent LED subunits on the sapphire substrate are connected in series through series metal electrodes, The series metal electrodes are filled in the isolation trench, one end of the series metal electrodes is electrically connected to the N-type metal electrode of one LED sub-unit, the other end of the series metal electrodes is electrically connected to the P-type metal electrode of another LED sub-unit, and the series metal electrodes The electrodes are insulated from the epitaxial layer by a passivation layer.

In the step a, a graphic mask layer is set on the epitaxial layer, and an etching window penetrating the graphic mask layer is set on the graphic mask layer, and the LED subunit is defined by using the etching window and the graphic mask layer MESA graphics.

The pattern mask layer includes a photoresist mask.

In the step b, the dry etching is ICP etching or RIE etching, and the epitaxial layer is dry etched to obtain an etched groove, and the etched groove extends downward from the P-GaN layer to the N-GaN layer Inside, the MESA mesas of the LED subunits on the sapphire substrate are isolated from each other by etching trenches.

The etching mask layer is a silicon dioxide layer deposited by PECVD, and the thickness of the etching mask layer is 150nm-200nm.

In the step d, the wavelength of the pulsed laser spot of the laser is 266nm or 355nm.

The present invention has following advantage:

1. Dry etching is only used to make the N-type electrode mesa of the MESA mesa, which is basically the same as the MESA etching process of conventional LEDs, and will not significantly occupy the capacity of dry etching equipment (ICP, RIE).

2. There is no need to occupy a large amount of PECVD production capacity, and an additional thick etching mask layer is deposited, which can be removed only after the etching mask layer is deposited by hot acid treatment.

3. Laser ablation forms an isolation trench, which is fast, efficient, and easy to control; and the width of the deep trench is narrow, which is conducive to reducing the loss of light-emitting area of the device and reducing the injection current density.

4. Thermal acid treatment of the isolation trench formed by laser ablation can completely remove residual ablation impurities and damage the epitaxial layer, ensuring that there is no leakage channel in the deep trench, and at the same time can smooth the surface of the side wall of the trench, which is conducive to reducing the failure of electrode interconnection probability.

Description of drawings

Fig. 1 is the structure of the GaN high voltage DC LED obtained in the present invention.

Fig. 2 is a schematic diagram of laser spot ablation in the present invention.

3 to 10 are cross-sectional views of the specific implementation steps of the insulation and isolation process of the present invention, wherein

Fig. 3 is a cross-sectional view of the present invention after growing an epitaxial layer on a sapphire substrate.

Fig. 4 is a cross-sectional view of the present invention after obtaining the MESA figure defining the LED sub-unit.

Fig. 5 is a cross-sectional view of the etching groove obtained in the present invention.

FIG. 6 is a cross-sectional view of the etching mask layer obtained in the present invention.

Fig. 7 is a cross-sectional view of the present invention after laser spot ablation.

8 is a cross-sectional view of the present invention after removing impurities after ablation to obtain a damaged epitaxial layer.

Fig. 9 is a cross-sectional view of the present invention after removing the damaged epitaxial layer.

FIG. 10 is a cross-sectional view of the isolation trench obtained in the present invention.

Fig. 11 is a schematic diagram of laser focused ablation in the present invention.

FIG. 12 is a schematic diagram of the present invention after performing partial-focus laser ablation.

Explanation of reference numerals: 1-P-GaN layer, 2-multiple quantum wells, 3-N-GaN layer, 4-μ-GaN layer, 5-sapphire substrate, 6-P-type metal electrode, 7-passivation layer , 8-ITO transparent electrode, 9-N-type metal electrode, 10-serial metal electrode, 11-LED subunit, 12-ablation debris, 13-damage epitaxial layer, 14-pattern mask layer, 15-etching Window, 16-etching trench, 17-etching mask layer, 18-isolation trench, 19-N electrode mesa and 20-epitaxy layer.

Detailed ways

The present invention will be further described below in conjunction with specific drawings and embodiments.

In order to effectively improve the insulation and isolation performance between multiple LED sub-units, greatly improve production efficiency, ensure production yield, and improve the performance of high-voltage DC LEDs, the insulation and isolation process of the present invention includes the following steps:

a. Provide a sapphire substrate 5 grown with an epitaxial layer 20, and define the MESA pattern of the LED subunit 11 on the epitaxial layer 20;

As shown in FIGS. 3 and 4 , the epitaxial layer 20 includes a μ-GaN layer 4 grown on the sapphire substrate 5, an N-GaN layer 3 grown on the μ-GaN layer 4, and an N-GaN layer grown on the The multiple quantum wells 2 on the N-GaN layer 3 and the P-GaN layer 1 grown on the multiple quantum wells 2 .

In order to define the MESA pattern of the LED subunit 11 on the epitaxial layer 20 , a pattern mask layer 14 is provided on the epitaxial layer 20 , and the pattern mask layer 14 includes a photoresist mask. The pattern mask layer 14 is provided with an etching window 15 penetrating the pattern mask layer 14, and the MESA pattern of the LED subunit 11 is defined by using the etching window 15 and the pattern mask layer 14, that is, spin-coating on the epitaxial layer 20 The photoresist is used to set the etching window 15 according to the position where the LED sub-unit 11 needs to be formed on the sapphire substrate 5, and the etching window 15 penetrates the pattern mask layer 14, so that the surface of the epitaxial layer 20 can be exposed through the etching window 15.

b. performing dry etching on the epitaxial layer 20 by using the above MESA pattern to obtain the MESA mesa of the LED subunit 11;

As shown in FIG. 5, the dry etching is ICP (Inductively Coupled Plasma) etching or RIE (Reactive Ion Etching) etching, and the dry etching epitaxial layer 20 obtains an etched trench 16, and the etched trench 16 extends downward from the P-GaN layer 1 into the N-GaN layer 3 , and the MESA mesas of the LED subunits 11 on the sapphire substrate 5 are isolated from each other by etching trenches 16 . In the embodiment of the present invention, the epitaxial layer 20 exposed by the etching window 15 is dry-etched to obtain an etching trench 16 at the position of the etching window 15, and the etching trench 16 penetrates the P-GaN layer 1, The multi-quantum well 2 and part of the N-GaN layer 3 are etched using photoresist as a mask to obtain the etched groove 16, so as to obtain the MESA mesa of the LED subunit 11 is a common technical means in this technical field. After the trench 16 is etched, the pattern mask layer 14 is removed so as to perform subsequent process steps, and the details are not repeated here.

c. Depositing an etching mask layer 17 on the MESA mesa forming the LED subunit 11, the etching mask layer 17 covering the MESA mesa;

As shown in FIG. 6, the etching mask layer 17 is a silicon dioxide layer deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the etching mask layer 17 is 150nm-200nm. The deposited etching mask layer 17 will fill in the etching trench 16 .

d. Using the pulsed laser spot of the laser to ablate the epitaxial layer 20 between the MESA mesas of the LED subunit 11 and the etching mask layer 17 to form an isolation trench 18 between the MESA mesas of the LED subunit 11 to pass through the isolation trench 18 isolating the LED subunits 11 from each other;

As shown in Fig. 7, Fig. 11 and Fig. 12, the laser may be a solid-state nanosecond laser, and the wavelength of the pulsed laser spot of the laser is 266nm or 355nm. Taking a pulsed laser spot with a wavelength of 355nm as an example, the epitaxial layer 20 and the etching mask layer 17 are ablated by the pulsed laser spot until the epitaxial layer 20 is ablated to the sapphire substrate 5. The frequency and moving speed were maintained at -450 μm, 23 μJ, 5 kHz, and 25 μm/s, respectively. As an emerging fast material processing technology, laser processing has achieved good results on difficult-to-process GaN-based materials and sapphire substrates, and has been widely used in the manufacturing process of GaN-based LED devices. As shown in FIG. 11 , in the case of focusing, the laser energy is focused on the sample surface, and the spot is sufficient to ablate through the epitaxial layer 20 and the sapphire substrate 5 . This is the laser processing mode adopted for conventional LED wafer division, and it is generally desired to ablate the sapphire substrate 5 to a certain depth. In the case of defocusing, the laser light spot on the sample surface is large, thereby reducing the laser energy density. At the same time, combined with the careful adjustment of other parameters, the selective ablation of the epitaxial layer 20 can be achieved without damaging the sapphire substrate 5 . During specific implementation, the working state of the laser is controlled, and the specific process of ablating the etching mask layer 17 and the epitaxial layer 20 without damaging the sapphire substrate 5 varies according to the working parameters of different lasers. The selection is well known to those skilled in the art and will not be repeated here.

e, removing impurities in the isolation trench 18 after being ablated by the pulsed laser spot, so as to smooth the side wall surface of the isolation trench 18;

As shown in Figures 7 and 8, when the etching mask layer 17 and the epitaxial layer 20 are ablated by the pulsed laser spot, it is bound to produce ablation impurities 12 and damage the epitaxial layer 13, because the pulsed laser spot will etch After the mask layer 17 and the epitaxial layer 20 are etched through, the isolation trench 18 can be obtained on the sapphire substrate 5, and the ablation impurities 12 are attached to the damaged epitaxial layer 13. In order to ensure the performance stability between the LED subunits 11 , the ablation impurities 12 and the damaged epitaxial layer 13 need to be removed to obtain a smooth sidewall of the isolation trench 18 , as shown in FIG. 9 .

In the embodiment of the present invention, the pulsed laser spot acts on the epitaxial layer 20 to cause pyrolysis of the GaN material, and at the same time generate ablation impurities 12, such as metal residues, and amorphous metal oxides and metal nitrides formed in the air environment, etc. . The specific process of removing the ablation impurities 12 and the damaged epitaxial layer 13 is: the wafer after laser ablation is etched in a mixed acid solution with a temperature of 200°C and a volume ratio of H ₃ PO ₄ :H ₂ SO ₄ =1:3 The by-products of laser ablation and the damaged epitaxial layer were removed within 10 minutes, and the concentrations of H ₂ SO ₄ and H ₃ PO ₄ solutions were 98% and 85%, respectively. The etching rate of the etching mask layer 17 in the mixed acid solution is very low enough to protect the underlying epitaxial layer 20 . Hot acid etching can completely remove the above products and eliminate the possibility of leakage. In addition, the surface morphology of the isolation trench 18 formed by ablation is uneven, and the epitaxial layer material near the sidewall surface is damaged. The damaged material can also be selectively etched with a hot acid solution to smooth the trench sidewall and reduce Surface leakage.

f. Removing the above-mentioned etching mask layer 17 .

As shown in Figure 10, since the etching mask layer 17 is a silicon dioxide layer, the etching mask layer 17 is removed by using HF solution or BOE solution, and the method for removing the etching mask layer 17 by using HF solution and BOE solution and The processes are well known to those skilled in the art and will not be repeated here.

In order to form a complete LED sub-unit 11, it is also necessary to set electrodes and interconnection after the insulation and isolation process is completed. The specific process of setting electrodes and interconnection can adopt the methods commonly used in this technical field, and the specific process is the present technology. It is well known to those in the field, and the structure of the formed GaN high voltage DC LED is shown in FIG. 1 .

As shown in FIG. 1, an ITO transparent electrode 8, a P-type metal electrode 6, an N-type metal electrode 8, and a passivation layer 7 are arranged on the MESA mesa forming the isolation trench 18, and the ITO transparent electrode 8 covers the P-GaN layer 1 The passivation layer 7 covers the P-GaN layer 1 and surrounds the outer wall of the epitaxial layer 20. The P-type metal electrode 6 passes through the passivation layer 7 and is electrically connected to the ITO transparent electrode 8, and the N-type metal electrode 9 passes through the passivation layer. The layer 7 is in ohmic contact with the N-GaN layer 3; the adjacent LED subunits 11 on the sapphire substrate 5 are connected in series through the series metal electrode 10, and the series metal electrode 10 is filled in the isolation trench 18, and one end of the series metal electrode 10 is connected to the The N-type metal electrode 9 of one LED subunit 11 is electrically connected, the other end of the series metal electrode 10 is electrically connected to the P-type metal electrode 6 of another LED subunit 11, and the series metal electrode 10 is connected to the epitaxial layer 20 through the passivation layer 7 Insulation isolation. The N-type metal electrode 9 is supported on the N-electrode mesa 19 , and the N-electrode mesa 19 is the surface of the N—GaN layer 3 .

The dry etching of the present invention is only used to make the N-type electrode mesa 19 of the MESA mesa, which is basically the same as the MESA etching process of the conventional LED, and will not obviously occupy the production capacity of the dry etching equipment (ICP, RIE). There is no need to occupy a large amount of PECVD production capacity, and an additional thick etching mask layer 17 is deposited, which can be removed only by treating the etching mask layer 17 with hot acid after deposition. The isolation trench 18 is formed by laser ablation, which is fast, efficient, and easy to control; and the width of the deep trench is narrow, which is beneficial to reduce the loss of the light emitting area of the device and reduce the injection current density. The isolation trench 18 formed by hot acid treatment and laser ablation can completely remove the residual ablation impurities 12 and damage the epitaxial layer 13, ensuring that there is no leakage channel in the deep trench, and at the same time smoothing the surface of the side wall of the trench, which is conducive to reducing the electrode interconnection. failure probability.

Claims (8)

1. a GaN base high voltage direct current LED insulation isolation technology, it is characterized in that, described insulation isolation technology comprises the steps:

(a), the Sapphire Substrate (5) providing growth to have epitaxial loayer (20), and at the upper MESA figure defining LED subelement (11) of described epitaxial loayer (20);

(b), utilize above-mentioned MESA figure to carry out dry etching to epitaxial loayer (20), to obtain the MESA table top of LED subelement (11);

(c), formed LED subelement (11) MESA table top on deposition-etch mask layer (17), described etching mask layer (17) covers on MESA table top;

(d), utilize laser pulsed laser spot ablation LED subelement (11) MESA table top between epitaxial loayer (20) and etching mask layer (17), to form isolated groove (18) between the MESA table top of LED subelement (11), to pass through isolated groove (18) by mutually isolated for LED subelement (11);

By foreign material after pulsed laser spot ablation in (e), removal isolated groove (18), with the sidewall surfaces of level and smooth isolated groove (18);

(f), remove above-mentioned etching mask layer (17).

2. GaN base high voltage direct current LED according to claim 1 insulate isolation technology, it is characterized in that: described epitaxial loayer (20) comprises the μ-GaN layer (4) be grown in Sapphire Substrate (5), the N-GaN layer (3) grown on described μ-GaN layer (4), grow Multiple Quantum Well (2) on described N-GaN layer (3) and the P-GaN layer (1) of growth in described Multiple Quantum Well (2).

3. GaN base high voltage direct current LED insulation isolation technology according to claim 2, it is characterized in that: on the MESA table top forming isolated groove (18), ito transparent electrode (8) is set, P type metal electrode (6) and passivation layer (7), ito transparent electrode (8) covers on P-GaN layer (1), passivation layer (7) covers on ito transparent electrode (8), and surround the outer wall of epitaxial loayer (20), P type metal electrode (6) is electrically connected with ito transparent electrode (8) through passivation layer (7), N-type metal electrode (9) is through passivation layer (7) and N-GaN layer (3) ohmic contact, the upper adjacent LED subelement (11) of Sapphire Substrate (5) is connected by series connection metal electrode (10), series connection metal electrode (10) is filled in isolated groove (18), one end of series connection metal electrode (10) is electrically connected with the N-type metal electrode (9) of a LED subelement (11), the other end of series connection metal electrode (10) is electrically connected with the P type metal electrode (6) of another LED subelement (11), and series connection metal electrode (10) is insulated by passivation layer (7) and epitaxial loayer (20) and isolated.

4. GaN base high voltage direct current LED insulation isolation technology according to claim 1, it is characterized in that: in described step (a), epitaxial loayer (20) arranges graphic mask layer (14), and the etching window (15) of through graphic mask layer (14) is set on described graphic mask layer (14), utilize etching window (15) and graphic mask layer (14) to define the MESA figure of LED subelement (11).

5. GaN base high voltage direct current LED insulation isolation technology according to claim 4, is characterized in that: described graphic mask layer (14) comprises photoresist mask.

6. GaN base high voltage direct current LED insulation isolation technology according to claim 2, it is characterized in that: in described step (b), dry etching is ICP etching or RIE etching, dry etching epitaxial loayer (20) obtains etching groove (16), described etching groove (16) extends downward in N-GaN layer (3) from P-GaN layer (1), mutually isolated by etching groove (16) between the MESA table top of the upper LED subelement (11) of Sapphire Substrate (5).

7. GaN base high voltage direct current LED insulation isolation technology according to claim 1, is characterized in that: described etching mask layer (17) is the silicon dioxide layer through PECVD deposition, and the thickness of described etching mask layer (17) is 150nm ~ 200nm.

8. GaN base high voltage direct current LED insulation isolation technology according to claim 1, it is characterized in that: in described step (d), the wavelength of the pulsed laser spot of laser is 266nm or 355nm.