CN104681564A - Display panel and display device using same - Google Patents

Abstract

The invention discloses a display panel and a display device using the same. The display panel comprises a thin film transistor substrate, a display medium and an opposite substrate. The opposite substrate is opposite to the thin film transistor substrate. The display medium is positioned between the thin film transistor substrate and the opposite substrate. The thin film transistor substrate comprises a substrate, a first electrode layer, a pixel electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, a channel layer and a protective layer. The first electrode layer and the pixel electrode layer are located on the substrate. The first insulating layer covers the first electrode layer and the pixel electrode layer. The second electrode layer is located on the first insulating layer. The second insulating layer covers the second electrode layer. The first through hole and the second through hole penetrate through the first insulating layer and the second insulating layer to expose the first electrode layer. The channel layer is located on the second insulating layer and filled in the first through hole and the second through hole to be electrically connected with the first electrode layer. The protective layer covers the channel layer.

Description

Display panel and display device using same

technical field

The present invention relates to a display panel and a display device using the same, and in particular to a top channel oxide semiconductor display panel and a display device using the same.

Background technique

Thin-Film Transistor (TFT) channel materials commonly used in display panels include polysilicon (polysilicon) and amorphous silicon (a-Si). The carrier mobility of polysilicon TFT components High (>100Vs/cm ² ), but the production cost is also high; although the production cost of amorphous silicon TFT element is low, the carrier mobility is also low (<1Vs/cm ² ).

Oxide semiconductors such as amorphous indium gallium zinc oxide (a-IGZO) have excellent electrical properties, such as carrier mobility between 10-20Vs/cm ² It can be used as an electronic channel layer, and gradually attracts considerable attention. However, such as bottom-gate back channel etch (back channel etch, BCE), channel protection (channel protect, CHP), or top-gate low temperature polysilicon (low temperature polysilicon) , LTPS) and other existing TFT designs, additional manufacturing processes such as chemical vapor deposition (chemical vapor deposition, CVD) or plasma (plasma) are required to form the channel layer, which is easy to cause oxygen in the oxide semiconductor The defect causes the start-up voltage V _gh to drift or the subthreshold swing (SS) is too large, which affects the characteristics of the oxide semiconductor electronic channel.

Contents of the invention

The object of the present invention is to provide a display panel and a display device thereof, which have good electron channel layer properties.

To achieve the above purpose, according to one aspect of the present invention, a display panel is provided. The display panel includes a thin film transistor substrate, a display medium and an opposite substrate. The opposite substrate is arranged relative to the thin film transistor substrate. The display medium is located between the TFT substrate and the opposite substrate. The thin film transistor substrate includes a substrate, a first electrode layer, a pixel electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, a channel layer and a protection layer. The first electrode layer and the pixel electrode layer are located on the substrate. The first insulating layer covers the first electrode layer and the pixel electrode layer. The second electrode layer is located on the first insulating layer. The second insulating layer covers the second electrode layer. The first through hole and the second through hole penetrate the first insulating layer and the second insulating layer to expose the first electrode layer. The channel layer is located on the second insulating layer and fills the first through hole and the second through hole to be electrically connected with the first electrode layer. A protective layer covers the channel layer.

According to another aspect of the present invention, a display device is provided, and the display device includes a display panel and a control circuit. The control circuit is coupled with the display panel. The display panel includes a thin film transistor substrate, a display medium and an opposite substrate. The opposite substrate is arranged relative to the thin film transistor substrate. The display medium is located between the TFT substrate and the opposite substrate. The thin film transistor substrate includes a substrate, a first electrode layer, a pixel electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, a channel layer and a protection layer. The first electrode layer and the pixel electrode layer are located on the substrate. The first insulating layer covers the first electrode layer and the pixel electrode layer. The second electrode layer is located on the first insulating layer. The second insulating layer covers the second electrode layer. The second insulating layer has a first through hole and a second through hole. The first through hole and the second through hole penetrate the first insulating layer and the second insulating layer to expose the first electrode layer. The channel layer is located on the second insulating layer and fills the first through hole and the second through hole so as to be electrically connected with the first electrode layer. A protective layer covers the channel layer.

By designing the channel layer on the top of the thin film transistor substrate, the display panel and the display device of the present invention can prevent the semiconductor characteristics of the channel layer from being damaged, thereby maintaining good electrical properties and improving display quality.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific embodiments are described in detail as follows in conjunction with the accompanying drawings:

Description of drawings

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention;

2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, and FIG. 2B is a top view of the thin film transistor substrate shown in FIG. 2A;

3A-8B are a manufacturing embodiment of the thin film transistor substrate in FIG. 2A, wherein the accompanying drawing marked as A is a cross-sectional view, and the accompanying drawing marked as B is a top view;

FIG. 9A is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention, and FIG. 9B is a top view of the thin film transistor substrate shown in FIG. 9A .

Symbol Description

1: display device

2: Display panel

10, 11: Thin film transistor substrate

20: Display Media

30: facing substrate

40: Backlight module

50: Control circuit

100: Substrate

110: First source/drain

120: Second source/drain

121: opening

130: pixel electrode layer

140: first insulating layer

150: second electrode layer

160: second insulating layer

161: first through hole

162: Second through hole

170: Channel layer

180: protective layer

Detailed ways

Please refer to FIG. 1 , which illustrates a display device according to an embodiment of the present invention. The display device 1 can be a common flat panel display, and is composed of a display panel 2 and a control circuit 50. The control circuit 50 is coupled to the display panel 2 for transmitting display signals and adjusting current output. There are many types of display panels 1 , which can be classified into self-illuminating type (such as OLED) or backlighting type (such as LCD) according to whether an external light source is required for imaging. When the backlight display panel 1 is selected, the display device 1 may include a backlight module 40 for providing the required light source.

The display panel 2 is the main component of the display device 1 and includes a TFT substrate 10 , a display medium 20 and an opposite substrate 30 . The TFT substrate 20 is coupled to the control circuit 50 to adjust each pixel according to the received display signal. The display medium 20 varies depending on the type of display panel. For example, when the display panel 2 is an LCD panel, the display medium is a liquid crystal layer; when the display panel 2 is an OLED panel, the display medium is an organic light emitting layer. The opposite substrate 30 can be a general transparent substrate or a color filter substrate (color filter), which is opposite to the TFT substrate 10 and sandwiches the display medium 20 therebetween. In one embodiment, when the opposite substrate 30 is a transparent substrate, a color filter can be formed on the TFT substrate 10, or the display medium 20 can have a color display function.

2A shows a cross-sectional view of a TFT substrate according to an embodiment, and FIG. 2B shows a top view of the TFT substrate in FIG. 2A , wherein FIG. 2A is a cross-section of the TFT substrate 10 in FIG. 2B at the dotted line A-A'. To make the drawing clearer, some elements are omitted in the top view of FIG. 2B . The thin film transistor substrate 10 includes a substrate 100, a first electrode layer (a first source/drain 110 and a second source/drain 120), a pixel electrode layer 130, a first insulating layer 140, a gate layer 150, a second insulating layer 160 , a channel layer 170 and a protective layer 180 .

A manufacturing embodiment of the thin film transistor substrate in FIG. 2A is described below with reference to FIGS. 3A to 8B , wherein the figure marked A is a cross-sectional view, and the figure marked B is a top view.

Referring to FIG. 3A and FIG. 3B , a substrate 100 (ignored in FIG. 3B ) is provided, and a patterned first electrode layer is formed on the substrate 100 . Note that the cross-section in FIG. 3A is cut along the L-shaped dashed line A-A' in FIG. 3B , not a straight line. The first electrode layer at least includes a first source/drain 110 and a second source/drain 120, the two are separated from each other, where the first source/drain 110 surrounds a C-shaped notch, and the second source/drain 120 The drain 120 is disposed in the notch, that is, the first source/drain 110 bypasses the second source/drain 120 . The first source/drain 110 can be used as a data line later. The material of the first electrode layer may include Al, Al—Nd, MoW, Cu, Cr, Au, Mo, MoAlMo, but is not limited thereto, and materials generally used for electrodes of semiconductor devices can be used.

Next, as shown in FIGS. 4A and 4B , the pixel electrode layer 130 is formed. The pixel electrode layer 130 is connected to the second source/drain 120 of the first electrode layer. In addition, an opening 121 is defined through the pixel electrode layer 130 to expose the source electrode 120 . The pixel electrode layer is a transparent electrode, and the material may include ITO, IZO or ZnO, but is not limited thereto.

Next, as shown in FIG. 5A and FIG. 5B, a first insulating layer 140 (ignored in FIG. 5B ) is deposited to cover the TFT substrate (covering the substrate 110, the first source/drain 110, the second source/drain 120 and the pixel electrode layer 130), and then form the second electrode layer 150. The second electrode layer 150 can be a gate line disposed on the first insulating layer and between the first source/drain 110 and the second source/drain 120 ( FIG. 5A ). The extension direction of the second electrode layer 150 is perpendicular to the extension direction of the first source/drain 110 (FIG. 5B), and the part of the second electrode layer 150 across the first source/drain 110 and the second source/drain 120 can be used as a thin film transistor element. grid used. That is to say, the second electrode layer 150 in FIG. 5A is used as a gate, together with the first source/drain 110 and the second source/drain 120 to form a thin film transistor device. The TFT element is located at the intersection of the first source/drain (data line) 110 and the second electrode layer 150 (gate line), as shown by the dotted box T in FIG. 5B . Therefore, the TFT substrate of this embodiment does not need to plan additional space for arranging the TFT elements, which can increase the aperture ratio of the combined display panel. The material of the first insulating layer 140 can be _SiNx , _SiOxNX , _AlOx or _SiOx ; The material of the second electrode layer 150 can be with the first electrode layer (the first source/ _drain 110, the second source/drain The electrode 120) is the same, including Al, Al-Nd, MoW, Cu, Cr, Au, Mo, MoAlMo, and may also be different from the first electrode layer, and the present invention is not limited to its material.

Then, as shown in FIG. 6A and FIG. 6B, a second insulating layer 160 (ignored in FIG. 6B ) is formed to cover the thin film transistor substrate (covering the passive layer 140 and the second electrode layer 150), and the second insulating layer 160 is mainly used as a gate. The purpose of the dielectric layer (gate insulator, GI) is to insulate the gate line (second electrode layer 150 ) from other structures. A photoresist (not shown) is used as a mask to define a first through hole 161 and a second through hole 162 , both of which penetrate the first insulating layer 140 and the second insulating layer 160 . The first through hole 161 exposes the second source/drain 120 , and the second through hole 162 exposes the first source/drain 110 . It is particularly noted that the diameter of the first through hole 161 is smaller than the opening 121 penetrating the pixel electrode layer 130 in FIG. electrode layer 130 . The material of the second insulating layer 160 may be SiN _x , SiO _{x NX} , AlO _x , SiO _x or TiO _x , but is not limited thereto.

Next, as shown in FIGS. 7A and 7B , a channel layer 170 is formed. The channel layer 170 is located on the second insulating layer 160, or located on the thin film transistor element composed of the first source/drain 110, the second source/drain 120 and part of the second electrode layer 150 (as a gate). . The channel layer 170 is filled into the first through hole 161 and the second through hole 162 to be electrically connected to the second source/drain 120 and the first source/drain 110 respectively, but the channel layer 170 is connected to the pixel electrode layer 130 and as The second electrode layer 150 of the gate is electrically insulated. As shown in FIG. 7B , the extending direction of the channel layer 170 is perpendicular to the extending direction of the second electrode layer 150 (gate line), and parallel to the extending direction of the first source/drain 110 (data line). The channel layer 170 is located at the intersection of the data line 110 and the gate line 150 . By designing the channel layer 170 to be perpendicular to the second electrode layer 150 (gate line), the channel layer of this embodiment only needs to be aligned with the source and drain, and does not need to be aligned with the gate, which can reduce the alignment. steps, reducing the precision required for the fabrication process. The material of the channel layer is, for example, an oxide semiconductor material, such as a-IGZO or a-IZO.

Finally, as shown in FIG. 8A and FIG. 8B , a protective layer 180 (overcoating layer, omitted in FIG. 8B ) is formed on the channel layer 170 , that is, the thin film transistor substrate 10 is completed. The thickness of the protective layer 180 can be adjusted according to the requirements of the manufacturing process, and polishing such as chemical mechanical polishing (CMP) can also be performed to make the surface smooth, as shown in FIG. 2A . The manufacturing steps of the protective layer 180 are simple, for example, it only needs to pre-bake and hot-bake the organic material, the pre-bake temperature is between 70-80°C, and the hot-bake temperature About 100°C. Compared with chemical vapor deposition CVD or plasma manufacturing process whose operating temperature is higher than 300° C., the formation of the protection layer 180 not only does not damage the electrical properties of the channel layer 170 , but also prevents the channel layer 170 from being exposed.

9A and 9B illustrate a cross-sectional view and a top view of a thin film transistor substrate according to another embodiment of the present invention. The thin film transistor substrate 11 is similar to the thin film transistor substrate 10 described in FIG. 2A and FIG. 2B , the difference lies in the position of the pixel electrode layer 130 , and the rest of the structure will not be repeated.

In FIG. 9A, the pixel electrode layer 130 is formed before the first electrode layer (the first source/drain 110 and the second source/drain 120), is located between the second source/drain 120 and the substrate 100, and is connected with The second source/drain 120 is electrically connected. Since the pixel electrode layer 130 is located under the second source/drain electrode 120, there is no need to design a through hole (for example, the opening 121 in Figure 4A and Figure 4B) on the pixel electrode layer 130, nor does it need The step generally aligns the opening 121 with the first through hole 161 . In this way, the alignment accuracy required by the manufacturing process can be further reduced, the cost can be reduced and the yield rate can be improved.

In the display panel and display device of the above embodiments, the channel layer of the thin film transistor substrate is designed on the top of the structure, and is further isolated by a protective layer, which can prevent the element characteristics of the channel layer from being damaged and maintain good electrical properties. In addition, compared with the existing architectures such as channel layer etched BCE and channel protection CHP in which the channel layer and the gate line are designed to be parallel, in the embodiment, the channel layer and the gate line are designed to be perpendicular to each other, which can reduce the cost required for the manufacturing process. Alignment accuracy, reduce cost and increase yield. What's more, the thin film transistor element of the embodiment is arranged at the intersection of the data line and the gate line of the thin film transistor substrate, which does not require extra space for arrangement, and can increase the overall aperture ratio of the display panel.

In summary, although the present invention has been disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Those skilled in the art to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. a display floater, comprising:

Thin film transistor base plate, comprising:

Substrate;

First electrode layer, is positioned on this substrate;

Pixel electrode layer, is positioned on this substrate;

First insulating barrier, covers this first electrode layer and this pixel electrode;

The second electrode lay, is positioned on this first insulating barrier;

Second insulating barrier, covers this second electrode lay, has the first through hole and the second through hole, and wherein this first through hole and this second through hole run through this first insulating barrier and this second insulating barrier, to expose this first electrode layer;

Channel layer, is positioned on this second insulating barrier, and inserts this first through hole and this second through hole, to be electrically connected with this first electrode layer; And

Protective layer, covers this channel layer;

Subtend substrate, is arranged relative to this thin film transistor base plate; And

Display medium, between this thin film transistor base plate and this subtend substrate.

2. display floater as claimed in claim 1, wherein this first electrode layer comprises the first source/drain and the second source/drain, and this first source/drain is a part for a data wire, and this second electrode lay is a gate line.

3. display floater as claimed in claim 2, wherein this pixel electrode layer is electrically connected with this second source/drain, and between this second source/drain and this first insulating barrier.

4. display floater as claimed in claim 3, wherein this pixel electrode layer has opening, exposes this second source/drain.

5. display floater as claimed in claim 4, wherein this first through hole is positioned within this opening.

6. display floater as claimed in claim 2, wherein this pixel electrode layer is electrically connected with this second source/drain, and between this substrate and this second source/drain.

7. display floater as claimed in claim 2, wherein this channel layer is positioned at this data wire and this gate line infall.

8. display floater as claimed in claim 1, wherein the material of this channel layer is indium oxide gallium zinc (Indium gallium zinc oxide, IGZO) or indium-zinc oxide (indium zinc oxide, IZO).

9. display floater as claimed in claim 1, wherein this display medium is liquid crystal layer or organic luminous layer.

10. a display unit, comprising:

Display floater, comprising:

Thin film transistor base plate, comprising:

Substrate;

First electrode layer, is positioned on this substrate;

Pixel electrode layer, is positioned on this substrate;

First insulating barrier, covers this first electrode layer and this pixel electrode layer;

The second electrode lay, is positioned on this first insulating barrier;

Second insulating barrier, covers this second electrode lay, has the first through hole and the second through hole, and wherein this first through hole and this second through hole run through this first insulating barrier and this second insulating barrier, to expose this first electrode layer;

Channel layer, is positioned on this second insulating barrier, and inserts this first through hole and this second through hole, to be electrically connected with this first electrode layer; And

Protective layer, covers this channel layer;

Subtend substrate, is arranged relative to this thin film transistor base plate; And

Display medium, between this thin film transistor base plate and this subtend substrate; And

Control circuit, is coupled to this display floater.