CN104681542A - Semiconductor electrostatic discharge protection device - Google Patents

Abstract

The invention discloses a semiconductor electrostatic discharge protection device, comprising: the semiconductor device comprises a first electric transistor, a second electric well region, a second electric protection ring and a semiconductor spacer region. The first electric transistor is formed in the second electric well region. The second electrical protection ring surrounds the first electrical transistor. And the semiconductor spacer region is positioned between the first electric transistor and the second electric protection ring and surrounds the first electric transistor, and the semiconductor spacer region is an undoped region, a first electric doped region or a second electric doped region with doping concentration smaller than that of the second electric well region.

Description

Semiconductor electrostatic discharge protection device

technical field

The invention relates to a semiconductor integrated circuit element, and in particular to a semiconductor electrostatic discharge protection device.

Background technique

Electrostatic discharge is the migration of electrostatic charges on non-conductive surfaces through conductive materials. Since electrostatic voltage is usually quite high, electrostatic discharge can easily damage the substrate and other components of an integrated circuit. In order to protect the integrated circuit from being damaged by ESD, a device with the function of conducting the ESD current to the ground is integrated into the integrated circuit.

Take the grounded gate n-type metal-oxide-semiconductor conductor Gate Grounded n-typeMetal-Oxide-Semiconductor (GGNMOS) transistor unit as an example, its gate, source and element substrate are grounded, when electrostatic discharge occurs (ESD zapping), The snapback causes the ground gate n-type metal-oxide-semiconductor transistor unit to be turned on, so as to conduct a large electrostatic discharge current (ESD current) between its drain structure and source structure, and then discharge the static electricity The discharge current is conducted to the ground to achieve the protection function of electrostatic discharge.

However, the traditional grounded gate n-type metal-oxide-semiconductor transistor unit is prone to secondary snapback collapse due to the base push-out effect of the parasitic NPN bicarrier junction transistor. To make the excessive leakage current pass through the emitter and ground base of the parasitic double carrier junction transistor, and then conduct to the ground from the element substrate (parasitic base) of the parasitic double carrier junction transistor, resulting in a ground gate n-type metal-oxide-semiconductor Conductor transistor unit permanently fails.

Therefore, how to prevent the leakage of the parasitic bicarrier junction transistor of the semiconductor ESD protection device has become a major challenge in the ESD protection design.

Contents of the invention

In order to solve the above problems, one aspect of the present invention is to provide a semiconductor electrostatic discharge protection device, comprising: a first transistor with a first electrical property, a second electrical property well region, a second electrical property guard ring, and a semiconductor spacer. The first transistor is formed in the second electrical well region. The second electrical protection ring surrounds the first transistor. The semiconductor spacer is located between the first transistor and the second electrical protection ring and surrounds the first transistor. Wherein, the semiconductor spacer region is an undoped region, a doped region of the first electrical type or a doped region of the second electrical type whose doping concentration is lower than that of the well area of the second electrical type.

In an embodiment of the present invention, the semiconductor electrostatic discharge protection device further includes a shallow trench isolation structure located between the first transistor and the second electrical protection ring. Wherein, the semiconductor spacer is located under the shallow trench isolation structure.

In an embodiment of the present invention, the semiconductor electrostatic discharge protection device further includes a shallow trench isolation structure located between the first transistor and the second electrical protection ring. Wherein, the semiconductor spacer is located between the shallow trench isolation structure and the second electrical protection ring.

In an embodiment of the present invention, the first electrical property is N-type electrical property, and the second electrical property is P-type electrical property. In an embodiment of the present invention, the first electrical property is a P-type electrical property, and the second electrical property is an N-type electrical property.

In an embodiment of the present invention, the first transistor includes a gate structure, a source, a drain, and a second electrical high-concentration doped region. The gate structure is formed on the second electrical well region. The source is formed in the second electrical well region and adjacent to the gate structure. The drain is formed in the second electrical well region and adjacent to the gate structure. The second electrical high-concentration doped region is located in the second electrical well region under the drain, and has a higher doping concentration than the second electrical well region.

In an embodiment of the present invention, the semiconductor electrostatic discharge protection device further includes a base contact region adjacent to the second electrical well region and the second electrical protection ring. Wherein, the base contact area and the source are commonly grounded, and the drain is electrically connected to an I/O pad.

In an embodiment of the present invention, the semiconductor electrostatic discharge protection device further includes a second transistor and a third transistor having a first electrical property. Wherein the first transistor, the second transistor and the third transistor have a common drain.

In an embodiment of the present invention, the semiconductor electrostatic discharge protection device further includes a well contact region (Well Pick-Up) and a second transistor and a third transistor having a first electrical property. Wherein, the first transistor, the second transistor and the third transistor have a common source and surround the well contact region.

Another aspect of the present invention is to provide a semiconductor electrostatic discharge protection device, including: a plurality of first electrical transistors, a second electrical protection ring, and a well contact area. Wherein, the second electrical protection ring surrounds the transistors of the first electrical type; and the transistors of the first electrical type surround the well contact region.

In an embodiment of the present invention, the semiconductor electrostatic discharge protection device further includes a first electrical protection ring, located between the first electrical transistors and the second electrical protection ring, and surrounding the first electrical protection rings. An electrical transistor.

In an embodiment of the present invention, each first transistor includes a gate structure, a source and a drain. The gate structure is formed on a second electrical well region. The drain is formed in the second electrical well region and adjoins the side of the gate structure away from the well contact region. The source is formed in the second electrical well region and adjoins the side of the gate structure close to the well contact region.

In one embodiment of the present invention, the well contact region and the source are commonly grounded, and the drain is electrically connected to an I/O pad.

In an embodiment of the present invention, each of the first transistors further includes a second electrical high-concentration doped region, located in the second electrical well region below the drain, and having a higher density than the second electrical The doping concentration of the well region.

According to the above-mentioned embodiments, the present invention provides a semiconductor electrostatic discharge protection device. In one embodiment of the present invention, the semiconductor electrostatic discharge protection device at least includes: a first electrical transistor formed in the element substrate, A second electrical guard ring surrounding the first electrical transistor and a semiconductor spacer between the first electrical transistor and the second electrical guard ring. Wherein, the semiconductor spacer region is an undoped region, a doped region of the first electrical type or a doped region of the second electrical type whose doping concentration is lower than that of the well area of the second electrical type. By setting a semiconductor spacer between the first electrical transistor and the second electrical guard ring, the distance between the drain of the first electrical transistor and the second electrical guard ring is increased, thereby increasing the semiconductor The resistance between the parasitic bicarrier junction transistor emitter and the ground base in the electrostatic discharge protection device reduces the leakage current from the drain to the ground through the element substrate, thereby improving the electrostatic discharge protection of the semiconductor electrostatic discharge protection device ability.

In another embodiment of the present invention, the semiconductor electrostatic discharge protection device at least includes: a plurality of first electrical transistors formed in the element substrate, a second electrical protection ring surrounding the first electrical transistors, and a second electrical protection ring surrounded by the first electrical transistors. A well contact region surrounded by transistors of the first electrical type. Through a specific wiring method, the distance between the drain and the well contact region of the first electrical transistor is increased, thereby increasing the parasitic bi-carrier junction transistor emitter and the ground base in the semiconductor electrostatic discharge protection device The resistance value can reduce the leakage current from the drain to the ground through the well contact area, thereby improving the electrostatic discharge protection capability of the semiconductor electrostatic discharge protection device.

Description of drawings

In order to make the above-mentioned and other objects, features and advantages of the present invention more comprehensible, several preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

FIG. 1A is a schematic top view of a semiconductor electrostatic discharge protection device according to an embodiment of the present invention;

1B is a schematic cross-sectional view of a partial structure of the semiconductor electrostatic discharge protection device shown along the tangent line S1 of FIG. 1A;

2A is a schematic top view of a semiconductor electrostatic discharge protection device according to another embodiment of the present invention;

2B is a schematic cross-sectional view of a partial structure of the semiconductor electrostatic discharge protection device shown along the tangent line S2 of FIG. 2A;

3A is a schematic top view of a semiconductor electrostatic discharge protection device according to another embodiment of the present invention;

3B is a schematic cross-sectional view of a partial structure of the semiconductor electrostatic discharge protection device shown along the tangent line S3 of FIG. 3A;

4A is a schematic top view of a semiconductor electrostatic discharge protection device according to yet another embodiment of the present invention;

4B is a schematic cross-sectional view of a partial structure of the semiconductor electrostatic discharge protection device shown along the tangent line S4 of FIG. 4A;

5A is a schematic top view of a semiconductor electrostatic discharge protection device according to yet another embodiment of the present invention;

FIG. 5B is a schematic cross-sectional view of a partial structure of the semiconductor ESD protection device along the tangent line S5 in FIG. 5A .

Explanation of main device symbols

100: Semiconductor electrostatic discharge protection device

101: Substrate 101a: Substrate Surface

102: Protection ring

103: Metal-Oxide-Semiconductor Transistors

103a: Gate structure 103b: Drain

103c: source 104: P-type well region

105: Shallow trench isolation structure 106: Semiconductor spacer

107: Substrate contact area 108a: Conductive contact

108b: Conductive contact 109: Conductive contact

110: Input/output pad 111: P-type high-concentration doped region

200: Semiconductor electrostatic discharge protection device

206: Semiconductor spacer region 207: Substrate contact region

300: Semiconductor electrostatic discharge protection device

306: Semiconductor spacer 307: Substrate contact area

400: Semiconductor electrostatic discharge protection device

403: Metal-Oxide-Semiconductor Transistors

403a: gate 403b: common drain

403c: Source 407: Substrate contact area

500: Semiconductor electrostatic discharge protection device

503: Metal-Oxide-Semiconductor Transistors

503a: Gate 503c: Drain

503b: common source 507: substrate contact area

512: N-type protective ring S1: Tangent

S2: Tangent S3: Tangent

S4: Tangent S5: Tangent

Detailed ways

The invention provides a semiconductor electrostatic discharge protection device, which can reduce the leakage current from being conducted to the ground through the element substrate, and improve the electrostatic discharge protection capability of the semiconductor electrostatic discharge protection device. In order to make the above and other objects, features and advantages of the present invention more comprehensible, several preferred embodiments will be described in detail below together with the accompanying drawings.

Please refer to FIGS. 1A and 1B . FIG. 1A is a schematic top view of a semiconductor ESD protection device 100 according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a partial structure of the semiconductor ESD protection device 100 along the tangent line S1 of FIG. 1A . Among them, the semiconductor electrostatic discharge protection device 100 includes at least one first electrical metal-oxide-semiconductor (Metal-Oxide-Semiconductor, MOS) formed in the semiconductor substrate 101 and surrounded by the second electrical protection ring 102 Transistor 103.

In some embodiments of the present invention, in order to withstand a sufficiently high ESD current, the semiconductor ESD protection device 100 generally includes a plurality of metal-oxide-semiconductor transistors 103 units. In order to save the occupied layout area, in the integrated circuit layout, the semiconductor ESD protection device 100 is generally designed as a multi-finger (multi-finger) composed of a plurality of finger-shaped metal-oxide-semiconductor transistors 103. ) structure (as shown in Figure 1A).

In some embodiments of the present invention, the first electrical property may be an N-type electrical property, and the second electrical property may be a P-type electrical property. For example, in this embodiment, each metal-oxide-semiconductor transistor 103 has a gate structure 103a, a drain 103b, and a source 103c. Wherein, the gate structure 103 a includes a gate dielectric layer 103 a 1 and a gate electrode 103 a 2 located on the P-type well region 104 . The drain 103b is a highly doped N-type doped region (indicated by N+), extending from the surface 101a of the substrate 101 into the P-type well region 104 and adjoining one side of the gate structure 103a. The source 103c is also a highly doped N-type doped region, extending from the surface 101a of the substrate 101 into the P-type well region 104, and adjacent to the other side of the gate structure 103a. The guard ring 102 is a highly doped P-type doped region (indicated by P+) extending from the surface 101 a of the substrate 101 into the P-type well region 104 , and is used to surround the N-type metal-oxide-semiconductor transistors 103 .

However, it should be noted that, in other embodiments of the present invention, the first electrical property is a P-type electrical property, and the second electrical property is an N-type electrical property. That is to say, in the following embodiments, the electrical properties of each region of the semiconductor ESD protection device 100 are not specified. It varies relatively with the actual electrical properties selected for the metal-oxide-semiconductor transistor 103 and the guard ring 102 .

In addition, between the metal-oxide-semiconductor transistor 103 and the second electrical protection ring 102 , there is also a shallow trench isolation structure 105 and a semiconductor spacer 106 surrounding the metal-oxide-semiconductor transistor 103 . In some embodiments of the present invention, the shallow trench isolation structure 105 is a dielectric material structure extending from the surface 101 a of the substrate 101 into the substrate 101 . The semiconductor spacer 106 is located under the shallow trench isolation structure 105 . In some embodiments of the present invention, the semiconductor spacer region 106 may be located between the shallow trench isolation structure 105 and the guard ring 102 . In this embodiment, the semiconductor spacer region 106 is an N-type doped region extending downwardly from the lower edge of the shallow trench isolation structure 105 into the substrate 101 and surrounding the metal-oxide-semiconductor transistor 103 .

In some embodiments of the present invention, the source 103c and the guard ring 102 are commonly grounded through the conductive contacts 108a and 109, respectively, and the drain 103b is electrically connected to an input/output pad 110 through the conductive contact 108b to provide input/output Pad 110 for electrostatic discharge protection. Because each metal-oxide-semiconductor transistor 103 is electrically connected to the guard ring 102 through the substrate contact region 107 including a part of the substrate 101 adjacent to the P-type well region 104 and the second electrical guard ring 102 . Therefore, a parasitic double-carrier junction (NPN junction) transistor is formed between the source 103 c , the drain 103 b , and the second electrical guard ring 102 .

The arrangement of the shallow trench isolation structure 105 and the semiconductor spacer region 106 can just increase the distance between the drain electrode 103b and the guard ring 102 (that is, the length of the substrate contact region 107), thereby increasing the emitter of the parasitic bicarrier junction transistor. The resistance between the electrode and the grounded base reduces the conduction of leakage current from the drain 103 b to the ground through the base contact region 107 , so as to improve the ESD protection degree of the semiconductor ESD protection device 100 .

In addition, in order to increase the resistance between the emitter and the grounded base of the parasitic bicarrier junction transistor, in some embodiments of the present invention, the P-type well region 104 below the drain 103b can also be selectively Among them, a P-type high-concentration doped region 111 is provided to have a higher doping concentration than the P-type well region 104 .

It should be noted that the electrical property of the semiconductor spacer region 106 is not limited to an N-type doped region. For example, please refer to FIGS. 2A and 2B . FIG. 2A is a schematic top view of a semiconductor ESD protection device 200 according to another embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of a partial structure of the semiconductor ESD protection device 200 along the tangent line S2 of FIG. 2A . Wherein, the structure of the semiconductor ESD protection device 200 is substantially the same as that of the semiconductor ESD protection device 100 shown in FIGS. 1A and 1B . lightly doped region.

In addition, please refer to FIGS. 3A and 3B again. FIG. 3A is a schematic top view of a semiconductor ESD protection device 300 according to another embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of a partial structure of the semiconductor ESD protection device 300 along the tangent line S3 in FIG. 3A . The structure of the semiconductor ESD protection device 300 is substantially the same as that of the semiconductor ESD protection device 100 shown in FIGS. 1A and 1B , the only difference being that the semiconductor spacer region 306 is an undoped region.

Regardless of whether the P-type lightly doped semiconductor spacer 306 or the non-doped semiconductor spacer 206 is used, the distance between the drain 103b and the guard ring 102 (that is, the length of the base contact region 207 or 307 can be increased) ), and then increase the resistance between the emitter and the grounded base of the parasitic bicarrier junction transistor, reduce the leakage current from the drain 103b through the substrate contact region 207 or 307 and conduct to the ground, so as to improve the semiconductor electrostatic discharge protection The degree of electrostatic discharge protection of the device 200 or 300 .

In addition, the effect of increasing the resistance between the emitter and the grounded base of the parasitic double-carrier junction transistor can also be achieved by changing the wiring method of the semiconductor electrostatic discharge protection device. Please refer to FIGS. 4A and 4B . FIG. 4A is a schematic top view of a semiconductor ESD protection device 300 according to another embodiment of the present invention. FIG. 4B is a schematic cross-sectional view of a partial structure of the semiconductor ESD protection device 400 along the tangent line S4 of FIG. 4A . Wherein, the structure of the semiconductor ESD protection device 400 is substantially the same as that of the semiconductor ESD protection device 300 shown in FIGS. 3A and 3B . The only difference lies in the layout of the metal-oxide-semiconductor transistor 403 of the semiconductor ESD protection device 400 .

In some embodiments of the present invention, the semiconductor electrostatic discharge protection device 400 includes at least a plurality of N-type metal-oxide-semiconductor transistors 403 with a common drain 403b, and these metal-oxide-semiconductor transistors of the first electrical type The gate 403a and the source 403 of the transistor 403 form a ring structure surrounding the common drain 403b. In this embodiment, the gates 403 a and sources 403 of the four first electrical type metal-oxide-semiconductor transistors 403 form a ring structure, surrounding the common drain 403 b (see FIG. 4A ). Thus, the common drain 403b can be located on the side of the first electrical type metal-oxide-semiconductor transistor 403 away from the guard ring 102, so as to increase the distance between the drain 403b and the guard ring 102 (that is, the distance between the base contact region 407 length), increasing the resistance of the parasitic bicarrier junction transistor emitter and grounded base. Furthermore, the leakage current is reduced from the drain 103b through the substrate contact region 407 and then conducted to the ground, so as to improve the ESD protection degree of the semiconductor ESD protection device 400 .

Please refer to FIGS. 5A and 5B again. FIG. 5A is a schematic top view of a semiconductor ESD protection device 500 according to yet another embodiment of the present invention. FIG. 5B is a schematic cross-sectional view of a partial structure of the semiconductor ESD protection device 500 along the tangent line S5 in FIG. 5A . Wherein, the semiconductor ESD protection device 500 is similar to the semiconductor ESD protection device 400 shown in FIGS. 4A and 4B , the only difference lies in the layout of the metal-oxide-semiconductor transistor 503 .

In some embodiments of the present invention, the semiconductor ESD protection device 500 includes at least a well contact region 507 and a plurality of N-type metal-oxide-semiconductor transistors 503 . Wherein, the well contact region 507 is located in the well contact region 507 in the P-type well region 104 , and one end thereof is grounded. The plurality of NMOS transistors 503 have a ring-shaped common source 503c. In detail, in this embodiment, four metal-oxide-semiconductor transistors 503 of the first electrical type, the gate 503a and the drain 503c of these metal-oxide-semiconductor transistors 503 can form a ring structure, used to surround the ring-shaped common source 503b. And this annular common source 503b surrounds the grounded well contact region 507 (see FIG. 4A ). Thus, the drain 503c of each metal-oxide-semiconductor transistor 503 can be kept away from the well contact region 507, so as to increase the distance between the drain 503c and the well contact region 507, and increase the parasitic double-carrier junction transistor The effect of the resistance of the emitter and the ground base. Furthermore, the leakage current is reduced from the drain 503 c to the ground through the well contact region 507 , so as to improve the ESD protection degree of the semiconductor ESD protection device 500 .

In addition, in order to avoid the element latch-up effect, in this embodiment, it is preferable to set an N-type guard ring 512 between the guard ring 502 and the metal-oxide-semiconductor transistor 503, and surround the first An electrical metal-oxide-semiconductor transistor 503 . In addition, the N-type guard ring 512 can also be used as a semiconductor spacer to increase the distance between the drain 503c and the grounded guard ring 102, and increase the distance between the emitter and the ground base of the parasitic bicarrier junction transistor. The resistance value between the poles is used to improve the ESD protection degree of the semiconductor ESD protection device 500 .

According to the above-mentioned embodiments, the present invention provides a semiconductor electrostatic discharge protection device. In one embodiment of the present invention, the semiconductor electrostatic discharge protection device at least includes: a first electrical transistor formed in the element substrate, A second electrical guard ring surrounding the first electrical transistor and a semiconductor spacer between the first electrical transistor and the second electrical guard ring. Wherein, the semiconductor spacer region is an undoped region, a doped region of the first electrical type or a doped region of the second electrical type whose doping concentration is lower than that of the well area of the second electrical type. By setting a semiconductor spacer between the first electrical transistor and the second electrical guard ring, the distance between the drain of the first electrical transistor and the second electrical guard ring is increased, thereby increasing the semiconductor The resistance between the parasitic bicarrier junction transistor emitter and the ground base in the electrostatic discharge protection device reduces the leakage current from the drain to the ground through the element substrate, thereby improving the electrostatic discharge protection of the semiconductor electrostatic discharge protection device ability.

In another embodiment of the present invention, the semiconductor electrostatic discharge protection device at least includes: a plurality of first electrical transistors formed in the element substrate, a second electrical protection ring surrounding the first electrical transistors, and a second electrical protection ring surrounded by the first electrical transistors. A well contact region surrounded by transistors of the first electrical type. Through a specific wiring method, the distance between the drain and the well contact region of the first electrical transistor is increased, thereby increasing the parasitic bi-carrier junction transistor emitter and the ground base in the semiconductor electrostatic discharge protection device The resistance value can reduce the leakage current from the drain to the ground through the well contact area, thereby improving the electrostatic discharge protection capability of the semiconductor electrostatic discharge protection device.

Although the present invention has been disclosed in conjunction with the above preferred embodiments, they are not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (14)

1. a semiconductor electrostatic discharge protector, comprising:

The first transistor has first electrically, is formed among one second electrical well region;

Second electrical guard ring, around this first transistor; And

Semiconductor spacer region, between this first transistor and this second electrical guard ring, and around this first transistor, and this semiconductor spacer region be undoped region, the first electrical doped region or doping content be less than the second electrical doped region of this second electrical well region.

2. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises shallow trench isolation structure, between this first transistor and this second electrical guard ring; Wherein this semiconductor spacer region is positioned at below this shallow trench isolation structure.

3. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises shallow trench isolation structure, between this first transistor and this second electrical guard ring; Wherein this semiconductor spacer region is between this shallow trench isolation structure and this second electrical guard ring.

4. semiconductor electrostatic discharge protector as claimed in claim 1, wherein this first be electrically that N-type is electrical, and this second electrical be that P type is electrical.

5. semiconductor electrostatic discharge protector as claimed in claim 1, wherein this first be electrically that P type is electrical, and this second electrical be that N-type is electrical.

6. semiconductor electrostatic discharge protector as claimed in claim 1, wherein this first transistor comprises:

Grid structure, is formed on this second electrical well region;

Source electrode, is formed among this second electrical well region, and this grid structure adjacent;

Drain electrode, is formed among this second electrical well region, and this grid structure adjacent; And

Second electrical high-concentration dopant district, is positioned among this second electrical well region below this drain electrode, and has the doping content higher than this second electrical well region.

7. semiconductor electrostatic discharge protector as claimed in claim 6, also comprises substrate contact district (body contact), is adjacent to this second electrical well region and this second electrical guard ring, and with this source electrode common ground; And this drain electrode is electrically connected with an I/o pad (I/O pad).

8. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises:

Transistor seconds, has that this is first electrical; And

Third transistor, has that this is first electrical;

Wherein, this first transistor, this transistor seconds and this third transistor have a common drain.

9. semiconductor electrostatic discharge protector as claimed in claim 1, also comprises:

Trap contact zone (well pick-up region), is formed among this second electrical well region

Transistor seconds, has that this is first electrical; And

Third transistor, has that this is first electrical;

Wherein, this first transistor, this transistor seconds and this third transistor have a ring-type common source, around this trap contact zone.

10. a semiconductor electrostatic discharge protector, comprising:

Multiple first conductive crystal pipe;

Second electrical guard ring, around those the first conductive crystal pipes; And

Trap contact zone, wherein those the first conductive crystal pipes, around this trap contact zone.

11. semiconductor electrostatic discharge protectors as claimed in claim 10, also comprise one first electrical guard ring, between those the first conductive crystal pipes and this second electrical guard ring, and around those the first conductive crystal pipes.

12. semiconductor electrostatic discharge protectors as claimed in claim 10, wherein each those the first conductive crystal pipe comprises:

Grid structure, is formed on one second electrical well region;

Drain electrode, is formed among this second electrical well region, and this grid structure adjacent is away from the side of this trap contact zone; And

Source electrode, is formed among this second electrical well region, and this grid structure adjacent is near the side of this trap contact zone.

13. semiconductor electrostatic discharge protectors as claimed in claim 12, wherein this trap contact zone and this source electrode common ground, and this drain electrode is electrically connected with an I/o pad.

14. semiconductor electrostatic discharge protectors as claimed in claim 12; wherein each those the first conductive crystal pipe also comprises one second electrical high-concentration dopant district; be positioned among this second electrical well region below this drain electrode, and there is the doping content higher than this second electrical well region.