CN104681422B - The forming method of semiconductor devices - Google Patents

Abstract

A method for forming a semiconductor device, comprising: providing a substrate, the substrate includes a first region and a second region, the surface of the first region has a first dummy gate structure, and the first dummy gate structure includes The first dummy gate layer located on the surface of the substrate, the substrate surface has a dielectric layer, the surface of the dielectric layer is flush with the surface of the first dummy gate structure; formed in the dielectric layer of the second region first opening; after forming the first opening, removing the first dummy gate layer, forming a second opening in the dielectric layer; forming a conductive layer in the first opening and the second opening, wherein the first dummy gate layer The conductive layer in one opening forms the device structure, and the conductive layer in the second opening forms the first gate. The method for forming a semiconductor device is simple.

Description

Method of forming semiconductor device

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.

Background technique

With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, has been continuously reduced to meet the miniaturization and development of integrated circuits. Integration requirements. In the process of continuous shrinking of the size of MOS transistor devices, the process of using silicon oxide or silicon oxynitride as the gate dielectric layer in the existing process is challenged. Transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer have some problems, including increased leakage current and diffusion of impurities, which affect the threshold voltage of the transistor and further affect the performance of semiconductor devices.

In order to solve the above problems, a transistor composed of a high-K gate dielectric layer and a metal gate is proposed, that is, a high-K metal gate (HKMG, High K Metal Gate) transistor. The high-K metal gate transistor adopts high-K (dielectric constant) material instead of commonly used silicon oxide or silicon oxynitride gate dielectric material, which can reduce the generation of leakage current and improve the performance of the transistor while reducing the size of the transistor.

In addition, with the development of integrated circuit manufacturing technology, the size of other semiconductor devices in the integrated circuit is continuously reduced, so that semiconductor devices made of polysilicon cannot meet the growing technical requirements. In order to overcome the problems of excessive resistance, large leakage current, or increased overlapping capacitance caused by the reduction in the size of semiconductor devices, semiconductor devices made of metals have also been developed accordingly, and fuse structures and fuses made of metals have been developed accordingly. Resistive devices.

Taking the fuse structure as an example, the fuse is used to connect the redundant circuits in the integrated circuit. When the circuit is found to be defective, these fusible connecting lines can be used to repair or replace the defective circuit; in addition, the fuse can also Provide programming functions, that is, firstly process the circuit, device array and programmed circuit on the chip, then input data from the outside, and complete the circuit design by blowing the fuse through the programmed circuit; for example, in programmable read-only In the memory (Programmable Read Only Memory, PROM), an open circuit is generated by blowing the fuse, that is, the state is "1", and the unbroken fuse remains connected, that is, the state is "0". A common fuse structure includes a cathode and an anode, and a fusing zone located between the cathode and the anode; when the fuse structure needs to be disconnected, a high-voltage pulse is applied to the cathode and the anode to make the inside of the fuse structure High heat is generated, thereby blowing the fuse zone.

However, it is difficult to integrate the process of forming high-k metal gate transistors with the process of forming other semiconductor devices, which makes the process of forming semiconductor devices complicated and increases the production cost.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a semiconductor device, so that the forming process of the high-K metal gate transistor can be integrated with the forming process of the device structure, so as to simplify the process and reduce the production cost.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, the substrate includes a first region and a second region, the surface of the first region has a first dummy gate structure, the The first dummy gate structure includes a first dummy gate layer located on the substrate surface, the substrate surface has a dielectric layer, and the surface of the dielectric layer is flush with the surface of the first dummy gate structure; A first opening is formed in the dielectric layer in the second region; after the first opening is formed, the first dummy gate layer is removed, and a second opening is formed in the dielectric layer; between the first opening and the second opening A conductive layer is formed in the first opening, wherein the conductive layer in the first opening forms the device structure, and the conductive layer in the second opening forms the first gate.

Optionally, the device structure is a fuse structure or a resistance structure, and the material of the conductive layer includes tungsten or aluminum.

Optionally, the forming process of the second opening includes: forming a mask layer on the surface of the dielectric layer and the sidewall and bottom surface of the first opening, the mask layer exposing the surface of the first dummy gate layer ; using the mask layer as a mask, etching and removing the first dummy gate layer to form a second opening in the dielectric layer.

Optionally, the material of the mask layer is one or more combinations of titanium, titanium nitride, tantalum and tantalum nitride.

Optionally, the forming process of the device structure and the first gate includes: forming a conductive layer on the surface of the mask layer, the first opening and the second opening; polishing the conductive layer and the mask layer until exposed A first grid is formed in the second opening until the dielectric layer is exposed, and a device structure is formed in the first opening.

Optionally, the device structure includes a mask layer and a conductive layer.

Optionally, a second isolation structure is provided in the substrate of the second region, and a position of the first opening corresponds to the second isolation structure.

Optionally, the substrate on both sides of the first dummy gate structure has a first source region and a first drain region respectively.

Optionally, the first source region and the first drain region are doped with P-type ions, and the first gate is used to form a PMOS transistor.

Optionally, a stress layer is formed in the substrate on both sides of the first dummy gate structure, the material of the stress layer is silicon germanium, and P-type ions are doped in the stress layer to form a first source region and the first drain region.

Optionally, the first source region and the first drain region are doped with N-type ions, and the first gate is used to form an NMOS transistor.

Optionally, the substrate surface of the first region also has a second dummy gate structure, the second dummy gate structure includes a second dummy gate layer located on the substrate surface, the second dummy gate The substrates on both sides of the structure respectively have a second source region and a second drain region, and the type of the transistor formed by adopting the second dummy gate structure is opposite to that of the transistor formed by adopting the first dummy gate structure.

Optionally, before forming the first opening, the second dummy gate layer is removed, a third opening is formed in the dielectric layer, and a second gate is formed in the third opening.

Optionally, a first isolation structure is provided in the substrate between the adjacent second dummy gate structure and the first dummy gate structure for isolation.

Optionally, when the conductivity type of the second source region and the second drain region is P-type, a stress layer is formed in the substrate on both sides of the second dummy gate structure, and the material of the stress layer is silicon Germanium is doped with P-type ions in the stress layer to form a second source region and a second drain region.

Optionally, the first dummy gate structure further includes a first gate dielectric layer located on the surface of the substrate, the first dummy gate layer is located on the surface of the first gate dielectric layer, and the first gate dielectric layer The material is a high-K material; the second dummy gate structure further includes a second gate dielectric layer located on the surface of the substrate, the second dummy gate layer is located on the surface of the second gate dielectric layer, and the second The material of the gate dielectric layer is a high-K material.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a semiconductor device of the present invention, before removing the first dummy gate layer, a first opening is formed in the dielectric layer in the second region, and the first opening is used to form a device structure. After removing the first dummy gate layer, a second opening can be formed in the dielectric layer, that is, the dielectric layer in the first region has a second opening, and the dielectric layer in the second region has a first opening, The second opening is used to form the first gate of the transistor. Afterwards, a conductive layer can be simultaneously formed in the first opening and the second opening; wherein, the conductive layer located in the first opening serves as the first gate of the transistor, and the conductive layer located in the second opening serves as the device structure, Examples are fuse structures or resistor structures. Therefore, in the process of forming the transistor, the device structure can be formed at the same time, so that the formation process of the semiconductor device can be simplified, the process time can be reduced, and the cost can be saved.

Description of drawings

1 to 7 are schematic cross-sectional structure diagrams of the formation process of the semiconductor device according to the embodiment of the present invention.

Detailed ways

As mentioned in the background art, it is difficult to integrate the process of forming a high-k metal gate transistor with the process of forming other semiconductor devices, which makes the process of forming the semiconductor device complicated and increases the production cost.

After research, it is found that in the formation process of the existing high-K metal gate transistor, the gate-last process (GateLast) is often used. Specifically, the forming process of the high-K metal gate transistor includes: forming a dummy gate structure on the substrate surface, and the dummy gate structure includes: a high-K dielectric layer on the substrate surface, a high-K dielectric layer on the surface A polysilicon dummy gate, the surface of the substrate has a dielectric layer flush with the surface of the dummy gate structure; after a source region and a drain region are formed in the substrate on both sides of the dummy gate structure, the metal gate is used to replace the Polysilicon dummy gates to form high-K metal gate structures.

If a metal fuse structure needs to be formed in an integrated circuit, it is necessary to form an additional metal layer on the surface of the dielectric layer after forming the metal gate, and form a patterned photoresist layer on the surface of the metal layer, The photoresist layer defines the pattern of the fuse structure, and then the metal layer is etched using the photoresist layer as a mask to form a metal fuse structure. Correspondingly, other metal-based devices also need to form an additional metal layer after forming a metal gate, and then use photolithography and etching processes to form a device structure, such as forming a metal resistor.

After further research, the present invention proposes a method for forming a semiconductor device. Wherein, before removing the first dummy gate layer, a first opening is formed in the dielectric layer in the second region, and the first opening is used to form a device structure. After removing the first dummy gate layer, a second opening can be formed in the dielectric layer, that is, the dielectric layer in the first region has a second opening, and the dielectric layer in the second region has a first opening, The second opening is used to form the first gate of the transistor. Afterwards, a conductive layer can be simultaneously formed in the first opening and the second opening; wherein, the conductive layer located in the first opening serves as the first gate of the transistor, and the conductive layer located in the second opening serves as the device structure, Examples are fuse structures or resistor structures. Therefore, in the process of forming the transistor, the device structure can be formed at the same time, so that the formation process of the semiconductor device can be simplified, the process time can be reduced, and the cost can be saved.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 7 are schematic cross-sectional structure diagrams of the formation process of the semiconductor device according to the embodiment of the present invention.

Referring to FIG. 1, a substrate 200 is provided, the substrate 200 includes a first region 210 and a second region 220, the surface of the first region 210 has a first dummy gate structure 201 and a second dummy gate structure 202, The first dummy gate structure 201 includes a first dummy gate layer 201a located on the surface of the substrate 200, the second dummy gate structure 202 includes a second dummy gate layer 202a located on the surface of the substrate 200, the The surface of the substrate 200 has a dielectric layer 203 , and the surface of the dielectric layer 203 is flush with the surfaces of the first dummy gate structure 201 and the second dummy gate structure 202 .

The substrate 200 is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate or a III-V compound substrate ( Such as silicon nitride or gallium arsenide, etc.). The first region 210 is used to form a transistor, and the second region 220 is used to form a device structure. In this embodiment, the device structure is a fuse structure or a resistor structure. It should be noted that the transistors formed in the first region 210 are high-K metal gate transistors, so the process for forming the transistors is a gate-last process.

The first dummy gate structure 201 is used to form a PMOS transistor or an NMOS transistor. The first dummy gate structure 201 includes: a first gate dielectric layer (not marked) located on the surface of the substrate 200, a first dummy gate layer 201a located on the surface of the first gate dielectric layer, and a first dummy gate layer 201a located on the surface of the first gate dielectric layer. and the first sidewall 201b on the surface of the substrate 200 on both sides of the first dummy gate layer 201a; wherein, the material of the first dummy gate layer 201a is polysilicon; the material of the first sidewall 201b is silicon oxide, One or more combinations of silicon nitride and silicon oxynitride; the material of the first gate dielectric layer is a high-K material, and the high-K material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, Zirconia silicon, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide, the high-K material can improve the isolation effect while reducing the thickness of the gate dielectric layer, and is suitable for small size transistor manufacturing. Subsequently, the first dummy gate layer 201a needs to be removed, and a metal gate is formed at the position of the first dummy gate layer 201a.

The substrate 200 on both sides of the first dummy gate structure 201 respectively has a first source region and a first drain region (not marked); when the first dummy gate structure 201 is used to form a PMOS transistor, in Doping P-type ions in the first source region and the first drain region; when the first dummy gate 201 is used to form an NMOS transistor, doping N in the first source region and the first drain region Type ions.

In one embodiment, the first dummy gate structure is used to form a PMOS transistor. Since the carriers in the PMOS transistor are holes, and the mobility of the holes is low, in order to enhance the electromigration efficiency in the PMOS transistor , forming a stress layer in the substrate on both sides of the first dummy gate structure. The stress layer can apply stress to the channel region between the first source region and the first drain region, so as to enhance the mobility of holes. When the material of the substrate is silicon, the material of the stress layer is silicon germanium, and the stress can apply compressive stress to the channel region. The forming process of the stress layer includes: using the first dummy gate structure as a mask to form an opening in the substrate, the sidewall of the opening extends to the bottom of the first dummy gate structure, so that the sidewall of the opening It is in a "Σ" shape relative to the surface of the substrate; a stress layer is formed in the opening by using a selective epitaxial deposition process; and P-type ions are doped in the stress layer to form a first source region and a first drain region.

In addition, the surface of the first region 210 of the substrate 200 also has a second dummy gate structure 202, and the second dummy gate structure 202 includes: a second gate dielectric layer (not marked) on the surface of the substrate 200, The second dummy gate layer 202a located on the surface of the second gate dielectric layer, and the second spacers 202b located on the surface of the substrate 200 on both sides of the second gate dielectric layer and the second dummy gate layer 202a; wherein, the first The material of the dummy gate layer 202a is polysilicon; the material of the second gate dielectric layer is a high-K material; the material of the second spacer 202b is one or more of silicon oxide, silicon nitride, and silicon oxynitride kind of combination. The substrate 200 on both sides of the second dummy gate structure 202 has a second source region and a second drain region respectively, and the ion type doped in the second source region and the second drain region is the same as that of the first source region. region is opposite to the first drain region, the type of transistor formed by using the second dummy gate structure 202 is opposite to that formed by using the first dummy gate structure 201 . Subsequently, the second dummy gate layer 202a needs to be removed, and a metal gate is formed at the position of the second dummy gate layer 202a.

In this embodiment, the surface of the substrate 200 in the first region 210 has a first dummy gate structure 201 and a second dummy gate structure 202; wherein, the first dummy gate structure 201 is used to form an NMOS transistor , the second dummy gate structure 202 is used to form a PMOS transistor, so that a CMOS transistor can be formed in the first region 210 . N-type ions are doped in the first source region and the first drain region, and P-type ions are doped in the second source region and the second drain region. It should be noted that there is a first isolation structure 204 in the substrate 200 between the adjacent second dummy gate structure 202 and the first dummy gate structure 201, and the material of the second isolation structure 206 is silicon oxide, nitrogen One or more combinations of silicon oxide and silicon oxynitride, the first isolation structure 204 is used to isolate the subsequently formed PMOS transistor and NMOS transistor.

In this embodiment, since the second dummy gate structure 202 is used to form a PMOS transistor, in order to enhance the performance of the PMOS transistor, stress layers are formed in the substrate 200 on both sides of the second dummy gate structure 202 205 , the stress layer 205 is made of silicon germanium, and P-type ions are doped in the stress layer 205 to form a second source region and a second drain region.

In this embodiment, the substrate 200 in the second region 220 has a second isolation structure 206, and the position of the subsequently formed device structure corresponds to the second isolation structure 206, so as to enhance the compatibility between the device structure and the substrate. Electrical isolation performance between bottom 200. The material of the second isolation structure 206 is one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the second isolation structure 206 can be formed simultaneously with the first isolation structure 204 .

After the first dummy gate structure 201 and the second dummy gate structure 202 are formed on the surface of the substrate 200, and the first source region, the first drain region, the second source region and the second drain region are formed, the substrate A dielectric layer 203 is formed on the surface of the bottom 200 . The dielectric layer 203 is used to electrically isolate the transistors formed by the first dummy gate structure 201 and the second dummy gate structure 202, and can preserve the structure and structure of the first dummy gate layer 201a and the second dummy gate layer 202a Location. The material of the dielectric layer 203 is silicon oxide, silicon nitride or silicon oxynitride, and the formation process includes: forming a dielectric film on the surface of the substrate 200, the first dummy gate structure 201 and the second dummy gate structure 202 by a deposition process ; Perform a polishing process on the dielectric film until the top surfaces of the first dummy gate structure 201 and the second dummy gate structure 202 are exposed.

Referring to FIG. 2 , the second dummy gate layer 202 a (as shown in FIG. 1 ) is removed, and a third opening is formed in the dielectric layer 203 ; a second gate 207 is formed in the third opening.

For high-K metal gate transistors, after removing the dummy gate layer and before forming the metal gate, a work function layer can also be formed on the surface of the high-K gate dielectric layer, and the work function layer or metal gate in PMOS transistors and NMOS transistors The materials are different, so that the threshold voltage of the PMOS transistor and the NMOS transistor can be adjusted to enhance the performance of the PMOS transistor and the NMOS transistor.

In this embodiment, the first dummy gate structure 201 is used to form an NMOS transistor, and the second dummy gate structure 202 is used to form a PMOS transistor. In order to make the formed PMOS transistor and NMOS transistor have work function layers or metal gates of different materials, the second dummy gate layer 202 a is removed first, and a third opening is formed in the dielectric layer 203 .

The third opening is used to form the second gate 207, which is the metal gate of the PMOS transistor to be formed. After forming the second gate 207, remove the first dummy gate layer 201a, and form the first gate at the position of the first dummy gate layer 201a, and the material of the first gate can be compatible with the second The materials of the gate 207 are different.

The forming process of the third opening includes: forming a first photoresist layer on the surface of the dielectric layer 203 and the first dummy gate structure 201 by using a photolithography process, and the first photoresist layer exposes the second dummy gate structure. Corresponding position of the gate layer 202a: using the first photoresist layer as a mask, etch the second dummy gate layer 202a until the second gate dielectric layer is exposed to form a third opening. Wherein, before forming the first photoresist layer, a first mask layer is formed on the surface of the dielectric layer 203 and the first dummy gate structure 201, and the first mask layer is etched with the first photoresist layer Until the surface of the second dummy gate layer 202a is exposed, the second dummy gate layer 202a is removed using the first mask layer as a mask. The process of removing the second dummy gate layer 202a is a dry etching process or a wet etching process. Since the material of the second dummy gate layer 202a is polysilicon, it is the second dummy gate layer 202a and the second side There is etching selectivity between the wall 202b or the second gate dielectric layer, and when the second dummy gate layer 202a is removed, the damage to the second spacer 202b or the second gate dielectric layer is relatively small.

The material of the second gate 207 is metal, and the metal is tungsten or aluminum; the formation process of the second gate 207 includes: on the surface of the dielectric layer 203, the surface of the first dummy gate structure 201, and A second gate film filling the third opening is formed in the third opening; a polishing process is performed on the second gate film until the dielectric layer 203 and the surface of the first dummy gate structure 201 are exposed. In addition, before forming the second gate film, a second work function film can also be formed on the surface of the dielectric layer 203 and the first dummy gate structure 201, and the sidewall and bottom surface of the third opening, the The polishing process also polishes the second work function film until the dielectric layer 203 and the surface of the first dummy gate structure 201 are exposed. The formation process of the second gate film or the second work function film is a physical vapor deposition process or a chemical vapor deposition process.

Referring to FIG. 3 , after forming the second gate 207 , a first opening 208 is formed in the dielectric layer 203 of the second region 220 .

The first opening 208 is used to form a device structure, and in this embodiment, the material of the device structure is metal. Since the first opening 208 is formed before the subsequent formation of the first gate, and the material of the first gate is also metal, the first opening 208 can be formed at the same time as the first gate is formed. The device structure is formed inside, so that the forming process of the device structure can be integrated with the forming process of the high-K metal gate transistor, and the process is simplified.

The position of the first opening 208 corresponds to the second isolation structure 206, so that the subsequently formed device structure overlaps with the second isolation structure 206, thereby enhancing the electrical isolation between the device structure and the substrate 200, and reducing the The small overlap capacitance between the device structure and the substrate 200 stabilizes the performance of the device structure.

The forming process of the first opening 208 includes: using a photolithography process to form a second photoresist layer on the surface of the dielectric layer 203, the first dummy gate structure 201 and the second gate 207, and the second photoresist layer Exposing the surface of the dielectric layer 203 where the first opening 208 needs to be formed; using the second photoresist layer as a mask, using an anisotropic dry etching process to etch the dielectric layer 203, in the A first opening 208 is formed in the dielectric layer 203; after the first opening 208 is formed, the second photoresist layer is removed. The bottom of the first opening 208 can expose the second isolation structure 206 , or the bottom of the first opening 208 is the dielectric layer 203 .

Please refer to FIG. 4 , a second mask layer 209 is formed on the surface of the dielectric layer 203 and the sidewall and bottom surface of the first opening 208, and the second mask layer 209 exposes the surface of the first dummy gate layer 201a. .

The second mask layer 209 is used as a mask for etching and removing the first dummy gate layer 201a, and at the same time, it can be used as a polishing stop layer to prevent the dielectric layer 203 and the second The surface of the gate 207 is damaged during the polishing process.

The material of the second mask layer 209 is one or more combinations of titanium, titanium nitride, tantalum and tantalum nitride, and the second mask layer 209 is relative to the second dummy gate layer 202a and subsequent The formed second gate is selective so as to maintain pattern stability when the second dummy gate layer 202a is subsequently removed and the second gate film is polished.

Since the second mask layer 209 is used as a stop layer during subsequent polishing of the first gate film, that is, before the subsequent formation of the first gate film, the second mask layer 209 remains. Since the material of the second mask layer 209 is a conductive material, and the material of the subsequently formed device structure is metal, the second mask layer 209 formed on the sidewall and bottom surface of the first opening 208 will not affect the formed affect the performance of the device structure.

The formation process of the second mask layer 209 is as follows: a deposition process is used to form a second mask layer on the surface of the dielectric layer 203, the surface of the second gate 207 and the first dummy gate structure 201, and the sidewall and bottom surface of the first opening 208. Two mask films; a third photoresist layer is formed on the surface of the second mask film, and the third photoresist layer at least exposes the corresponding position of the first dummy gate layer 201a; The resist layer etches the second mask film until the top surface of the second dummy gate layer 201a is exposed to form a second mask layer 209; after the second mask layer 209 is formed, the third mask layer is removed. photoresist layer. Wherein, the etching process is an anisotropic dry etching process, which can make the pattern of the second mask layer consistent with the pattern of the third photoresist layer.

Please refer to FIG. 5 , using the second mask layer 209 as a mask, etch and remove the first dummy gate layer 201 a (as shown in FIG. 4 ), and form a second opening 230 in the dielectric layer 203 .

In this embodiment, the second opening 230 is used to form the first gate, which is the metal gate of the NMOS transistor to be formed. The process of removing the first dummy gate layer 201a is a dry etching process or a wet etching process. Since the material of the second dummy gate layer 202a is polysilicon, the second dummy gate layer 202a and the second The spacer 202b or the second gate dielectric layer has etching selectivity, and when the second dummy gate layer 202a is removed, the shape of the second spacer 202b or the second gate dielectric layer can be kept stable. Preferably, the process of removing the first dummy gate layer 201a is a wet etching process, and the wet etching process does less damage to the first spacer 201b and the second gate dielectric layer.

Referring to FIG. 6 , a conductive layer 231 is formed on the surface of the second mask layer 209 , the first opening 208 (as shown in FIG. 5 ) and the second opening 230 (as shown in FIG. 5 ).

Since there is a first opening 208 in the first region 210 and a second opening 230 in the second region 220, and the device structure to be formed and the material of the first gate are both metal, the conductive layer 231 can formed in the first opening 208 and the second opening 230 at the same time. Wherein, the conductive layer 231 in the first opening 208 is used to form a first gate, and the conductive layer 231 in the second opening 230 is used to form a device structure, and the device structure includes a fuse structure or a resistor structure. Therefore, it is possible to avoid additionally forming a metal layer to form the device structure, so that the forming process of the high-K metal gate transistor and the forming process of the device structure can be integrated, and the process steps can be simplified.

In this embodiment, the material of the conductive layer 231 is tungsten or aluminum, the formation process of the conductive layer 231 is a chemical vapor deposition process or a physical vapor deposition process, and the formed conductive layer 231 needs to fill the first opening 208 and a second opening 230 .

In this embodiment, before the conductive layer 231 is formed, a deposition process is used to form a first electrode on the surface of the dielectric layer 203 and the second gate 207, as well as the side walls and bottom surfaces of the first opening 208 and the second opening 230. A work function film (not shown), the material of the first work function film is a conductive material. The first work function film forms a first work function layer after a subsequent polishing process, and the first work function layer is used to adjust the threshold voltage of the NMOS transistor, and the material of the first work function layer and the second work function layer The materials of the functional layers are different. Since the material of the first work function film is a conductive material, the first work function film formed on the sidewall and bottom surface of the first opening 208 will not affect the performance of the formed device structure.

In other embodiments, the conductive layer can also be directly formed in the first opening 208 and the second opening 230 .

Please refer to FIG. 7 , polish the conductive layer 231 (as shown in FIG. 6 ) and the second mask layer 209 until the dielectric layer 203 is exposed, and form a first The gate 232 forms a device structure 233 in the first opening 208 (as shown in FIG. 5 ).

In the polishing process, the second mask layer 209 is used as a stop layer of the polishing process, and after the second mask layer 209 is exposed in the polishing process, polishing is performed until the surface of the dielectric layer 203 is exposed; or After the second mask layer 209 is exposed by the polishing process, the second mask layer 209 on the surface of the dielectric layer 203 is removed by an etching process.

The material of the first gate 232 is tungsten or aluminum. In this embodiment, the polishing process also polishes the first work function film on the surface of the dielectric layer 203, and there is also a first work function layer between the first gate dielectric layer and the first gate 232 .

In this embodiment, the device structure 233 is a fuse structure, and the fuse structure includes a first work function film located on the sidewall and bottom surface of the first opening 208, and a conductive layer 231 located in the first opening 208; Moreover, there is a second mask layer 209 between the first work function film and the dielectric layer 203 . Since the materials of the second mask layer 209 , the first work function film and the conductive layer 231 are all conductive materials, the performance of the formed device structure 233 is stable.

The fuse structure includes: a cathode area and an anode area located at two ends, and a fusing area located between the cathode area and the anode area. The width of the cathode region or the anode region parallel to the surface of the substrate 200 is relatively large, while the width of the fusing region parallel to the surface of the substrate 200 is relatively small. When a bias voltage is applied between the cathode region and the anode region, The resistance of the fuse zone is relatively large, so it will preferentially fuse due to heat.

In other embodiments, the device structure 233 is a resistance structure, and two ends of the resistance structure have electrode regions. The resistance structure includes a mask layer, a first work function film and a conductive layer 231 . The pattern of the resistance structure parallel to the surface of the substrate 200 depends on the specific technical requirements of the resistance.

It should be noted that, after the polishing process, an insulating layer is formed on the surface of the dielectric layer 203, the device structure 233, the first gate 232 and the second gate 207, and an insulating layer is formed in the insulating layer and the dielectric layer 203. The first conductive plug and the second conductive plug. Wherein, the first conductive plug is formed in the first region 210, and is formed in one of the first source region, the first drain region, the second source region, the second drain region, the first gate 232, and the second gate 207. one or more surfaces; the second conductive plug is formed in the second region 220 for realizing the electrical connection of the device structure in the circuit. In this embodiment, the device structure 233 is a fuse structure, and the second conductive plug is formed on the surface of the cathode region and the anode region of the fuse structure. In other embodiments, the device structure 233 is a resistance structure, and the second conductive plug is formed on the surface of the electrode region of the resistance structure.

In this embodiment, before removing the first dummy gate layer, a first opening is formed in the dielectric layer in the second region, and the first opening is used to form a device structure. After removing the first dummy gate layer, a second opening can be formed in the dielectric layer, that is, the dielectric layer in the first region has a second opening, and the dielectric layer in the second region has a first opening, The second opening is used to form the first gate of the transistor. Afterwards, a conductive layer can be simultaneously formed in the first opening and the second opening; wherein, the conductive layer located in the first opening serves as the first gate of the transistor, and the conductive layer located in the second opening serves as the device structure, Examples are fuse structures or resistor structures. Therefore, in the process of forming the transistor, the device structure can be formed at the same time, so that the formation process of the semiconductor device can be simplified, the process time can be reduced, and the cost can be saved.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (13)

1. a kind of forming method of semiconductor devices, which is characterized in that including：

Substrate is provided, the substrate includes first area and second area, and the first area surface has the first dummy grid knot Structure, first dummy gate structure include the first dummy gate layer positioned at substrate surface, and the substrate surface has dielectric layer, institute The surface for stating dielectric layer is flushed with the surface of the first dummy gate structure；

The first opening is formed in the dielectric layer of the second area；

The side wall and bottom surface being open in dielectric layer surface and first form mask layer, and the mask layer exposes described First dummy gate layer surface；

Using the mask layer as mask, etching removes first dummy gate layer, and the second opening is formed in dielectric layer；

Conductive layer is formed in the mask layer surface, the first opening and the second opening；

The conductive layer and mask layer are polished, until exposing dielectric layer, first grid is formed in the second opening, the Device architecture is formed in one opening, the device architecture is fuse-wires structure or electric resistance structure, and the device architecture includes mask layer And conductive layer.

2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the conductive layer includes tungsten Or aluminium.

3. the forming method of semiconductor devices as described in claim 1, which is characterized in that the material of the mask layer be titanium, One or more combinations in titanium nitride, tantalum and tantalum nitride.

4. the forming method of semiconductor devices as described in claim 1, which is characterized in that tool in the substrate of the second area There are the second isolation structure, the position of first opening corresponding with second isolation structure.

5. the forming method of semiconductor devices as described in claim 1, which is characterized in that first dummy gate structure both sides Substrate in be respectively provided with the first source region and the first drain region.

6. the forming method of semiconductor devices as claimed in claim 5, which is characterized in that first source region and the first drain region It is interior doped with p-type ion, the first grid is for constituting PMOS transistor.

7. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that in first dummy gate structure two Form stressor layers in the substrate of side, the materials of the stressor layers is SiGe, the doped p-type ion in the stressor layers, forms the One source region and the first drain region.

8. the forming method of semiconductor devices as claimed in claim 5, which is characterized in that first source region and the first drain region It is interior doped with N-type ion, the first grid is for constituting NMOS transistor.

9. the forming method of semiconductor devices as described in claim 1, which is characterized in that the substrate surface of the first area It includes the second dummy gate layer positioned at substrate surface also to have the second dummy gate structure, second dummy gate structure, and described the It is respectively provided with the second source region and the second drain region in the substrate of two dummy gate structure both sides, the crystalline substance formed using the second dummy gate structure Body pipe is opposite with the transistor types formed using the first dummy gate structure.

10. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that before forming the first opening, go Except second dummy gate layer, third opening is formed in the dielectric layer；Second grid is formed in the third is open.

11. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that adjacent second dummy gate structure and In substrate between first dummy gate structure there is the first isolation structure to be isolated.

12. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that second source region and the second leakage When the conduction type in area is p-type, stressor layers, the material of the stressor layers are formed in the substrate of second dummy gate structure both sides Material is SiGe, and the doped p-type ion in the stressor layers forms the second source region and the second drain region.

13. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that first dummy gate structure is also Include the first gate dielectric layer positioned at substrate surface, first dummy gate layer is located at the first grid dielectric layer surface, described The material of first gate dielectric layer is hafnium；Second dummy gate structure further includes the second gate medium positioned at substrate surface Layer, second dummy gate layer are located at the second gate dielectric layer surface, and the material of second gate dielectric layer is hafnium.