CN104679592A - Method and system for dynamically distributing resources in microcontroller unit MCU - Google Patents
Method and system for dynamically distributing resources in microcontroller unit MCU Download PDFInfo
- Publication number
- CN104679592A CN104679592A CN201310638362.9A CN201310638362A CN104679592A CN 104679592 A CN104679592 A CN 104679592A CN 201310638362 A CN201310638362 A CN 201310638362A CN 104679592 A CN104679592 A CN 104679592A
- Authority
- CN
- China
- Prior art keywords
- flash
- block
- flash memory
- storage block
- mcu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a method and a system for dynamically distributing resources in a microcontroller unit MCU. The MCU comprises a processor and a static random access memory, wherein the static random access memory comprises a plurality of memory blocks. The method comprises the following steps: the MCU receives a pre-set flash memory capacity which is configured by the processor when an application program is applied; the pre-set flash memory capacity is smaller than a maximum flash memory capacity of the static random access memory; a flash memory storage block for flash memory storage and an internal memory storage block for internal memory storage in the static random access memory are distributed according to the pre-set flash memory capacity; program data in the flash memory storage block is read and executed, and data interaction is carried out with the internal memory storage block. The method and the system can be suitable for requirements of different products, different customers and different application scenes, and a condition that the flash memory capacity is idle and wasted and the internal memory capacity is not enough is avoided.
Description
Technical field
The embodiment of the present invention relates to MCU technical field, particularly relates to read method and the system of the system configuration information in a kind of MCU.
Background technology
Micro-control unit (Micro Control Unit, MCU), also known as one chip microcomputer (Single Chip Microcomputer, or single-chip microcomputer SCM), refer to the appearance along with large scale integrated circuit and development thereof, by central processing unit (the Central Processing Unit of computing machine, CPU), static RAM (Static Random Access Memory, SRAM), ROM (read-only memory) (Read-Only Memory, ROM), timer conter and multiple I/O Interface integration are on one chip, form the computing machine of chip-scale, do various combination for different application scenarios to control.Wherein, whole SRAM is divided into internal memory SRAM and flash memory SRAM, and internal memory SRAM scratch-pad memory data, flash memory SRAM keeps in flash memory chip data.
MCU is general-purpose chip, according to individual demand, MCU chip generally can customize multiple product line (several even can reach tens product lines), in chip, the size of flash memory SRAM is determined according to maximum flash capacity, and due to the individual demand of different product, the demand of its flash capacity is also different, but so in a lot of personalized tailor-made product, do not need to support maximum flash capacity, thus the idle waste of some flash memories SRAM can be caused.Further, when there is the flash memory SRAM of idle waste, chip area can be made bigger than normal than actual demand more, be unfavorable for chip miniaturization.
On the other hand, the flash capacity of each product and memory size are fixing, so often there is the idle waste of some flash memories SRAM on the one hand, and the situation that memory size is not enough.
In addition, the Area comparison of whole SRAM is large, and therefore in chip production, SRAM occurs that the probability of defect is corresponding higher, and the processing mode generally taked is abandoned by this chips, and defect all appears in fact not all SRAM block, part SRAM block is only had to occur defect in most cases.So, only have a fritter SRAM to occur defect in process of production, whole chip will be caused to abandon, cause the huge waste of chip.
Summary of the invention
The invention provides a kind of read method and system of the system configuration information overcome in the problems referred to above or the MCU that solves the problem at least in part.
The invention provides the method for Resource dynamic allocation in a kind of micro-control unit MCU, described MCU comprises processor and static RAM, and described static RAM comprises multiple storage block, and described method comprises:
Described MCU receives the default flash capacity that described processor configures when running application, and described default flash capacity is less than the maximum flash capacity of described static RAM;
Distribute in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory according to described default flash capacity;
Read and perform the routine data in described flash memory storage block, carrying out data interaction with described memory block simultaneously.
Preferably, described MCU also comprises control information storer, and described control information storer stores the bad block message of described static RAM;
Receive the step of the default flash capacity that described processor configures when running application at described MCU before, described method also comprises:
After described MCU electrification reset, described MCU reads described bad block message from described control information storer;
The bad block of described static RAM is labeled as unavailable, and reorganizes the position of the storage block of non-bad block according to described bad block message.
Preferably, described control information storer also stores described maximum flash capacity information, and receive the step of the default flash capacity that described processor configures when running application at described MCU before, described method also comprises:
According to after described MCU electrification reset, described MCU reads described maximum flash capacity information from described control information storer;
Distribute the flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity information, after distributing, remaining storage block is the memory block for memory;
Read the routine data in described flash memory storage block, and run described routine data.
Preferably, described MCU is also connected with flash chip, and described method also comprises:
If described MCU first time powers on, then copy routine data in described flash chip to described static RAM for the flash memory storage block of flash memory storage.
Preferably, described default flash capacity is the number of required storage block, described storage block has respective numbering, and described step of distributing the flash memory storage block for flash memory storage and the memory block for memory in static RAM according to default flash capacity comprises:
The number of the numbering of each storage block and required storage block is compared;
Described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory.
Preferably, described MCU and described flash chip separate and in outside physical connection, or described flash chip is integrated in described MCU.
Preferably, described MCU also comprises Flash memory bus interface and system bus, and described MCU, by described Flash memory bus interface and described system bus, receives the default flash capacity that described processor configures when running application.
Present invention also offers the system of Resource dynamic allocation in a kind of micro-control unit MCU, described MCU comprises processor and static RAM, and described static RAM comprises multiple storage block;
Described MCU also comprises configuration deposit unit and storage block allocation units:
Described configuration deposit unit, for receiving the default flash capacity that described processor configures when running application, described default flash capacity is less than the maximum flash capacity of described static RAM;
Described storage block allocation units, for distributing according to described default flash capacity in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory;
Described processor, for reading and performing the routine data in described flash memory storage block, carries out data interaction with described memory block simultaneously.
Preferably, described MCU also comprises control information storer, and described control information storer stores the bad block message of described static RAM;
Described MCU also comprises:
Main control unit, for after described MCU electrification reset, reads described bad block message from described control information storer;
Static RAM recomposition unit, for being labeled as unavailable by the bad block of described static RAM, and reorganizes the position of the storage block of non-bad block according to described bad block message.
Preferably, described control information storer also stores described maximum flash capacity information;
Described main control unit, also for according to after described MCU electrification reset, reads described maximum flash capacity information from described control information storer;
Described storage block allocation units, also for distributing the flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity information, after distributing, remaining storage block is the memory block for memory.
Preferably, also comprise the flash chip be connected with described MCU, described system also comprises:
Flash memory control module, if power on for described MCU first time, then copies routine data in described flash chip to described static RAM for the flash memory storage block of flash memory storage.
Preferably, described default flash capacity is the number of required storage block, and described storage block has respective numbering, and described storage block allocation units comprise:
Relatively subelement, for comparing the number of the numbering of each storage block and required storage block;
Chooser unit, for described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory.
Preferably, described MCU and described flash chip separate and in outside physical connection, or described flash chip is integrated in described MCU.
Preferably, described MCU also comprises Flash memory bus interface and system bus, and described configuration deposit unit and described storage block allocation units are by described Flash memory bus interface and described system bus and described processor communication.
Compared with prior art, the embodiment of the present invention comprises following advantage:
According to the embodiment of the present invention, when total static RAM SRAM resource is fixing, flash memory and internal memory capacity is separately configured to MCU by application deployment, then according to flash capacity, the size of storage allocation and flash memory shared static RAM separately, thus can different product be adapted to, different client, demand under different application scene, avoid occurring the idle waste of flash capacity, and the situation that memory size is not enough, reach the most effectively utilizing of SRAM resource, and the usability of chip can be improved by the demand meeting internal memory.Meanwhile, adopt the embodiment of the present invention, the existence avoiding the flash memory SRAM of idle waste makes chip area bigger than normal than actual demand more, is beneficial to chip miniaturization.
And, according to the embodiment of the present invention, maximum flash capacity can also be configured in control information storer OTP, after chip electrification reset, namely according to configuration maximum flash capacity storage allocation and flash memory separately shared by the size of static RAM, thus no application scenarios and demand can be adapted to.
According to the embodiment of the present invention, defect may be produced for SRAM and cause the non-serviceable problem of SRAM, the present invention is equally by reasonably allocating SRAM resource, bad block is labeled as unavailable, available SRAM is reconfigured and renumbers, this chips still can be used on some product, and be unlikely to abandon.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the method for Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention one;
Fig. 2 is the process flow diagram of the method for Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention two;
Fig. 3 is the one-piece construction figure of a kind of MCU of the embodiment of the present invention three;
Fig. 4 is the structural representation of a kind of static RAM of the embodiment of the present invention three;
Fig. 5 is the structural representation of a kind of flash controller of the embodiment of the present invention three;
Fig. 6 is the structural representation of a kind of Memory Controller Hub of the embodiment of the present invention three;
Fig. 7 is the structural representation of a kind of static RAM of the embodiment of the present invention three;
Fig. 8 is the process flow diagram of the method for Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention three;
Fig. 9 is the structured flowchart of the system of Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention four.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
In embedded MCU System on Chip/SoC, because MCU is as general chip, usually need a chips and customize out multiple product, memory size size required by each product, flash capacity size is all inconsistent, because the data in advance in flash memory SRAM reads from flash chip, therefore the size of flash memory SRAM will be determined according to the capacity of flash chip, be generally the maximum flash space of setting.And in fact, in conventional art practical application, user is when reality uses certain product, major applications scene all can not use the maximum flash space that product is arranged, and only uses a part wherein, and now a part of flash memory SRAM can leave unused waste equally; Area further due to flash memory SRAM is very large, and sometimes may reach 1/3 of the chip total area, the waste of flash memory SRAM can make chip area bigger than normal than actual demand more, is unfavorable for chip miniaturization.
Internal memory is the key device of CPU working procedure, its large low capacity is directly connected to speed and the efficiency of CPU operation, yes is the bigger the better, but memory size becomes large, directly can cause the increase of chip area, the therefore size of internal memory one of bottleneck of running of CPU often, the situation of Out of Memory is usually there is in the application of reality, thus cause in whole chip, there is waste in flash memory SRAM on the one hand, and internal memory SRAM is not enough on the other hand.
In addition, chip production is a complicated process, also a lot of technological process methods is had, but regardless of which kind of production method, all can not ensure that all chips have been all sheets, chip production out after, enter chip testing phase, it has been sheet that test phase distinguishes that chips exactly, and that chips is bad sheet.Such as, Memory BIST test is at chip testing phase, for testing the whether intact method of testing of SRAM.Can test out those SRAM blocks good, those SRAM blocks are defective, and for GD32F1xx family chip, the ratio of defects of SRAM reaches 1.7%.And bad sheet generally processes and all abandons, thus chip is caused to be wasted.
In view of this, one of core idea of the embodiment of the present invention is, by application program flexible configuration flash memory SRAM and internal memory SRAM capacity separately, make with in a product, can according to different application scenarioss, to the different demands of flash memory SRAM and internal memory SRAM capacity separately, configuration flash memory SRAM capacity and internal memory SRAM capacity separately, reach the demand of different application scene.
Below, by each embodiment following, the system and method for Resource dynamic allocation in micro-control unit MCU of the present invention is introduced.
Embodiment one:
With reference to Fig. 1, show the process flow diagram of the method for Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention one, described MCU comprises processor and static RAM, and described static RAM comprises multiple storage block, and the method can comprise the following steps:
Step 101, described MCU receive the default flash capacity that described processor configures when running application, and described default flash capacity is less than the maximum flash capacity of described static RAM.
In the embodiment of the present invention, MCU comprises the processor (CPU) for the treatment of application program, and static memory SRAM, and static memory comprises multiple storage block, may be used for storing flash memory or the data of internal memory.In the embodiment of the present invention, application program can carry default flash capacity, and user can according to different application scenarioss, and to the different demands of flash memory SRAM and internal memory SRAM capacity separately, flash memory SRAM capacity is determined in configuration, reaches the demand of different application scene.Processor is when processing application program, this flash capacity is sent to MCU, wherein, described default flash capacity is less than the maximum flash capacity of described static RAM, maximum flash capacity can be the flash capacity maximal value for SRAM presets, and can read from the control information storer of outside.
Step 102, to distribute in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory according to described default flash capacity.
MCU distributes SRAM according to the flash capacity arranged, specifically, can distribute flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity, after then distributing, remaining storage block is as the memory block being used for memory.
Such as, in the prior art, a product flash capacity is 512Kbytes, and memory size is 64Kbytes.Under a lot of application scenarios, do not need so large flash memory space, and memory headroom is often not enough, such as, program needs the internal memory SRAM using 96Kbytes, and adopts the scheme of prior art cannot head it off, can only be solved by some software approach such as more program schedulers, thus waste a large amount of program execution time, processor executive routine efficiency is declined greatly.And can by the mode of program configuration registers by the method for the embodiment of the present invention, reduce flash memory SRAM capacity, as above flash capacity can be configured to 480Kbytes in example, thus internal memory SRAM capacity increases to 96Kbytes, as can be seen here, different product can be adapted to, different client according to the embodiment of the present invention, demand under different application scene, avoids occurring the idle waste of flash capacity.
And, because the configuration of flash capacity is arranged by application program, determined by the user of product completely, so the user of product according to the applicable cases of self, under the prerequisite that total SRAM capacity is fixing, can determine flash memory SRAM and internal memory SRAM capacity separately completely flexibly, thus at the larger internal memory SRAM of needs, and when not needing maximum flash SRAM capacity, make the service efficiency that SRAM reaches optimum, the usability of chip is improved by the size improving internal memory.
In addition, adopt the embodiment of the present invention, the existence of the flash memory SRAM of idle waste can be avoided to make chip area bigger than normal than actual demand more, be beneficial to chip miniaturization.
Step 103, read and perform the routine data in described flash memory storage block, carrying out data interaction with described memory block simultaneously.
After distributing the storage space of flash memory and internal memory, the routine data in flash memory storage block can be obtained further by the processor of MCU, and perform described routine data, in normal procedure implementation, mainly reading flash memory SRAM, executive routine, and redirect between read/write memory three states, some intermediate data or operation results etc. in processor executive routine process, need stored in internal memory, or read from internal memory.
Embodiment two:
With reference to Fig. 2, show the process flow diagram of the read method of the system configuration information of a kind of MCU of the embodiment of the present invention two.
In the embodiment of the present invention, described MCU comprises processor and static RAM, and described static RAM comprises multiple storage block.
The method can comprise the following steps:
Step 201, after described MCU electrification reset, described MCU reads described bad block message from described control information storer.
Step 202, the bad block of described static RAM is labeled as unavailable, and reorganizes the position of the storage block of non-bad block according to described bad block message.
With last embodiment unlike, in the present embodiment, described MCU also comprises control information storer, and described control information storer stores the bad block message of described static RAM.
Control information storer adopts OTP(One Time Programmable, One Time Programmable) storage mode, usually pass through certain test case in the product test stage, by disposable for information programming products configuration information, after ensureing storer power-off, data do not regret loss.In the embodiment of the present invention, the bad block message of static RAM can be stored in OTP.Described MCU electrification reset reads described bad block message from OTP, after obtaining bad block message, the bad block message of static memory can be labeled as unavailable, then reorganizes the position of the storage block of non-bad block according to bad block message.
Specifically, disabled SRAM block can be eliminated, be arranged to unavailable by the numbered register of this SRAM block, then reorganized by available SRAM, the numbered register corresponding by available SRAM block numbers in order again, thus ensure when reading the data of SRAM, the storage block of numbering all can use, and avoids having access to bad block, not only can avoid accessing unsuccessfully, and this chips still can be used on some product, and be unlikely to abandon.
Such as, be 512Kbytes at flash capacity, memory size is in the chip of 64Kbytes, SRAM is divided into the SRAM block (9 × 64=512+64) of 9 64Kbytes, if by test, and wherein 2 SRAM block defectiveness, adopt in prior art, any SRAM defectiveness can only abandon, and therefore, this SRAM will abandon.And adopt the embodiment of the present invention, when programming OTP, be arranged to unavailable by these two SRAM blocks, other are arranged to available, by SRAM recombinant technique, this chips still can be used for the product that total SRAM size is no more than 7 × 64Kbytes, and such as flash capacity is 384Kbytes, and memory size is 64Kbytes, therefore, the embodiment of the present invention, by SRAM reorganization scheme, makes the defective chip of certain block SRAM, still can be used in certain product.
Step 203, basis are after described MCU electrification reset, and described MCU reads described maximum flash capacity information from described control information storer.
Step 204, distribute the flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity information, after distributing, remaining storage block is the memory block for memory.
Step 205, the routine data read in described flash memory storage block, and run described routine data.
In the embodiment of the present invention, control information storer also comprises maximum flash capacity information, namely can store the maximum flash capacity of flash data in SRAM, so can the individual cultivation of each product is stored in OTP, with the equally disposable programming of bad block message in OTP.
Also do not read after MCU electrification reset and working procedure data, when now accessing SRAM, the configuration that can realize flash memory and memory size by OTP, namely according to the size of the shared static RAM separately of maximum flash capacity storage allocation and flash memory in OTP, thus no application scenarios and demand can be adapted to.
Specifically, after MCU electrification reset, first from control information storer, described maximum flash capacity information is read, then can distribute flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity, after distributing, remaining storage block is as the memory block being used for memory.
After the capacity distributing flash memory and internal memory in SRAM, the routine data in flash memory storage block can be read, and run described routine data, while the described routine data of operation, if desired preserve result or need to read data from internal memory, processor can carry out data interaction with described memory block simultaneously.
If step 206 described MCU first time powers on, then copy routine data in described flash chip to described static RAM for the flash memory storage block of flash memory storage.
If MCU powers on first time, then need to copy flash memory, disposable flash chip Program data etc. are all copied in flash memory SRAM, when the processor of MCU needs the data of accessing flash memory, directly can access flash memory storage block in SRAM.
Step 207, described MCU receive the default flash capacity that described processor configures when running application, and described default flash capacity is less than the maximum flash capacity of described static RAM.
Step 208, to distribute in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory according to described default flash capacity.
Step 209, read and perform the routine data in described flash memory storage block, carrying out data interaction with described memory block simultaneously.
In the embodiment of the present invention, preferably, described default flash capacity is the number of required storage block, described storage block has respective numbering, describedly distribute flash memory storage block for flash memory storage in static RAM according to default flash capacity, after distributing, remaining storage block is comprise for the step of the memory block of memory:
Sub-step S11, the number of the numbering of each storage block and required storage block to be compared.
Sub-step S12, described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory.
In the embodiment of the present invention, default flash capacity is the number of required storage block, available storage block all has corresponding numbering (such as, when there is n storage block, numbering is followed successively by 0, 1, 2 ... n), when distributing the memory capacity of flash memory and internal memory according to default flash capacity, the storage block of flash memory and internal memory can be distributed according to numbering size, the preferred mode of the embodiment of the present invention is, described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory, such as, default flash capacity is 10, then will be numbered the storage block of 0 ~ 9 as the flash memory storage block being used for flash memory storage, using the storage block of numbering 10 ~ n as the memory block being used for memory.
In concrete realization, described MCU and described flash chip can be separate and in outside physical connection, or also described flash chip can be integrated in described MCU.
In concrete realization, described MCU can also comprise Flash memory bus interface and system bus, and described MCU, by described Flash memory bus interface and described system bus, receives the default flash capacity that described processor configures when running application.
Below, by embodiment three, resource dynamic distributing method in micro-control unit MCU of the present invention is described in detail.
Embodiment three:
First, introduce the one-piece construction of the MCU in the embodiment of the present invention, as shown in Figure 3, this MCU can comprise CPU301, SRAM302, OTP303, flash controller 304, Memory Controller Hub 305, flash chip 306 and system bus 307.Be described below respectively:
CPU301:CPU handling procedure data, routine data can read from flash memory.
SRAM302:SRAM is standard I P, deposits data in internal storage data and flash chip in the present invention, loss of data after power-off, and read or write speed is fast, can read and write in real time.
OTP303:OTP is a kind of storage class, is meant to One Time Programmable, and usually in product test stage disposable programming products configuration information, power-off data are not lost.
Flash controller 304: the function of flash controller is the outer flash memory of control strip, comprises and performs the data manipulation such as reading and writing, erasing, read ID, read states etc.
Memory Controller Hub 305: internal memory Main Function is the place of temporary program or data in CPU executive routine, and Memory Controller Hub Main Function is, by the read-write operation that system bus sends to internal memory, changes into the read-write operation of internal memory SRAM.
Flash chip 306: flash memory is conventional chip, readable, erasable, power-off data are not lost, but read or write speed is slow, and the most of the time reads, and is mainly used in storage program and some changeless data in MCU system.This MCU and flash chip can be separate and in outside physical connection, in order to make the volume of product smaller and more exquisite, can adopt MCP(Multiple Chip Package, many preparative layers packaged chip) master chip and flash chip be manufactured in same encapsulation by technology.
System bus 307:MCU passes through system bus, the default flash capacity that receiving processor configures when running application.
MCU shown in Fig. 3 can also comprise DMA(Direct Memory Access, direct memory access) and multiple external equipment (equipment 1, equipment 2 etc.), DMA can realize the data transmission between peripheral hardware efficiently, to arrange in pairs or groups in MCU chip some external equipments, such as SPI(Serial Peripheral Interface, Serial Peripheral Interface (SPI)), UART(Universal Asynchronous Receiver Transmitter, universal asynchronous receiving-transmitting transmitter), i2C(Inter-Integrated Circuit, inter-integrated circuit) etc., different MCU may arrange in pairs or groups different peripheral hardwares, or the peripheral hardware of different number of arranging in pairs or groups.
As shown in Figure 4, the structural representation of static RAM 302 in the embodiment of the present invention three is given.SRAM302 is standard I P, and whole SRAM space is divided into internal memory SRAM3021 and flash memory SRAM3022.Internal memory SRAM3021 scratch-pad memory data, flash memory SRAM3022 keeps in flash memory chip data.
As shown in Figure 5, the structural representation of flash controller 304 in the embodiment of the present invention three is given.Be described below respectively:
Flash memory bus interface 3041: the function of Flash memory bus interface is the read-write operation read and write access of system bus being converted into flash controller inside.The access of system bus is divided into two classes according to the difference of address space by Flash memory bus interface: a class is access configuration register, and a class is access program storage space.Configuration register is accessed by data path 2; Program's memory space is accessed by data path 1.
Configuration register 3042: mainly comprise a series of register, which stores configuration information and the status information of flash controller.Configured by data path 2 by system bus, wherein REG_FLASH_SIZE register is flash capacity sized registers, stores flash capacity information, by control information path 2, can pass to SRAM control module.
SRAM control module 3043: the inner read-write operation to SRAM of flash controller and the read-write operation of Memory Controller Hub to SRAM are converted into the signal needed for SRAM module.Read control information, storage allocation SRAM and flash memory SRAM size (flash capacity of configuration and bad block message) from configuration register and main control unit module respectively by control information path 2 and control information path 3 simultaneously.By control information path 4, read SRAM restructuring control information (i.e. maximum flash capacity) from main control unit module, complete SRAM restructuring.
Flash memory control module 3044: the outer flash memory of control strip, comprises and perform the data manipulation such as reading and writing, erasing, read ID, read states etc.But most of function is read operation in MCU system, and it is slow owing to directly reading flash chip speed, have a strong impact on the execution speed of CPU, therefore by flash memory control module by data in flash chip after system start-up, disposablely flash data is read, by data path 3, deposit in flash memory SRAM, system executive is the fetch program from flash memory SRAM all, because the reading speed of SRAM is fast, and the executive routine speed of so great quickening CPU.
Main control unit 3045: be responsible for the mode of operation controlling flash controller, each submodule co-ordination is made to complete function needed for each mode of operation, after system power-on reset, read flash capacity information from OTP module deposit register (OTP_FALSH_SIZE), this register stores the FALSH max cap. of this fixed product, and be transferred to flash memory SRAM control module by control information path 3, read SRAM shuffling information from OTP module simultaneously, pass to SRAM control module by control information path 4.
Wherein the function of each data path is as follows:
Data path 1: from the data reading port of flash memory SRAM, to the data reading port of Flash memory bus interface.
Data path 2: the data path between Flash memory bus interface and configuration register.
Data path 3: from the data reading port of flash memory control module, writes FPDP to SRAM control module.
Control information path 1: from OTP module read data to the path of main control unit.
Control information path 2: from configuration register to the control information path of SRAM control module.
Control information path 3: the control information path of SRAM comparator array module from main control unit to SRAM control module.
Control information path 4: the control information path of SRAM recomposition unit module from main control unit to SRAM control module.
As shown in Figure 6, the structural representation of Memory Controller Hub 305 in the embodiment of the present invention three is given.The read-write operation that rambus interface 3051 sends to internal memory for resolution system bus, internal memory SRAM interface 3052 translates into SRAM read-write operation for the read-write operation parsed by rambus interface.
As shown in Figure 7, give the structural representation of static RAM SRAM control module 3043 in the embodiment of the present invention three, sub-module is described below:
SRAM recomposition unit 3043-1:SRAM recomposition unit comprises the numbered register of each SRAM block, and the sequence number that each numbered register stores corresponding SRAM block (is defaulted as 0,1,2 ...).By main control unit by control information path 4, read in OTP about each SRAM block whether available information, disabled SRAM block is eliminated (being arranged to unavailable by the numbered register of this SRAM block), available SRAM is reorganized (numbered register corresponding by available SRAM block numbers in order again).Whether whether available information defines each SRAM block to SRAM can use in the application, defective SRAM block can be determined like this in volume production test, be defined as unavailable, bad when ensureing that even if chip has a small amount of SRAM block, these bad SRAM can be eliminated soon, and the SRAM block made good use of uses in application program, such chip also can continue to use on some product, and is unlikely to abandon.
SRAM comparator array 3043-2: obtained by SRAM recomposition unit, position (numbering of namely corresponding numbered register) residing for each SRAM block, by control information path 3 and control information path 2, obtain the SRAM amount of capacity required for flash memory, by comparison operation, can show that each SRAM block is for flash memory SRAM or internal memory SRAM.
SRAM selects array 3043-3: being exported as selecting signal by SRAM comparator array, selecting each SRAM block and belonging to flash memory SRAM or internal memory SRAM.The SRAM block belonging to flash memory SRAM, by data path 3, reads data and is written in this SRAM block from flash chip, and by data path 1, from then on SRAM block reads data to system bus.Belong to the SRAM block of internal memory SRAM, mutual with Memory Controller Hub, be used as Installed System Memory and use.
Below, be introduced with reference to Fig. 8 to the method for Resource dynamic allocation in the micro-control unit MCU in the embodiment of the present invention, show the process flow diagram of the method for Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention three, in the present invention, setting distributes SRAM space in units of block, each SRAM block comprises fixing SRAM size, and (defining variable is SRAM_BLOCK_SIZE, be such as 1024bytes), each SRAM block can not be accessed by flash controller and Memory Controller Hub simultaneously.Defining variable SRAM_SIZE is the SRAM block number that in chip, SRAM module is total.The method can comprise the following steps:
Step S401, read OTP: disposable after electrification reset will exist in OTP the main control unit read by control information path 1 about SRAM control information in flash controller.Comprising the block number SRAM_FAIL_SIZE and the flash capacity information OTP_FLASH_SIZE that determine defective SRAM in volume production test, OTP_FLASH_SIZE represents this SRAM largest block number shared by product flash memory, and this numerical value is less than the difference of SRAM_SIZE and SRAM_FAIL_SIZE.Wherein also comprise each SRAM block whether available information, indicate whether each SRAM block can be used in the application, in volume production test, defective SRAM block is arranged to unavailable, and does not have defective SRAM block to be arranged to available.Because OTP is disposable programmable storage unit, the SRAM control information that therefore one-off programming is good above in process of producing product, in this product use procedure, these information remain constant, and these OTP information are that the individual demand of each product determines.
Step S402, SRAM recombinate: whether SRAM recomposition unit reads each SRAM block by control information path 4 is available information, reorganizes the position residing for each SRAM.Each SRAM block and corresponding numbered register, reset each numbered register by SRAM recomposition unit.Be exemplified below: in default situations (all SRAM blocks are all available), the numbered register of each SRAM block is respectively: 0,1,2 ..., n ..., SRAM_SIZE-1.Wherein be numbered the data of SRAM block memory address scope between n × SRAM_BLOCK_SIZE to (n+1) × SRAM_BLOCK_SIZE-1 of n.Suppose the SRAM block defectiveness finding to be numbered 1 in volume production test, the SRAM block being numbered 1 is arranged to unavailable, after being recombinated by SRAM, the SRAM block of numbering 0 is constant, and numbered register corresponding to SRAM block being numbered 1 is arranged to unavailable, and the numbered register that each SRAM block from numbering 2 is corresponding all deducts 1, after computing, the numbered register of each SRAM block is respectively: 0, (unavailable), 1, ..., n-1 ..., SRAM_SIZE-2.
Step S403, distribution SRAM: after electrification reset, first time distributes SRAM, be that OTP_FLASH_SIZE information is passed to SRAM comparator array in flash memory SRAM controller by control information path 3, the SRAM block number distributed in SRAM shared by flash memory is OTP_FLASH_SIZE(OTP_FLASH_SIZE=SRAM_SIZE-SRAM_FAIL_SIZE-O TP_FLASH_SIZE).Compared with OTP_FLASH_SIZE by numbered register corresponding for each SRAM block, the SRAM block being less than OTP_FLASH_SIZE is assigned as flash memory SRAM, and the SRAM block being more than or equal to OTP_FLASH_SIZE is assigned as internal memory SRAM.
Step S404, needs copy: the first time that powers on needs to copy flash memory, otherwise does not need to copy flash memory.
Step S405, copy flash memory: the first time that powers on needs to copy flash memory, disposable by flash chip Program data etc. by flash memory control module, by data path 3, pass through SRAM controller, all copy in flash memory SRAM, the SRAM block number copied is OTP_FLASH_SIZE.
Step S406, read flash memory SRAM: after having copied, automatically read data in flash memory SRAM, by data path 1, read system bus.
Step S407, executive routine: by reading flash memory SRAM step, CPU obtains the routine data in flash memory SRAM, perform the program in flash memory SRAM.
Step S407, configuration REG_FLASH_SIZE register: by data path 2 in the application program of user, configuration REG_FLASH_SIZE register (this register is in configuration register module).SRAM block number shared by the flash memory that REG_FLASH_SIZE sets for user program, this value can not be greater than OTP_FLASH_SIZE, because OTP_FLASH_SIZE is the max cap. of current production flash memory; This value is greater than the actual flash capacity (user according to the actual size of present procedure, can know this numerical value) used of user program in addition.Configure REG_FLASH_SIZE register, jump to and distribute SRAM state, by the SRAM comparator array in SRAM controller, SRAM is redistributed according to REG_FLASH_SIZE, SRAM block number shared by flash memory is REG_FLASH_SIZE(REG_FLASH_SIZE=SRAM_SIZE-SRAM_FAIL_SIZE-R EG_FLASH_SIZE), after distributing, do not need to copy flash memory, continue to read flash memory SRAM, executive routine.
Step S409, read/write memory: in normal procedure implementation, mainly reading flash memory SRAM, executive routine, and redirect between read/write memory three states, some intermediate data or operation results etc. in CPU executive routine process, need stored in internal memory, or read from internal memory, then by system bus, by Memory Controller Hub, read/write memory SRAM completes.Now exercisable internal memory SRAM block number is the total block data of SRAM, deducts the block number that SRAM breaks down, then deducts user and configure SRAM block number shared by flash memory, can be expressed as (SRAM_SIZE-SRAM_FAIL_SIZE-REG_FLASH_SIZE).Therefore the memory size set in application program can not exceed this value.
According to the embodiment of the present invention, when total static RAM SRAM resource is fixing, flash memory and internal memory capacity is separately configured to MCU by application deployment, then according to flash capacity, the size of storage allocation and flash memory shared static RAM separately, thus can different product be adapted to, different client, demand under different application scene, avoid occurring the idle waste of flash capacity, and the situation that memory size is not enough, reach the most effectively utilizing of SRAM resource, and the usability of chip can be improved by the demand meeting internal memory.Meanwhile, adopt the embodiment of the present invention, the existence avoiding the flash memory SRAM of idle waste makes chip area bigger than normal than actual demand more, is beneficial to chip miniaturization.
And, according to the embodiment of the present invention, maximum flash capacity can also be configured in control information storer OTP, after chip electrification reset, namely according to configuration maximum flash capacity storage allocation and flash memory separately shared by the size of static RAM, thus no application scenarios and demand can be adapted to.
According to the embodiment of the present invention, defect may be produced for SRAM and cause the non-serviceable problem of SRAM, the present invention is equally by reasonably allocating SRAM resource, bad block is labeled as unavailable, available SRAM is reconfigured and renumbers, this chips still can be used on some product, and be unlikely to abandon.
Embodiment four:
With reference to Fig. 9, show the structured flowchart of the system of Resource dynamic allocation in a kind of micro-control unit MCU of the embodiment of the present invention four, described MCU50 comprises processor 501 and static RAM 502, and described static RAM 502 comprises multiple storage block;
Described MCU50 also comprises configuration deposit unit 503 and storage block allocation units 504:
Described configuration deposit unit 503, for receiving the default flash capacity that described processor configures when running application, described default flash capacity is less than the maximum flash capacity of described static RAM;
Described storage block allocation units 504, for distributing according to described default flash capacity in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory;
Described processor 501, for reading and performing the routine data in described flash memory storage block, carries out data interaction with described memory block simultaneously.
In the embodiment of the present invention, the storage block allocation units 504(be equivalent to described in the present embodiment of the static RAM SRAM control module 3043 in Fig. 5 comprises and compares subelement and chooser unit) and static RAM recomposition unit 507.
In the embodiment of the present invention, preferably, described MCU also comprises control information storer 505, and described control information storer 505 stores the bad block message of described static RAM;
Described MCU50 also comprises:
Main control unit 506, for after described MCU electrification reset, reads described bad block message from described control information storer;
Static RAM recomposition unit 507, for being labeled as unavailable by the bad block of described static RAM, and reorganizes the position of the storage block of non-bad block according to described bad block message.
In the embodiment of the present invention, preferably, described control information storer 505 also stores described maximum flash capacity information;
Described main control unit 506, also for according to after described MCU electrification reset, reads described maximum flash capacity information from described control information storer;
Described storage block allocation units 504, also for distributing the flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity information, after distributing, remaining storage block is the memory block for memory.
In the embodiment of the present invention, preferably, described system also comprises the flash chip 60 be connected with described MCU, and described MCU50 also comprises:
Flash memory control module 508, if power on for described MCU first time, then copies routine data in described flash chip to described static RAM for the flash memory storage block of flash memory storage.
In the embodiment of the present invention, preferably, described default flash capacity is the number of required storage block, and described storage block has respective numbering, and described storage block allocation units 504 comprise:
Relatively subelement 5041, for comparing the number of the numbering of each storage block and required storage block;
Chooser unit 5042, for described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory.
In the embodiment of the present invention, preferably, described MCU50 and described flash chip 60 separate and in outside physical connection, or described flash chip 60 is integrated in described MCU.
In the embodiment of the present invention, preferably, described MCU50 also comprises Flash memory bus interface 509 and system bus 510, and described configuration deposit unit 503 is communicated with described processor 501 with described system bus 510 by described Flash memory bus interface 509 with described storage block allocation units 504.
According to the embodiment of the present invention, when total static RAM SRAM resource is fixing, flash memory and internal memory capacity is separately configured to MCU by application deployment, then according to flash capacity, the size of storage allocation and flash memory shared static RAM separately, thus can different product be adapted to, different client, demand under different application scene, avoid occurring the idle waste of flash capacity, and the situation that memory size is not enough, reach the most effectively utilizing of SRAM resource, and the usability of chip can be improved by the demand meeting internal memory.Meanwhile, adopt the embodiment of the present invention, the existence avoiding the flash memory SRAM of idle waste makes chip area bigger than normal than actual demand more, is beneficial to chip miniaturization.
And, according to the embodiment of the present invention, maximum flash capacity can also be configured in control information storer OTP, after chip electrification reset, namely according to configuration maximum flash capacity storage allocation and flash memory separately shared by the size of static RAM, thus no application scenarios and demand can be adapted to.
According to the embodiment of the present invention, defect may be produced for SRAM and cause the non-serviceable problem of SRAM, the present invention is equally by reasonably allocating SRAM resource, bad block is labeled as unavailable, available SRAM is reconfigured and renumbers, this chips still can be used on some product, and be unlikely to abandon.
For system embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
The embodiment of the present invention can describe in the general context of computer executable instructions, such as program module.Usually, program module comprises the routine, program, object, assembly, data structure etc. that perform particular task or realize particular abstract data type.Also can put into practice the present invention in a distributed computing environment, in these distributed computing environment, be executed the task by the remote processing devices be connected by communication network.In a distributed computing environment, program module can be arranged in the local and remote computer-readable storage medium comprising memory device.
For aforesaid each embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not by the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in instructions all belongs to preferred embodiment, and involved action and module might not be that the present invention is necessary.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, commodity or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, commodity or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, commodity or the equipment comprising described key element and also there is other identical element.
Above to the method and system of Resource dynamic allocation in a kind of micro-control unit MCU provided by the present invention, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (14)
1. the method for Resource dynamic allocation in micro-control unit MCU, it is characterized in that, described MCU comprises processor and static RAM, and described static RAM comprises multiple storage block, and described method comprises:
Described MCU receives the default flash capacity that described processor configures when running application, and described default flash capacity is less than the maximum flash capacity of described static RAM;
Distribute in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory according to described default flash capacity;
Read and perform the routine data in described flash memory storage block, carrying out data interaction with described memory block simultaneously.
2. method according to claim 1, is characterized in that, described MCU also comprises control information storer, and described control information storer stores the bad block message of described static RAM;
Receive the step of the default flash capacity that described processor configures when running application at described MCU before, described method also comprises:
After described MCU electrification reset, described MCU reads described bad block message from described control information storer;
The bad block of described static RAM is labeled as unavailable, and reorganizes the position of the storage block of non-bad block according to described bad block message.
3. method according to claim 2, it is characterized in that, described control information storer also stores described maximum flash capacity information, and receive the step of the default flash capacity that described processor configures when running application at described MCU before, described method also comprises:
According to after described MCU electrification reset, described MCU reads described maximum flash capacity information from described control information storer;
Distribute the flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity information, after distributing, remaining storage block is the memory block for memory;
Read the routine data in described flash memory storage block, and run described routine data.
4. method according to claim 3, is characterized in that, described MCU is also connected with flash chip, and described method also comprises:
If described MCU first time powers on, then copy routine data in described flash chip to described static RAM for the flash memory storage block of flash memory storage.
5. method according to claim 1, it is characterized in that, described default flash capacity is the number of required storage block, described storage block has respective numbering, and described step of distributing the flash memory storage block for flash memory storage and the memory block for memory in static RAM according to default flash capacity comprises:
The number of the numbering of each storage block and required storage block is compared;
Described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory.
6. method according to claim 4, is characterized in that, described MCU and described flash chip separate and in outside physical connection, or described flash chip is integrated in described MCU.
7. method according to claim 1, it is characterized in that, described MCU also comprises Flash memory bus interface and system bus, and described MCU, by described Flash memory bus interface and described system bus, receives the default flash capacity that described processor configures when running application.
8. the system of Resource dynamic allocation in micro-control unit MCU, it is characterized in that, described MCU comprises processor and static RAM, and described static RAM comprises multiple storage block;
Described MCU also comprises configuration deposit unit and storage block allocation units:
Described configuration deposit unit, for receiving the default flash capacity that described processor configures when running application, described default flash capacity is less than the maximum flash capacity of described static RAM;
Described storage block allocation units, for distributing according to described default flash capacity in described static RAM for the flash memory storage block of flash memory storage and the memory block for memory;
Described processor, for reading and performing the routine data in described flash memory storage block, carries out data interaction with described memory block simultaneously.
9. system according to claim 8, is characterized in that, described MCU also comprises control information storer, and described control information storer stores the bad block message of described static RAM;
Described MCU also comprises:
Main control unit, for after described MCU electrification reset, reads described bad block message from described control information storer;
Static RAM recomposition unit, for being labeled as unavailable by the bad block of described static RAM, and reorganizes the position of the storage block of non-bad block according to described bad block message.
10. system according to claim 9, is characterized in that, described control information storer also stores described maximum flash capacity information;
Described main control unit, also for according to after described MCU electrification reset, reads described maximum flash capacity information from described control information storer;
Described storage block allocation units, also for distributing the flash memory storage block for flash memory storage in described static RAM according to described maximum flash capacity information, after distributing, remaining storage block is the memory block for memory.
11. systems according to claim 10, is characterized in that, also comprise the flash chip be connected with described MCU, described system also comprises:
Flash memory control module, if power on for described MCU first time, then copies routine data in described flash chip to described static RAM for the flash memory storage block of flash memory storage.
12. systems according to claim 8, is characterized in that, described default flash capacity is the number of required storage block, and described storage block has respective numbering, and described storage block allocation units comprise:
Relatively subelement, for comparing the number of the numbering of each storage block and required storage block;
Chooser unit, for described numbering is less than the number of required storage block as the flash memory storage block being used for flash memory storage, described numbering is more than or equal to the number of required storage block as the memory block being used for memory.
13. systems according to claim 11, is characterized in that, described MCU and described flash chip separate and in outside physical connection, or described flash chip is integrated in described MCU.
14. systems according to claim 8, it is characterized in that, described MCU also comprises Flash memory bus interface and system bus, and described configuration deposit unit and described storage block allocation units are by described Flash memory bus interface and described system bus and described processor communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310638362.9A CN104679592A (en) | 2013-12-02 | 2013-12-02 | Method and system for dynamically distributing resources in microcontroller unit MCU |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310638362.9A CN104679592A (en) | 2013-12-02 | 2013-12-02 | Method and system for dynamically distributing resources in microcontroller unit MCU |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104679592A true CN104679592A (en) | 2015-06-03 |
Family
ID=53314683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310638362.9A Pending CN104679592A (en) | 2013-12-02 | 2013-12-02 | Method and system for dynamically distributing resources in microcontroller unit MCU |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104679592A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933509A (en) * | 2017-02-17 | 2017-07-07 | 联想(北京)有限公司 | The processing method and electronic equipment of a kind of disk number |
| WO2019129193A1 (en) * | 2017-12-28 | 2019-07-04 | Silicon Motion Inc. | Memory card controller, memory card device, method used in memory card controller, and electronic device coupled to memory card device |
| CN110858147A (en) * | 2018-08-24 | 2020-03-03 | 深圳市优必选科技有限公司 | MCU information acquisition method and terminal equipment |
| US10671403B2 (en) | 2017-02-17 | 2020-06-02 | Lenovo (Beijing) Co., Ltd. | Method and apparatus for identifying hardware device in operating system |
| US10866746B2 (en) | 2017-12-28 | 2020-12-15 | Silicon Motion Inc. | Memory addressing methods and associated controller, memory device and host |
| CN112424752A (en) * | 2018-07-19 | 2021-02-26 | 纳木技术株式会社 | Volume (storage) supply method of application program container on cloud platform |
| CN112527506A (en) * | 2020-12-18 | 2021-03-19 | 北京百度网讯科技有限公司 | Device resource processing method and device, electronic device and storage medium |
| CN113741792A (en) * | 2020-05-29 | 2021-12-03 | 广州极飞科技股份有限公司 | Method for storing data by single chip microcomputer, single chip microcomputer and readable storage medium |
| CN114780153A (en) * | 2022-03-31 | 2022-07-22 | 深圳曦华科技有限公司 | Boot program starting method and related device |
| WO2023284177A1 (en) * | 2021-07-12 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor memory and capacity configuration method for storage block thereon |
| US12265469B2 (en) | 2023-10-16 | 2025-04-01 | Silicon Motion Inc. | Flash memory controller, SD card device, method used in flash memory controller, and host device coupled to SD card device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060274566A1 (en) * | 2005-06-02 | 2006-12-07 | Daisaburo Takashima | Memory system combining flash EEPROM and FeRAM |
| US20070040841A1 (en) * | 2005-08-22 | 2007-02-22 | Samsung Electronics Co., Ltd. | Display apparatus and control method thereof |
| CN200947355Y (en) * | 2006-08-03 | 2007-09-12 | 创惟科技股份有限公司 | Flash data cache |
| CN101201791A (en) * | 2007-08-28 | 2008-06-18 | 深圳市同洲电子股份有限公司 | Method and system for developing and debugging application program |
| CN101256501A (en) * | 2008-04-18 | 2008-09-03 | 四川长虹电器股份有限公司 | Software decompression starting method |
| CN102662913A (en) * | 2012-03-29 | 2012-09-12 | 佛山华芯微特科技有限公司 | Method and MCU (microcontroller unit) chip for improving storage performance of MCU |
| CN103186471A (en) * | 2011-12-30 | 2013-07-03 | 深圳市共进电子股份有限公司 | Method and system for managing bad blocks in storage equipment |
-
2013
- 2013-12-02 CN CN201310638362.9A patent/CN104679592A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060274566A1 (en) * | 2005-06-02 | 2006-12-07 | Daisaburo Takashima | Memory system combining flash EEPROM and FeRAM |
| US20070040841A1 (en) * | 2005-08-22 | 2007-02-22 | Samsung Electronics Co., Ltd. | Display apparatus and control method thereof |
| CN200947355Y (en) * | 2006-08-03 | 2007-09-12 | 创惟科技股份有限公司 | Flash data cache |
| CN101201791A (en) * | 2007-08-28 | 2008-06-18 | 深圳市同洲电子股份有限公司 | Method and system for developing and debugging application program |
| CN101256501A (en) * | 2008-04-18 | 2008-09-03 | 四川长虹电器股份有限公司 | Software decompression starting method |
| CN103186471A (en) * | 2011-12-30 | 2013-07-03 | 深圳市共进电子股份有限公司 | Method and system for managing bad blocks in storage equipment |
| CN102662913A (en) * | 2012-03-29 | 2012-09-12 | 佛山华芯微特科技有限公司 | Method and MCU (microcontroller unit) chip for improving storage performance of MCU |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10671403B2 (en) | 2017-02-17 | 2020-06-02 | Lenovo (Beijing) Co., Ltd. | Method and apparatus for identifying hardware device in operating system |
| CN106933509A (en) * | 2017-02-17 | 2017-07-07 | 联想(北京)有限公司 | The processing method and electronic equipment of a kind of disk number |
| CN106933509B (en) * | 2017-02-17 | 2019-09-24 | 联想(北京)有限公司 | A kind of processing method and electronic equipment of disk number |
| US12061801B2 (en) | 2017-12-28 | 2024-08-13 | Silicon Motion Inc. | Memory addressing methods and associated controller, memory device and host |
| US10691589B2 (en) | 2017-12-28 | 2020-06-23 | Silicon Motion Inc. | Flash memory controller, SD card device, method used in flash memory controller, and host device coupled to SD card device |
| US10853239B2 (en) | 2017-12-28 | 2020-12-01 | Silicon Motion Inc. | Memory card controller, memory card device, method used in memory card controller, and electronic device coupled to memory card device |
| US10866746B2 (en) | 2017-12-28 | 2020-12-15 | Silicon Motion Inc. | Memory addressing methods and associated controller, memory device and host |
| US11829289B2 (en) | 2017-12-28 | 2023-11-28 | Silicon Motion Inc. | Flash memory controller, SD card device, method used in flash memory controller, and host device coupled to SD card device |
| WO2019129193A1 (en) * | 2017-12-28 | 2019-07-04 | Silicon Motion Inc. | Memory card controller, memory card device, method used in memory card controller, and electronic device coupled to memory card device |
| US11249893B2 (en) | 2017-12-28 | 2022-02-15 | Silicon Motion Inc. | Flash memory controller, SD card device, method used in flash memory controller, and host device coupled to SD card device |
| US11422717B2 (en) | 2017-12-28 | 2022-08-23 | Silicon Motion Inc. | Memory addressing methods and associated controller, memory device and host |
| CN112424752A (en) * | 2018-07-19 | 2021-02-26 | 纳木技术株式会社 | Volume (storage) supply method of application program container on cloud platform |
| CN110858147A (en) * | 2018-08-24 | 2020-03-03 | 深圳市优必选科技有限公司 | MCU information acquisition method and terminal equipment |
| CN110858147B (en) * | 2018-08-24 | 2023-12-29 | 深圳市优必选科技有限公司 | MCU information acquisition method and terminal equipment |
| CN113741792A (en) * | 2020-05-29 | 2021-12-03 | 广州极飞科技股份有限公司 | Method for storing data by single chip microcomputer, single chip microcomputer and readable storage medium |
| CN113741792B (en) * | 2020-05-29 | 2023-09-01 | 广州极飞科技股份有限公司 | Method for storing data by singlechip, singlechip and readable storage medium |
| CN112527506A (en) * | 2020-12-18 | 2021-03-19 | 北京百度网讯科技有限公司 | Device resource processing method and device, electronic device and storage medium |
| US11875045B2 (en) | 2021-07-02 | 2024-01-16 | Changxin Memory Technologies, Inc. | Semiconductor memory and method for density configuring of bank of semiconductor memory |
| WO2023284177A1 (en) * | 2021-07-12 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor memory and capacity configuration method for storage block thereon |
| CN114780153B (en) * | 2022-03-31 | 2023-08-08 | 深圳曦华科技有限公司 | Boot program starting method and related device |
| CN114780153A (en) * | 2022-03-31 | 2022-07-22 | 深圳曦华科技有限公司 | Boot program starting method and related device |
| US12265469B2 (en) | 2023-10-16 | 2025-04-01 | Silicon Motion Inc. | Flash memory controller, SD card device, method used in flash memory controller, and host device coupled to SD card device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104679592A (en) | Method and system for dynamically distributing resources in microcontroller unit MCU | |
| US11221961B1 (en) | Configuration of nonvolatile memory as virtual devices with user defined parameters | |
| US11836380B2 (en) | NVMe direct virtualization with configurable storage | |
| US9990139B2 (en) | Scalable and area optimized method to implement command queues in SRIOV based NVM devices | |
| CN105103144A (en) | Apparatuses and methods for adaptive control of memory | |
| JP2007128511A (en) | Method and device for automatically evaluating and allocating resource in cell based system | |
| US12013802B2 (en) | Method and apparatus for embedded processor to perform fast data communication, and storage medium | |
| US11899970B2 (en) | Storage system and method to perform workload associated with a host | |
| CN105760310B (en) | address distribution method and DDR controller | |
| US20230288471A1 (en) | Virtualizing Hardware Processing Resources in a Processor | |
| US20230289212A1 (en) | Flexible Migration of Executing Software Between Processing Components Without Need For Hardware Reset | |
| CN1323362C (en) | Network equipment and method for distributing its peripheral device interconnection resources | |
| US9503096B1 (en) | Multiple-layer configuration storage for runtime reconfigurable systems | |
| US20170344504A1 (en) | Method for accessing a number of slave devices with registers by a master device over a network | |
| CN103678151A (en) | Configuration method and configuration device of block storage device of virtual machine | |
| CN109542840B (en) | SoC system | |
| CN116954815A (en) | Resource scheduling method and device, computer equipment and computer readable storage medium | |
| US11663043B2 (en) | High bandwidth memory system with dynamically programmable distribution scheme | |
| CN116048377A (en) | Data processing method of solid state disk and related equipment | |
| CN115280272A (en) | Data access circuit and method | |
| US9853644B2 (en) | Multiple-layer configuration storage for runtime reconfigurable systems | |
| US11989420B2 (en) | Memory allocation method and apparatus, electronic device, and storage medium | |
| WO2012127534A1 (en) | Barrier synchronization method, barrier synchronization device and processing device | |
| CN117149447B (en) | Bandwidth adjustment method, device, equipment and storage medium | |
| US20060085620A1 (en) | Address aligned resource set allocation in a memory space |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150603 |
|
| RJ01 | Rejection of invention patent application after publication |