CN104656733B - Self-adaptation exports the low pressure difference linear voltage regulator of ultra low quiescent current - Google Patents

Abstract

The invention relates to a large-scale integrated circuit and aims to provide an LDO with self-adaptive output ultra-low quiescent current. The LDO circuit can maintain high stability under a wide range of load conditions, especially under no-load conditions, and has the characteristics of ultra-low quiescent current and fast response. For this reason, the technical scheme that the present invention takes is, the low-dropout linear regulator of self-adaptive output ultra-low quiescent current, by two gain amplifying stages, two CMOS power transistor loops, a feedback loop, reduce overshoot loop and Composed of a frequency compensation loop; the input signal is input from the inverting input terminal of the first gain amplifier stage and then output through the second amplifier stage and the first CMOS power transistor loop; the output of the first gain amplifier stage also passes through the second CMOS power transistor The loop is directly output to the loop output end of the first CMOS power transistor. The invention is mainly applied to the design and manufacture of large-scale integrated circuits.

Description

Low dropout linear regulator with adaptive output ultra-low quiescent current

technical field

The invention relates to a large-scale integrated circuit, a low-voltage low-power consumption circuit, and a low-dropout linear regulator (LDO). Specifically, it relates to a low-dropout linear voltage regulator with adaptive output ultra-low quiescent current.

Background technique

Modern high-speed development of power management units requires many voltage modulators to supply power to each functional module. For high-performance, high-sensitivity digital-analog or mixed-signal modules, a low-dropout linear regulator (LDO) is an ideal choice. However, it is not easy for the LDO to maintain stability when driving a load capacitance of hundreds of pf. The research on LDO without output capacitor (OCL-LDO) is a very popular direction, because it can reduce the influence of the parasitic capacitance between the connections of hundreds of I/Opads on the chip on the inside of the chip.

Also for portable units such as cell phone batteries, low quiescent supply current is critical because it prolongs battery life. The LDO without output capacitor can compromise the static power consumption of the battery and the loop stability and transient response of the LDO.

Contents of the invention

In order to overcome the deficiencies of the prior art, an LDO with self-adaptive output ultra-low quiescent current is provided. The LDO circuit can maintain high stability under a wide range of load conditions, especially under no-load conditions, and has the characteristics of ultra-low quiescent current and fast response. The technical scheme adopted by the present invention is: a low-dropout linear voltage regulator with adaptive output ultra-low quiescent current, which consists of two gain amplification stages, two CMOS power transistor loops, a feedback loop, an overshoot-reducing loop, and a frequency compensation Loop composition; the input signal is input from the inverting input terminal of the first gain amplifier stage and then output through the second amplifier stage and the first CMOS power transistor loop; the output of the first gain amplifier stage is also directly output through the second CMOS power transistor loop To the output end of the first CMOS power transistor loop; the feedback loop is connected between the non-inverting input end of the first gain amplification stage and the output end of the first CMOS power transistor loop; the frequency compensation loop is connected to the output end of the first gain amplification stage, the second Between the output terminals of a CMOS power transistor circuit; the overshoot reduction circuit is connected to the output terminal of the first CMOS power transistor circuit;

The specific structure of the LDO is: the first to fourteenth PMOS transistors M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 and the first to sixteenth NMOS transistors M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322, a total of 30 MOS transistors, four capacitors are compensation capacitors Ca, Cm, Cz , CL and five resistors, that is, resistors R1, R2, Rm, Rz, RL are jointly formed; where:

The sources of the first to fourteenth PMOS transistors M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, and MP2 are commonly connected to the power supply VDD; except for the second to third In addition to the PMOS transistors M11 and M12, the substrates of the first, fourth to fourteenth PMOS transistors M10, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1 and MP2 are connected to the power supply VDD; The sources of the first to eighth, eleventh to fourteenth, and sixteenth NMOS transistors M13, M14, M132, M133, M17, M18, M171, M181, M24, M25, M28, M31, and M322 are commonly grounded to GND ; The substrate terminals of the first to sixteenth NMOS transistors M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, and M322 are grounded to GND;

The gate of the first PMOS transistor M10 is connected to the first bias voltage Vb1, the drain is connected to the source and substrate of the second to third PMOS transistors M11, M12 and the drain of the fourth PMOS transistor M15; the first PMOS transistor M10 1. The gates of the sixth PMOS transistor M101 are commonly connected to the first bias voltage Vb1; the gates of the second to third PMOS transistors M11 and M12 are respectively connected to the common-mode input voltage Vcm and the reference reference voltage Vref; the second PMOS transistor M11 , the drains of the first and fifth NMOS transistors M13 and M17, and the gate of the seventh NMOS transistor M171 are jointly connected to the source of the ninth NMOS transistor M19; the third PMOS transistor M12, the second NMOS transistor M14, and the sixth NMOS transistor The drain of M18, the gate of the eighth NMOS transistor M181, and the left end of the first capacitor Ca are jointly connected to the source of the tenth NMOS transistor M20;

The drain of the seventh NMOS transistor M171 and the gate of the ninth NMOS transistor M19 are connected to the lower end of the first resistor R1; the drain of the eighth NMOS transistor M181 and the gate of the tenth NMOS transistor M20 are connected to the bottom of the second resistor R2 The lower end; the upper ends of the first to second resistors R1, R2 are commonly connected to the drain of the sixth PMOS transistor M101; the gates of the seventh to eighth PMOS transistors M21, M22, and the drain of the seventh PMOS transistor M21 are commonly connected to the ninth The drain of the NMOS transistor M19; the gates of the ninth to tenth PMOS transistors M131, M23, and the thirteenth PMOS transistor MP1 are jointly connected to the drains of the tenth NMOS transistor M20 and the eighth PMOS transistor M22; the first to fourth NMOS The gates of the transistors M13, M14, M132, and M133 are commonly connected to the drains of the ninth PMOS transistor M131 and the third NMOS transistor M132; the gates of the fifth to sixth and thirteenth NMOS transistors M17, M18, M28, The left end of the resistor Rm is commonly connected to the second bias voltage Vb2;

The gates of the eleventh to twelfth NMOS transistors M24 and M25 are jointly connected to the drains of the eleventh NMOS transistor M24 and the tenth PMOS transistor M23; the drains of the twelfth NMOS transistor M25 and the eleventh PMOS transistor M26, The upper end of the second capacitor Cm is commonly connected to the gate of the fourteenth PMOS transistor MP2; the gates of the eleventh to twelfth PMOS transistors M26, M27 are commonly connected to the drains of the twelfth PMOS transistor M27 and the thirteenth NMOS transistor M28 pole; the drain of the thirteenth PMOS transistor MP1, the upper end of the fourth resistor Rz, the drain of the fourteenth NMOS transistor M31, the upper end of the load capacitor CL, and the upper end of the load resistor RL are jointly connected to the output terminal VOUT; the third capacitor Cz The upper end of the fourth resistor Rz is connected to the lower end and the lower end is grounded; the gate of the fourteenth NMOS transistor M31 and the lower end of the second capacitor Cm are jointly connected to the right end of the third resistor Rm; the gate and drain of the fifteenth NMOS transistor M321 Commonly connected to the drain of the fourteenth PMOS transistor MP2; the gate and drain of the sixteenth NMOS transistor M322, and the source of the fifteenth NMOS transistor M321 are commonly connected to the common-mode feedback voltage Vcm.

Compared with prior art, technical characteristic and effect of the present invention:

Under low voltage and low power consumption (μW) conditions, this ultra-low quiescent current LDO can drive a wide range of load capacitance (hundreds of pF), while having low quiescent current and faster response speed.

Description of drawings

Figure 1 Topology of LDO with ultra-low quiescent current

Figure 2 Schematic diagram of the implementation of an ultra-low quiescent current LDO

detailed description

Most of the research on OCL-LDO in recent years has the direction of low quiescent current and fast response. The present invention can provide an OCL-LDO with ultra-low quiescent current, fast response and requiring very small load current. The LDO uses adaptive power transistor technology. When driving a large load current, this OCL-LDO can realize the conversion from two-level structure to three-level structure. It is also highly stable over a wide range of load conditions, especially at no load, with ultra-low quiescent current.

The invention proposes an LDO with self-adaptive output ultra-low quiescent current. The LDO is composed of two gain amplification stages, two CMOS power transistor loops, a feedback loop, an overshoot reduction loop and a frequency compensation loop. The two gain amplification stages are: a transconductance gain input stage Av1, and a second high gain stage Av2. The two CMOS power transistor loops are: transconductance gain stage MP1 and transconductance gain stage MP2.

The specific implementation circuit schematic diagram is as follows:

The two gain amplification stages are respectively the first gain amplification stage (including the first to second, sixth, seventh to eighth PMOS transistors M11, M12, M101, M21 and M22, the fifth to tenth NMOS transistors M17, M18 , M171, M181, M19 and M20, first to second resistors R1, R2.); second gain amplification stage (including tenth to twelfth PMOS transistors M23, M26 and M27, tenth to thirteenth NMOS transistors M24, M25 and M28.). The two CMOS power transistor loops are: the first CMOS power transistor loop (including the thirteenth PMOS transistor MP1 ); the second CMOS power transistor loop (including the fourteenth PMOS transistor MP2 ). The feedback loop includes: fifteenth to sixteenth NMOS transistors M321, M322, and a second PMOS transistor M12. The frequency compensation circuit includes: a tenth NMOS transistor M20, first and third capacitors Ca, Cz and a fourth resistor Rz. The overshoot reducing loop includes: a fourteenth NMOS transistor M31, a second capacitor Cm and a third resistor Rm.

The LDO consists of the first to fourteenth PMOS transistors M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 and the first to sixteenth NMOS transistors M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322, a total of 30 MOS transistors, four capacitors are compensation capacitors Ca, Cm, Cz, CL and five A resistor is composed of resistors R1, R2, Rm, Rz, and RL; where:

The sources of the first to fourteenth PMOS transistors M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, and MP2 are commonly connected to the power supply VDD; except for the second to third In addition to the PMOS transistors M11 and M12, the substrates of the first, fourth to fourteenth PMOS transistors M10, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1 and MP2 are connected to the power supply VDD; The sources of the first to eighth, eleventh to fourteenth, and sixteenth NMOS transistors M13, M14, M132, M133, M17, M18, M171, M181, M24, M25, M28, M31, and M322 are commonly grounded to GND The substrate terminals of the first to sixteenth NMOS transistors M13 , M14 , M132 , M133 , M17 , M18 , M171 , M181 , M19 , M20 , M24 , M25 , M28 , M31 , M321 , M322 are grounded to GND.

The gate of the first PMOS transistor M10 is connected to the first bias voltage Vb1, the drain is connected to the source and substrate of the second to third PMOS transistors M11, M12 and the drain of the fourth PMOS transistor M15; the first PMOS transistor M10 1. The gates of the sixth PMOS transistor M101 are commonly connected to the first bias voltage Vb1; the gates of the second to third PMOS transistors M11 and M12 are respectively connected to the common-mode input voltage Vcm and the reference reference voltage Vref; the second PMOS transistor M11 , the drains of the first and fifth NMOS transistors M13 and M17, and the gate of the seventh NMOS transistor M171 are jointly connected to the source of the ninth NMOS transistor M19; the third PMOS transistor M12, the second NMOS transistor M14, and the sixth NMOS transistor The drain of M18, the gate of the eighth NMOS transistor M181, and the left end of the first capacitor Ca are jointly connected to the source of the tenth NMOS transistor M20.

The drain of the seventh NMOS transistor M171 and the gate of the ninth NMOS transistor M19 are connected to the lower end of the first resistor R1; the drain of the eighth NMOS transistor M181 and the gate of the tenth NMOS transistor M20 are connected to the bottom of the second resistor R2 The lower end; the upper ends of the first to second resistors R1, R2 are commonly connected to the drain of the sixth PMOS transistor M101; the gates of the seventh to eighth PMOS transistors M21, M22, and the drain of the seventh PMOS transistor M21 are commonly connected to the ninth The drain of the NMOS transistor M19; the gates of the ninth to tenth PMOS transistors M131, M23, and the thirteenth PMOS transistor MP1 are jointly connected to the drains of the tenth NMOS transistor M20 and the eighth PMOS transistor M22; the first to fourth NMOS The gates of the transistors M13, M14, M132, and M133 are commonly connected to the drains of the ninth PMOS transistor M131 and the third NMOS transistor M132; the gates of the fifth to sixth and thirteenth NMOS transistors M17, M18, M28, The left ends of the resistors Rm are commonly connected to the second bias voltage Vb2.

The gates of the eleventh to twelfth NMOS transistors M24 and M25 are jointly connected to the drains of the eleventh NMOS transistor M24 and the tenth PMOS transistor M23; the drains of the twelfth NMOS transistor M25 and the eleventh PMOS transistor M26, The upper end of the second capacitor Cm is commonly connected to the gate of the fourteenth PMOS transistor MP2; the gates of the eleventh to twelfth PMOS transistors M26, M27 are commonly connected to the drains of the twelfth PMOS transistor M27 and the thirteenth NMOS transistor M28 pole; the drain of the thirteenth PMOS transistor MP1, the upper end of the fourth resistor Rz, the drain of the fourteenth NMOS transistor M31, the upper end of the load capacitor CL, and the upper end of the load resistor RL are jointly connected to the output terminal VOUT; the third capacitor Cz The upper end of the fourth resistor Rz is connected to the lower end and the lower end is grounded; the gate of the fourteenth NMOS transistor M31 and the lower end of the second capacitor Cm are jointly connected to the right end of the third resistor Rm; the gate and drain of the fifteenth NMOS transistor M321 Commonly connected to the drain of the fourteenth PMOS transistor MP2; the gate and drain of the sixteenth NMOS transistor M322, and the source of the fifteenth NMOS transistor M321 are commonly connected to the common-mode feedback voltage Vcm.

The third PMOS transistor M12 is selected as the reference voltage input terminal, and the second PMOS transistor M11 is selected as the common-mode feedback input terminal. Then the signal passes through the first dynamic bias input stage, to the second adaptive gain stage, the third power transistor amplification stage, and the fourth reduction overshoot stage; at the same time, the signal reaches the output terminal through two other paths: one is the frequency compensation stage, All the way is the feedback stage; so far the signal has completed the feedback comparison and amplification in the loop. Loading a resistor and a large load capacitor at the output of the LDO can test the small-signal AC response and the large-signal step response of the LDO. The results show that this ultra-low quiescent current LDO can drive large load capacitance (tens of pF), while having high linearity and faster response speed.

Claims (1)

1. self-adaptation exports a low pressure difference linear voltage regulator for ultra low quiescent current, it is characterized in that, is made up of two gain amplification stage, two CMOS power crystal tube loops, backfeed loop, reduction overshoot loop and frequency compensation loops; Input signal exports through the second amplifier stage, a CMOS power crystal tube loop after being inputted by the inverting input of the first gain amplification stage successively; The output of the first gain amplification stage also directly outputs to a CMOS power transistor loop output by the 2nd CMOS power crystal tube loop; Backfeed loop is connected between the in-phase input end of the first gain amplification stage, a CMOS power transistor loop output; Frequency compensation loop is connected between the output terminal of the first gain amplification stage, a CMOS power transistor loop output; Reduce overshoot loop and be connected to a CMOS power transistor loop output;

Described LDO concrete structure is: by the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 and first is to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322 is totally 30 MOS transistor, four electric capacity and building-out capacitor Ca, Cm, Cz, CL and five resistance and resistance R1, R2, Rm, Rz, RL is formed jointly, wherein:

The source electrode of the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 meets power supply VDD jointly; Except the second to the 3rd PMOS transistor M11, M12, the substrate termination power supply VDD of the first, the 4th to the 14 PMOS transistor M10, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2; First to the 8th, the 11 to the 14, the source electrode common ground GND of the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M24, M25, M28, M31, M322; The substrate terminal ground connection GND of first to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322;

The grid of the first PMOS transistor M10 meets the first bias voltage Vb1, drain electrode connects the second to the 3rd PMOS transistor M11, the source electrode of M12 and the drain electrode of substrate and the 4th PMOS transistor M15; The grid of the first PMOS transistor M10, the 6th PMOS transistor M101 meets the first bias voltage Vb1 jointly; The grid of the second to the 3rd PMOS transistor M11, M12 meets input common mode voltage Vcm and reference data voltage Vref respectively and holds; Second PMOS transistor M11, first, the drain electrode of the 5th nmos pass transistor M13, M17, the grid of the 7th nmos pass transistor M171 connect the source electrode of the 9th nmos pass transistor M19 jointly; The left end of the drain electrode of the 3rd PMOS transistor M12, the second nmos pass transistor M14, the 6th nmos pass transistor M18, the grid of the 8th nmos pass transistor M181, the first electric capacity Ca connects the source electrode of the tenth nmos pass transistor M20 jointly;

The drain electrode of the 7th nmos pass transistor M171, the grid of the 9th nmos pass transistor M19 connect the lower end of the first resistance R1 jointly; The drain electrode of the 8th nmos pass transistor M181, the grid of the tenth nmos pass transistor M20 connect the lower end of the second resistance R2 jointly; The upper end of the first to the second resistance R1, R2 connects the drain electrode of the 6th PMOS transistor M101 jointly; The grid of the 7th to the 8th PMOS transistor M21, M22, the drain electrode of the 7th PMOS transistor M21 connect the drain electrode of the 9th nmos pass transistor M19 jointly; The grid of the 9th to the tenth PMOS transistor M131, M23, the 13 PMOS transistor MP1 connects the drain electrode of the tenth nmos pass transistor M20, the 8th PMOS transistor M22 jointly; The grid of first to fourth nmos pass transistor M13, M14, M132, M133 connects the drain electrode of the 9th PMOS transistor M131, the 3rd nmos pass transistor M132 jointly; 5th to the 6th, the grid of the 13 nmos pass transistor M17, M18, M28, the left end of the 3rd resistance Rm meet the second bias voltage Vb2 jointly;

The grid of the 11 to the tenth bi-NMOS transistor M24, M25 connects the drain electrode of the 11 nmos pass transistor M24, the tenth PMOS transistor M23 jointly; The drain electrode of the tenth bi-NMOS transistor M25, the 11 PMOS transistor M26, the upper end of the second electric capacity Cm connect the grid of the 14 PMOS transistor MP2 jointly; The grid of the 11 to the 12 PMOS transistor M26, M27 connects the drain electrode of the 12 PMOS transistor M27, the 13 nmos pass transistor M28 jointly; The drain electrode of the 13 PMOS transistor MP1, the upper end of the 4th resistance Rz, the drain electrode of the 14 nmos pass transistor M31, the upper end of load capacitance CL, the upper end of pull-up resistor RL meet output terminal VOUT jointly; The lower end of upper termination the 4th resistance Rz of the 3rd electric capacity Cz, lower end ground connection; The grid of the 14 nmos pass transistor M31, the lower end of the second electric capacity Cm connect the right-hand member of the 3rd resistance Rm jointly; The grid of the 15 nmos pass transistor M321 and drain electrode connect the drain electrode of the 14 PMOS transistor MP2 jointly; The source electrode of the grid of the 16 nmos pass transistor M322 and drain electrode, the 15 nmos pass transistor M321 meets common mode feedback voltage Vcm jointly.