CN104638005B - Lateral double-diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents

Abstract

A lateral double diffused metal oxide semiconductor device and a manufacturing method thereof, comprising: a semiconductor substrate; an epitaxial semiconductor layer formed on the semiconductor substrate; a gate structure disposed on the epitaxial semiconductor layer; a first doped region disposed in the epitaxial semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the epitaxial semiconductor layer on a second side relative to the first side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a groove formed in the third doped region, the first doped region and the epitaxial semiconductor layer below the first doped region; a conductive contact located in the groove; and a fifth doped region disposed in the epitaxial semiconductor layer below the first doped region. The present invention can reduce the manufacturing cost and component size of the lateral double diffused metal oxide semiconductor device.

Description

Lateral double diffused metal oxide semiconductor device and manufacturing method thereof

technical field

The present invention relates to an integrated circuit device, and in particular to a lateral double diffused metal oxide semiconductor device and a manufacturing method thereof.

Background technique

In recent years, due to the rapid development of communication devices such as mobile communication devices and personal communication devices, wireless communication products such as mobile phones and base stations have shown substantial growth. In wireless communication products, high voltage components of lateral double diffused metal oxide semiconductor (LDMOS) devices are often used as components related to radio frequency (900MHz-2.4GHz) circuits.

The lateral double-diffused metal oxide semiconductor device not only has a high operating bandwidth, but also has high output power because it can withstand a high breakdown voltage, so it is suitable for use as a power amplifier of wireless communication products. In addition, because the lateral double-diffused metal oxide semiconductor (LDMOS) device can be formed by using the traditional complementary metal oxide semiconductor (CMOS) process technology, its manufacturing technology is relatively mature and can be made by using a relatively cheap silicon substrate.

Please refer to FIG. 1 , which shows a schematic cross-sectional view of a conventional N-type lateral double-diffused metal-oxide-semiconductor (N-type LDMOS) device applicable to radio frequency circuit components. As shown in Figure 1, the N-type lateral double-diffused metal oxide semiconductor device mainly includes a P+ type semiconductor substrate 100, a P-type epitaxial semiconductor layer 102 formed on the P+ type semiconductor substrate 100, and a P-type epitaxial semiconductor layer formed on the P-type semiconductor substrate 100. A gate structure G on a portion of layer 102 . A P-type doped region 104 is provided in a part of the P-type epitaxial semiconductor layer 102 below the gate structure G and on the left side, and adjacent to the P-type doped region 104 on the right side of the gate structure G. A part of the P- epitaxial semiconductor layer 102 in the impurity region 104 is provided with an N-type drift region (driftregion) 106 . A P+ type doping region 130 and an N+ type doping region 110 are arranged in a part of the P type doping region 104, and the P+ type doping region 130 partially contacts a part of the N+ type doping region 110, as A contact region (P+ type doped region 130) and a source (N+ type doped region 110) of this N-type lateral double-diffused metal oxide semiconductor device are used, and the P on the right side of the adjacent N-type drift region 106 -Another N+ type doped region 108 is disposed in a part of the epitaxial semiconductor layer 102 to serve as a drain of the N-type lateral double-diffused metal oxide semiconductor device. In addition, an insulating layer 112 is formed on the gate structure G, which covers the sidewall and top surface of the gate structure G, and partially covers the N+ type doped regions 108 and 110 adjacent to the gate structure G. Moreover, the N-type lateral double-diffused metal oxide semiconductor device is also provided with a P+ type doped region 120, which is generally located in the N+ type doped region 110 and the P-type epitaxial semiconductor below a part of the P-type doped region 104. In the region 102 , the P+ type doped region 120 physically connects the P− type doped region 104 and the P+ semiconductor substrate 100 .

Based on the formation of the P+ doped region 120, a current (not shown) can flow laterally from its drain terminal (N+ doped region 108) when the N-type lateral double-diffused MOS device shown in FIG. 1 is in operation. It flows through the channel (not shown) under the gate structure G and flows toward the source terminal (N+ doped region 110 ), and then reaches the P+ type semiconductor substrate guided by the P− type doped region 104 and the P+ doped region 120 At 100 , undesired problems such as inductor coupling and cross talk between adjacent circuit elements can be avoided. However, the formation of the P+ doped region 120 requires the implementation of high-concentration, high-dose ion distribution (not shown) and a higher temperature thermal diffusion process such as higher than 900° C., and the gate structure G and A predetermined distance D1 must be maintained between the left sides of the N+ doped region 110 to ensure the performance of the N-type lateral double-diffused MOS device. In this way, the manufacturing of the above-mentioned P+ type doped region 120 and the predetermined distance D1 maintained between the gate structure G and the N+ doped region 110 will relatively increase the on-resistance ( Ron) and the device size of the N-type lateral double-diffused MOS device, which is not conducive to the further reduction of the manufacturing cost and device size of the N-type lateral double-diffused metal-oxygen semiconductor device.

Contents of the invention

The technical problem to be solved by the present invention is to provide a lateral double-diffused metal oxide semiconductor device and its manufacturing method, so as to solve the problems of manufacturing cost and element size of the power amplifier in the prior art. .

The solution of the present invention to solve the above technical problems includes: providing a lateral double-diffused metal oxide semiconductor device, comprising: a semiconductor substrate having a first conductivity type; an epitaxial semiconductor layer formed on the semiconductor substrate and having the first conductivity type A conductivity type; a gate structure disposed on a part of the epitaxial semiconductor layer; a first doped region disposed in a part of the epitaxial semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type; a second doped region, disposed in a part of the epitaxial semiconductor layer on a second side opposite to the first side of the gate structure, having a second conductivity type opposite to the first conductivity type conductivity type; a third doped region, disposed in a part of the first doped region, having the second conductivity type; a fourth doped region, disposed in a part of the second doped region, having the second conductivity type; a groove formed in the third doped region, the first doped region and a part of the epitaxial semiconductor layer below the first doped region; a conductive contact located in the groove and a fifth doped region, disposed in a part of the epitaxial semiconductor layer below the first doped region, having the first conductivity type, the fifth doped region physically contacts the semiconductor substrate and surrounds the semiconductor substrate Part of the sidewall and bottom surface of the conductive contact.

The invention provides a method for manufacturing a lateral double-diffused metal oxide semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming an epitaxial semiconductor layer on the semiconductor substrate having the first conductivity type; forming a gate structure on a part of the epitaxial semiconductor layer; forming a first doped region in a part of the epitaxial semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type; forming a The second doped region has a second conductivity type opposite to the first conductivity type in a portion of the epitaxial semiconductor layer on a second side opposite to the first side of the gate structure; forming a third doped region The impurity region has the second conductivity type in a part of the first doped region; a fourth doped region is formed in a part of the second doped region and has the second conductivity type; an insulating layer is formed in the The second doped region and the gate structure and on a part of the third doped region; forming a trench in the third doped region adjacent to the insulating layer, the first doped region In a part of the epitaxial semiconductor layer below; perform an ion distribution process, and distribute the dopant of the first conductivity type in the epitaxial semiconductor layer exposed by the trench to form a fifth doping region, wherein the fifth doped region physically contacts the semiconductor substrate; and forms a conductive contact in the trench, wherein the conductive contact layer physically contacts the fifth doped region.

The present invention also provides a method for manufacturing a lateral double-diffused metal oxide semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a first epitaxial semiconductor layer on the semiconductor substrate having the first conductivity type type; forming a first trench in a part of the first epitaxial semiconductor layer; performing an ion distribution process, distributing dopants of the first conductivity type in the first exposed by the first trench In the epitaxial semiconductor layer, to form a first doped region, wherein the first doped region physically contacts the semiconductor substrate; to form a second epitaxial semiconductor layer in the first trench; to form a gate structure in the On a portion of the epitaxial semiconductor layer adjacent to the second epitaxial semiconductor layer; forming a second doped region in a portion of the first epitaxial semiconductor layer adjacent to a first side of the gate structure and surrounding the second epitaxial semiconductor layer a semiconductor layer having the first conductivity type; forming a third doped region in a part of the first epitaxial semiconductor layer on a second side opposite to the first side of the gate structure, having a A second conductivity type of conductivity type; forming a fourth doped region in a part of the second doped region, having the second conductivity type and surrounding the second epitaxial semiconductor layer; forming a fifth doped region in the second epitaxial semiconductor layer A part of the third doped region has the second conductivity type; an insulating layer is formed on the fourth doped region and the gate structure and on a part of the fifth doped region; partly removing the second epitaxial semiconductor layer to form a second trench partially exposing the second doped region and a part of the fourth doped region; and forming a conductive contact on the second In the trench, wherein the conductive contact physically contacts the second epitaxial semiconductor layer.

The invention can reduce the manufacturing cost and element size of the lateral double-diffusion metal oxide semiconductor device.

In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view showing a conventional lateral double-diffused metal oxide semiconductor device.

2-6 are a series of schematic cross-sectional views showing a method for manufacturing a lateral double-diffused metal oxide semiconductor device according to an embodiment of the present invention.

7-11 are a series of schematic cross-sectional views showing a method for manufacturing a lateral double-diffused metal oxide semiconductor device according to another embodiment of the present invention.

Description of main components

detailed description

Please refer to the schematic cross-sectional views of FIGS. 2-6 , which show a method for manufacturing a lateral double-diffused metal oxide semiconductor device suitable for radio frequency circuit components according to an embodiment of the present invention.

Referring to FIG. 2 , firstly, a semiconductor substrate 200 such as a silicon substrate is provided. In one embodiment, the semiconductor substrate 200 has a first conductivity type such as P-type conductivity and a resistivity between 0.001 ohm-cm (Ω-cm) and 0.005 ohm-cm (Ω-cm). Next, an epitaxial semiconductor layer 202, such as an epitaxial silicon layer, is formed. The epitaxial semiconductor layer 202 can be temporarily field-doped with a first conductivity type dopant such as P-type conductivity when it is formed, and can have a thickness between 0.5 ohm-centimeter (Ω-cm)-1 ohm-centimeter (Ω-cm) dopant concentration. In one embodiment, the resistivity of the epitaxial semiconductor layer 210 is higher than the resistivity of the semiconductor substrate 200 .

Referring to FIG. 3 , a patterned gate structure G is then formed on a part of the epitaxial semiconductor layer 202. The gate structure G mainly includes a gate dielectric sequentially formed on a part of the epitaxial semiconductor layer 202. layer 204 and a gate electrode layer 206 . The gate dielectric layer 204 and the gate electrode layer 206 in the gate structure G can be fabricated using conventional gate technology and related materials, so the details of their fabrication will not be described here. Then, several appropriate masks (not shown) and several ion distribution processes (not shown) are performed to form a doped region 208 on the epitaxial semiconductor layer 202 on the left side of the gate structure G, respectively. , and another doped region 210 is formed in a portion of the epitaxial semiconductor layer 202 on an opposite side such as the right side of the gate structure G. In one embodiment, the doped region 208 has a first conductivity type such as a P-type conductivity type and a dopant concentration between 1×1013 atoms/cm²-5×1014 atoms/cm², while the doped region 210 has a concentration as opposite to A second conductivity type of the N-type conductivity type of the P-type conductivity type and a dopant concentration between 5x1011 atoms/cm2-5x1013 atoms/cm2, and the ion distribution process used to form the doped regions 208 and 210 can be Ion distribution process for oblique angle.

Another suitable patterning mask (not shown) and the use of an ion patterning process (not shown) are then employed to respectively form a portion of the doped regions 208 and 210 on opposite sides of the gate structure G, respectively. A doped region 212 and a doped region 214 are then implemented through a thermal diffusion process (not shown), thereby obtaining the configuration shown in FIG. 3 . In one embodiment, the doped region 212 formed in a part of the doped region 208 and the doped region 214 formed in a part of the doped region 210 respectively have a second conductivity type such as N-type conductivity and between The dopant concentration is 1×10 15 atoms/cm 2 -5×10 15 atoms/cm 2 , and the ion distribution process for forming the doped regions 212 and 214 can be the ion distribution process perpendicular to the surface of the epitaxial semiconductor layer 202 . In one embodiment, the doped region 210 is used as a drift-region, and the doped regions 212 and 214 are used as a source/drain region respectively.

Referring to FIG. 4 , an insulating layer 216 is then formed on the epitaxial semiconductor layer 202 , and the insulating layer 216 conformably covers several sidewalls and top surfaces of the gate structure G. Referring to FIG. A patterning process (not shown) is then used to form an opening 218 in a portion of the insulating layer 216 . As shown in FIG. 4 , the opening 218 exposes a part of the doped region 212 , while the rest of the epitaxial semiconductor layer 202 and the surface of the gate structure G are still covered by the insulating layer 216 . In one embodiment, the insulating layer 216 may include insulating materials such as silicon dioxide and silicon nitride, and may be formed by methods such as chemical vapor deposition.

Referring to FIG. 5 , an etching process (not shown) is performed using the insulating layer 216 as an etching photomask to form a trench 220 in the epitaxial semiconductor layer 202 exposed by the opening 218 . As shown in FIG. 5 , the trench 220 has a depth H1 and mainly penetrates through the doped region 212 , the doped region 208 and a part of the epitaxial semiconductor layer 202 . Next, perform an ion distribution procedure 222, and use the insulating layer 216 as a distribution photomask to distribute the dopant of the first conductivity type such as the P-type conductivity type into the epitaxial semiconductor layer 202 exposed by the trench 220 , and then obtain the doped region 224 disposed in a part of the epitaxial semiconductor layer 224 and a part of the semiconductor substrate 200 as shown in FIG. 5 through the implementation of a thermal diffusion process (not shown). In one embodiment, the doped region 224 has a first conductivity type such as P-type conductivity and a dopant concentration between 1×10 15 atoms/cm 2 and 5×10 15 atoms/cm 2 . In one embodiment, the dopant concentration in the doped region 224 is higher than that in the epitaxial semiconductor layer 202 .

Referring to FIG. 6 , a conductive layer 226 and another conductive layer 228 are sequentially deposited, wherein the conductive layer 226 is conformally formed on the surface of the insulating layer 216 and the bottom surface and sidewall of the semiconductor substrate 202 exposed by the trench 220 , and the conductive layer 228 is formed on the surface of the conductive layer 226 and fills the trench 220 . The conductive layers 226 and 228 are then patterned by performing a suitable patterned photomask layer (not shown) and a patterning process (not shown).

As shown in FIG. 6, conductive layers 226 and 228 are formed on the insulating layer 216 adjacent to the trench 220 and extend on the bottom and sidewalls of the trench 220, so as to cover the epitaxial semiconductor layer 202 exposed by the trench 220, doped The surfaces of the impurity regions 208 and 212, and the conductive layers 226 and 228 also cover the gate structure G and a part of the doped region 210 adjacent to the gate structure G, but the conductive layers 226 and 228 do not cover the doped region 214. The portion of conductive layer 226 and conductive layer 228 formed in trench 220 may serve as a conductive contact. Here, the doped region 224 partially surrounds the bottom surface and several sidewalls of the conductive layer 226 and the conductive layer 228 located in the trench 220 .

In one embodiment, the conductive layer 226 includes a conductive material such as titanium-titanium nitride alloy (Ti—TiN), and the conductive layer 228 includes a conductive material such as tungsten. Then, a dielectric material such as silicon dioxide and spin-on-glass (SOG) is deposited on the conductive layer 228, and the dielectric material covers the conductive layer 228, the insulating layer 216 and the gate structure G, thereby forming a The dielectric layer 230 has a substantially planar surface, serving as an interlayer dielectric (ILD). A trench 236 is then formed in a portion of the dielectric layer 230 and a portion of the insulating layer 216 on a portion of the doped region 214 by performing a patterning process (not shown) including lithography and etching processes, and the trench 236 is formed in a portion of the doped region 214. Groove 236 exposes a portion of doped region 214 . Next, a conductive layer 238 and a conductive layer 240 are sequentially deposited, wherein the conductive layer 238 is conformably formed on the surface of the dielectric layer 230 and on the sidewall exposed by the trench 236, and the conductive layer 240 is formed on the conductive layer The groove 236 is filled on the surface of the groove 238, and the part of the conductive layer 238 and the conductive layer 240 formed in the groove 236 is used as a conductive contact. In one embodiment, the conductive layer 238 includes a conductive material such as titanium-titanium nitride alloy (Ti—TiN), and the conductive layer 240 includes a conductive material such as tungsten. In this way, the lateral double-diffused MOS device according to an embodiment of the present invention is basically completed.

In one embodiment, the gate structure G and the doped regions 212 and 214 in the lateral double-diffused MOS device shown in FIG. The plurality of regions of the first conductivity type included are P-type regions, while the plurality of regions of the second conductivity type are N-type regions, so the formed lateral double-diffused metal oxide semiconductor device is an N-type lateral double-diffused metal oxide semiconductor device. In the semiconductor device, the doped region 212 is used as a source region at this time, and the doped region 214 is used as a drain region at this time.

In this embodiment, a current (not shown) can be made to flow laterally from the drain terminal (doped region 214 ) through the channel (not shown) under the gate structure G and toward the source terminal (doped region 212 ). , and then guide the doped region 208, the conductive layers 226 and 228 and the doped region 224 to reach the semiconductor substrate 200, so as to avoid inductive coupling (inductor coupling) and crosstalk (cross talk) between adjacent circuit elements, etc. Problems are not expected to occur.

In this embodiment, by forming the conductive layers 226 and 228 in the trench 220 and the diffusion region 224 buried in the epitaxial semiconductor layer 202 and contacting the semiconductor substrate 200, it is possible to avoid the use of high-concentration, high-dose ion cloth. value to form the P+ doped region 120 as shown in FIG. The predetermined distance D1 shown.

In this way, compared with the N-type lateral double-diffused metal-oxygen-semiconductor device shown in FIG. 1, the lateral double-diffused metal-oxygen-semiconductor device shown in FIG. It is beneficial to reduce the manufacturing cost and element size of the N-type lateral double-diffused metal oxide semiconductor device, and the formation of the diffusion region 224 and the conductive layers 226 and 228 also helps to reduce the on-resistance (Ron) of the N-type lateral double-diffused metal oxide semiconductor device. ).

In addition, in another embodiment, the multiple regions of the first conductivity type included in the lateral double-diffused metal oxide semiconductor device shown in FIG. 6 are N-type regions, and the multiple regions of the second conductivity type are P-type regions. type region, so the formed lateral double diffused metal oxide semiconductor device is a P type lateral double diffused metal oxide semiconductor device.

Please refer to the schematic cross-sectional views of FIGS. 7-11 , which show a method for manufacturing a lateral double-diffused metal oxide semiconductor device suitable for radio frequency circuit components according to another embodiment of the present invention.

Referring to FIG. 7 , firstly, a semiconductor substrate 300 such as a silicon substrate is provided. In one embodiment, the semiconductor substrate 300 has a first conductivity type such as P-type conductivity and a resistivity between 0.001 ohm-cm (Ω-cm) and 0.005 ohm-cm (Ω-cm). Then an epitaxial semiconductor layer 301 is formed on the semiconductor substrate 300 . The epitaxial semiconductor layer 301 can be temporarily field-doped with a first conductivity type impurity such as P-type conductivity characteristics and a resistivity between 0.5 ohm-centimeter (Ω-cm)-1 ohm-centimeter (Ω-cm) when it is formed. . In one embodiment, the resistivity of the epitaxial semiconductor layer 301 is higher than that of the semiconductor substrate 300 . Next, a patterned photomask layer 302 is formed on the epitaxial semiconductor layer 301 , the patterned photomask layer 302 includes an opening 303 , and the opening 303 exposes a part of the epitaxial semiconductor layer 301 . The material of the patterned photomask layer 302 is, for example, photoresist, so the opening 303 can be formed by related processes such as conventional lithography and etching. Then, using the patterned photomask layer 302 as an etching photomask, an etching process (not shown) is performed to form a trench 304 in the epitaxial semiconductor layer 301 exposed by the opening 303 .

As shown in FIG. 7 , the trench 304 has a depth H2. Next, perform an ion distribution procedure 306, and use the patterned photomask layer 302 as a distribution photomask to distribute the dopant of the first conductivity type such as the P-type conductivity type to the area exposed by the trench 304. In the epitaxial semiconductor layer 301, and then through the implementation of a thermal diffusion process (not shown), the doping region 308 disposed in a part of the epitaxial semiconductor layer 301 and a part of the semiconductor substrate 300 as shown in FIG. 7 is obtained. In one embodiment, the doped region 308 has a dopant concentration ranging from 1×10 15 atoms/cm 2 to 5×10 15 atoms/cm 2 . In one embodiment, the dopant concentration in the doped region 308 is higher than that in the epitaxial semiconductor layer 301 .

Please refer to FIG. 8, after removing the patterned photomask layer 302, an epitaxial growth process (not shown) is then performed on the surface of the part of the epitaxial semiconductor layer 301 exposed by the trench 304 and the epitaxial semiconductor layer An epitaxial semiconductor material (not shown) is grown on the top surface of 301 , and is temporarily doped with a dopant of the first conductivity type such as P-type conductivity when it is formed. Then a planarization process (not shown) is performed to remove the epitaxial semiconductor material above the surface of the epitaxial semiconductor layer 301, and then an epitaxial semiconductor layer 310 doped with epitaxial semiconductor material is formed in the trench 304 as an epitaxial semiconductor layer 310. For conductive layer. In one embodiment, the epitaxial semiconductor layer 310 has a resistivity between 0.001 ohm-cm (Ω-cm) and 0.05 ohm-cm (Ω-cm).

Referring to FIG. 9 , a patterned gate structure G is then formed on a part of the epitaxial semiconductor layer 300. This gate structure G mainly includes a gate dielectric sequentially formed on a part of the epitaxial semiconductor layer 301. layer 312 and a gate electrode layer 314 . The gate dielectric layer 312 and the gate electrode layer 314 in the gate structure G can be fabricated using conventional gate technology and related materials, so the details of their fabrication will not be described here. Then, several appropriate masks (not shown) and several ion distribution processes (not shown) are performed to form a doped region 316 on the epitaxial semiconductor layer 301 on the left side of the gate structure G, respectively. , and another doped region 318 is formed in a portion of the epitaxial semiconductor layer 301 on an opposite side such as the right side of the gate structure G. In one embodiment, the doped region 316 has a first conductivity type such as a P-type conductivity type and a dopant concentration between 1×1013 atoms/cm2-5×1014 atoms/cm2, while the doped region 318 has a concentration as opposite to A second conductivity type of the N-type conductivity type of the P-type conductivity type and a dopant concentration between 5x1011 atoms/cm2-5x1013 atoms/cm2, and the ion distribution process used to form the doped regions 316 and 318 can be It is the ion distribution process of oblique angle.

Another suitable patterning mask (not shown) and the use of an ion patterning process (not shown) are then employed to respectively form a portion of the doped regions 316 and 318 on opposite sides of the gate structure G respectively. A doped region 320 and a doped region 322 are then implemented through a thermal diffusion process (not shown), thereby obtaining the arrangement shown in FIG. 9 . In one embodiment, the doped region 320 formed in a part of the doped region 316 and the doped region 322 formed in a part of the doped region 318 respectively have a second conductivity type such as N-type conductivity and between The dopant concentration is 1×10 15 atoms/cm 2 -5×10 15 atoms/cm 2 , and the ion distribution process for forming the doped regions 320 and 322 can be the ion distribution process perpendicular to the surface of the epitaxial semiconductor layer 210 . In one embodiment, the doped region 318 is used as a drift-region, and the doped regions 320 and 322 are used as a source/drain region respectively. As shown in FIG. 9 , the doped regions 316 and 320 of the epitaxial semiconductor layer 301 formed on the left side of the gate structure G surround a part of the epitaxial semiconductor layer 310 .

Referring to FIG. 10 , an insulating layer 324 is then formed on the epitaxial semiconductor layer 301 , and the insulating layer 324 conformably covers several sidewalls and top surfaces of the gate structure G. Referring to FIG. A patterning process (not shown) is then used to form an opening 325 in a portion of the insulating layer 324 . As shown in FIG. 10, the opening 325 exposes a part of the conductive layer 310 surrounded by the doped region 320, while the rest of the epitaxial semiconductor layer 301 and the surface of the gate structure G are still covered by the insulating layer 324. . In one embodiment, the insulating layer 324 may include insulating materials such as silicon dioxide and silicon nitride, and may be formed by methods such as chemical vapor deposition. Then, using the insulating layer 324 as an etching photomask, an etching process (not shown) is performed to partially remove the inside of the conductive layer 310 exposed by the opening 325 and form a trench 326 . As shown in FIG. 10 , the trench 326 has a depth H3 , and the trench 326 mainly exposes part of the doped region 320 , the doped region 316 and the epitaxial semiconductor layer 310 .

Referring to FIG. 11 , a conductive layer 328 and another conductive layer 330 are sequentially deposited, wherein the conductive layer 328 is conformally formed on the surface of the insulating layer 324 and the doped region exposed by the trench 326 (see FIG. 10 ). 320 , the doped region 316 , and the bottom and sidewalls of the conductive layer 310 , while the conductive layer 330 is formed on the surface of the conductive layer 328 and fills up the trench 326 . These conductive layers 328 and 330 are then patterned by performing a suitable patterned photomask layer (not shown) and a patterning process (not shown).

As shown in FIG. 11 , conductive layers 328 and 330 are formed on the insulating layer 324 adjacent to the trench 326 and extend on the bottom and sidewalls of the trench 326, so as to cover the epitaxial semiconductor layer 310 exposed by the trench 326, doped The surfaces of the impurity regions 316 and 320, and the conductive layers 328 and 330 also cover the gate structure G and a part of the doped region 318 adjacent to the gate structure G, but the conductive layers 328 and 330 do not cover the doped regions 322. The portions of the conductive layer 328 and the conductive layer 330 formed in the trench 326 and the underlying conductive layer 310 can be used as a conductive contact.

In one embodiment, the conductive layer 328 includes a conductive material such as titanium-titanium nitride alloy (Ti—TiN), and the conductive layer 330 includes a conductive material such as tungsten. Then, a dielectric material such as silicon dioxide and spin-on-glass (SOG) is deposited on the conductive layer 330, and the dielectric material covers the conductive layer 330, the insulating layer 324 and the gate structure G, thereby forming a The dielectric layer 332 has a substantially planar surface, serving as an interlayer dielectric (ILD). A trench 336 is then formed in a portion of the dielectric layer 332 and a portion of the insulating layer 324 on a portion of the doped region 322 by performing a patterning process (not shown) including lithography and etching processes, and the trench 336 is formed. Groove 336 exposes a portion of doped region 322 . Next, a conductive layer 338 and a conductive layer 340 are sequentially deposited, wherein the conductive layer 338 is conformably formed on the surface of the dielectric layer 332 and on the sidewall exposed by the trench 336, and the conductive layer 340 is formed on the conductive layer The groove 336 is filled on the surface of the groove 338, and the part of the conductive layer 338 and the conductive layer 340 formed in the groove 336 is used as a conductive contact. In one embodiment, the conductive layer 338 includes a conductive material such as titanium-titanium nitride alloy (Ti—TiN), and the conductive layer 340 includes a conductive material such as tungsten. In this way, the lateral double-diffused MOS device according to an embodiment of the present invention is basically completed. In one embodiment, the multiple regions of the first conductivity type included in the lateral double-diffused metal oxide semiconductor device shown in FIG. 11 are P-type regions, and the multiple regions of the second conductivity type are N-type regions, Therefore, the formed lateral double diffused metal oxide semiconductor device is an N-type lateral double diffused metal oxide semiconductor device, and the doped region 320 is now used as a source region, and the doped region 322 is now used as a drain region. .

In this embodiment, a current (not shown) can be made to flow laterally from the drain terminal (doped region 322 ) through the channel (not shown) under the gate structure G and toward the source terminal (doped region 320 ). , then guide the doped regions 320 and 316, the epitaxial semiconductor layer 310, the conductive layers 328 and 330, and the doped region 308 to the semiconductor substrate 300, so as to avoid inductive coupling (inductor coupling) and Undesirable problems such as cross talk occur.

In this embodiment, by forming the conductive layers 328 and 330 in the trench 326, the epitaxial semiconductor layer 310, and the diffusion region 308 buried in the epitaxial semiconductor layer 301 and contacting the semiconductor substrate 300, it is possible to avoid the use of high concentration, A high dose of ion distribution is used to form the P+ doped region 120 as shown in FIG. At the predetermined distance D1 shown in FIG. 1 . Thus, compared with the N-type lateral double-diffused metal-oxygen-semiconductor device shown in FIG. 1, the lateral double-diffused metal-oxygen-semiconductor device shown in FIG. It is beneficial to reduce the manufacturing cost and element size of the N-type lateral double-diffused metal-oxygen semiconductor device, and the formation of the diffusion region 308, the epitaxial semiconductor layer 310, and the conductive layers 328 and 330 also helps to reduce the cost of the N-type lateral double-diffused metal-oxygen semiconductor device. On-resistance (Ron).

In addition, in another embodiment, the multiple regions of the first conductivity type included in the lateral double-diffused metal oxide semiconductor device shown in FIG. 11 are N-type regions, and the multiple regions of the second conductivity type are P-type regions. type region, so the formed lateral double diffused metal oxide semiconductor device is a P type lateral double diffused metal oxide semiconductor device.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the scope of the patent application.

Claims (14)

1. A kind of 1. horizontal double diffusion metal-oxide-semiconductor (MOS) device, it is characterised in that the horizontal double diffusion metal-oxide-semiconductor (MOS) device bag Include：

   Semiconductor substrate, there is one first conduction type；

   One epitaxial semiconductor layer, it is formed on the semiconductor substrate, there is first conduction type；

   One grid structure, it is arranged on one of the epitaxial semiconductor layer；

   One first doped region, in one of the epitaxial semiconductor layer for being positioned adjacent to one first side of the grid structure, have First conduction type；

   One second doped region, it is arranged at the one of the epitaxial semiconductor layer of one second side of first side of the relative grid structure In portion, there is one second conduction type in contrast to first conduction type；

   One the 3rd doped region, is arranged in one of first doped region, has second conduction type；

   One the 4th doped region, is arranged in one of second doped region, has second conduction type；

   One groove, it is formed at the 3rd doped region, first doped region and the epitaxial semiconductor layer below first doped region One in, and the groove does not extend to the semiconductor substrate；

   One conductive contact thing, in the groove, including the epitaxial semiconductor layer with first conduction type and it is located at One first conductive layer and one second conductive layer in the epitaxial semiconductor layer, and second conductive layer is the first conductive layer institute ring Around；And

   One the 5th doped region, in one of the epitaxial semiconductor layer being arranged at below first doped region, there is this first to lead Electric type, the 5th doped region material contact semiconductor substrate and the partial sidewall around the conductive contact thing and bottom surface, and The 5th non-material contact of doped region first doped region.
2. 2. horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 1, it is characterised in that first conduction type is P-type and second conduction type is N-type, or first conduction type is N-type and second conduction type is p-type.
3. 3. horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 1, it is characterised in that the 3rd doped region is one Source area, and the 4th doped region is a drain region.
4. 4. horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 1, it is characterised in that the epitaxial semiconductor layer One doping concentration is less than a doping concentration of the 5th doped region.
5. A kind of 5. manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device, it is characterised in that the horizontal double diffusion gold oxygen half The manufacture method of conductor device includes：

   Semiconductor substrate is provided, there is one first conduction type；

   An epitaxial semiconductor layer is formed on the semiconductor substrate, there is first conduction type；

   A grid structure is formed on one of the epitaxial semiconductor layer；

   One first doped region is formed in one of the epitaxial semiconductor layer of one first side of the neighbouring grid structure, having should First conduction type；

   One second doped region is formed in the one of the epitaxial semiconductor layer of one second side of first side of the grid structure relatively In portion, there is one second conduction type in contrast to first conduction type；

   One the 3rd doped region is formed in one of first doped region, there is second conduction type；

   One the 4th doped region is formed in one of second doped region, there is second conduction type；

   An insulating barrier is formed on second doped region and the grid structure and on one of the 3rd doped region；

   A groove is formed in the epitaxial semiconductor layer below the 3rd doped region of the insulating barrier, first doped region One in, and the groove does not extend to the semiconductor substrate；

   An ion implantation program is implemented, the admixture of implantation first conduction type is in the epitaxial semiconductor exposed for the groove In layer, to form one the 5th doped region, wherein the 5th doped region material contact semiconductor substrate and non-material contact this First doped region；And

   A conductive contact thing is formed in the groove, wherein the doped region of conductive contact thing material contact the 5th.
6. 6. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 5, it is characterised in that this first Conduction type is p-type and second conduction type is N-type, or first conduction type is N-type and second conduction type is P Type.
7. 7. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 6, it is characterised in that the 3rd Doped region is source area, and the 4th doped region is drain region.
8. 8. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 5, it is characterised in that in this from After sub- implantation program, a dopant concentration of the 5th doped region exposed for the groove is higher than the one of the epitaxial semiconductor layer Dopant concentration.
9. 9. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 5, it is characterised in that the conduction Contactant includes one first conductive layer and one second conductive layer circular for first conductive layer.
10. A kind of 10. manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device, it is characterised in that the horizontal double diffusion gold oxygen half The manufacture method of conductor device includes：

    Semiconductor substrate is provided, there is one first conduction type；

    One first epitaxial semiconductor layer is formed on the semiconductor substrate, there is first conduction type；

    A first groove is formed in one of first epitaxial semiconductor layer, and not extend to this semiconductor-based for the first groove Plate；

    Implement an ion implantation program, the admixture of implantation first conduction type in exposed for the first groove this outside first Prolong in semiconductor layer, to form one first doped region, wherein the first doped region material contact semiconductor substrate；

    One second epitaxial semiconductor layer is formed in the first groove；

    A grid structure is formed on one of the epitaxial semiconductor layer, neighbouring second epitaxial semiconductor layer；

    Formed one second doped region in one of first epitaxial semiconductor layer of one first side of the neighbouring grid structure simultaneously Around second epitaxial semiconductor layer, there is first conduction type, wherein the non-material contact of the first doped region this second mix Miscellaneous area；

    One the 3rd doped region is formed in first epitaxial semiconductor layer of one second side of first side of the relative grid structure One in, have in contrast to first conduction type one second conduction type；

    One the 4th doped region is formed in one of second doped region, with second conduction type and surround second extension Semiconductor layer；

    One the 5th doped region is formed in one of the 3rd doped region, there is second conduction type；

    An insulating barrier is formed on the 4th doped region and the grid structure and on one of the 5th doped region；

    Part removes second epitaxial semiconductor layer to form a second groove, and second doped region is exposed in the second groove part With one of the 4th doped region；And

    A conductive contact thing is formed in the second groove, wherein the conductive contact thing material contact second epitaxial semiconductor Layer.
11. 11. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 10, it is characterised in that this One conduction type is p-type and second conduction type is N-type, or first conduction type is N-type and second conduction type is P Type.
12. 12. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 10, it is characterised in that this Four doped regions are source area, and the 5th doped region is drain region.
13. 13. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 10, it is characterised in that in this After ion implantation program, the dopant concentration of first doped region exposed for the first groove is partly led higher than first extension The dopant concentration of body layer.
14. 14. the manufacture method of horizontal double diffusion metal-oxide-semiconductor (MOS) device according to claim 10, it is characterised in that this is led Electrical contact includes one first conductive layer and one second conductive layer circular for first conductive layer.