CN104637861A - Silicon through-hole process - Google Patents
Silicon through-hole process Download PDFInfo
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- CN104637861A CN104637861A CN201310557105.2A CN201310557105A CN104637861A CN 104637861 A CN104637861 A CN 104637861A CN 201310557105 A CN201310557105 A CN 201310557105A CN 104637861 A CN104637861 A CN 104637861A
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- Prior art keywords
- hole
- tungsten
- layer
- silicon
- deep trench
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 58
- 239000010703 silicon Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 44
- 239000010937 tungsten Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010936 titanium Substances 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a silicon through-hole process. The silicon through-hole process is integrated with an active device process and includes steps of depositing a metal antimedium layer on a silicon wafer after manufacturing an active device on the silicon wafer; etching a silicon through hole area, then forming an oxidation layer, depositing titanium and titanium nitride and depositing another metal tungsten layer; re-etching and depositing a second metal tungsten layer; etching a contact hole and carrying out a metal interconnection process; thinning the back. The silicon through-hole process realizes integration of the silicon through-hole process on the basis of not changing existing processes and procedures, resistance and inductance of the device are reduced, and performance of RF (radio frequency) products is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, refer to a kind of silicon via process method mutually integrated with active device technique especially.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed, larger data storage amount and more function faster, and semiconductor chip is to more high integration future development.And the integrated level of semiconductor chip is higher, the characteristic size (CD:Critical Dimension) of semiconductor device is less.
Silicon through hole (TSV:through silicon via) technique is a kind of emerging ic manufacturing process, the circuit being produced on silicon chip upper surface can be connected to silicon chip back side by the metal of filling in silicon through hole by it, in conjunction with three-dimension packaging technique, make IC layout from conventional two-dimensional be arranged side by side develop into more advanced three-dimensional stacked, such component encapsulation is more compact, chip lead distance is shorter, thus greatly can improve frequency characteristic and the power characteristic of circuit.Existing silicon via process, comprising: utilize plasma etching at crystal column surface etching through hole; Chemical gaseous phase depositing process is adopted to form insulating barrier in through-hole surfaces; Metal SiClx through hole, takes copper electro-plating method filling vias, and adopts CMP to remove unnecessary copper electrodeposited coating; Carry out wafer rear grinding, expose copper conductor layer, complete through-silicon via structure.
Above-mentioned technique makes TSV and the integrated of device have larger difficulty: when the ratio of silicon through hole in silicon chip is too large, and silicon chip stress is comparatively large, and easy buckling deformation, affects subsequent process steps; More difficult control silicon through hole is at the length of exposure of silicon chip back side.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of silicon via process method, is mutually integrated with active device technique, comprises following step:
Step one, after silicon chip completing the making of active device, deposit layer of metal front medium layer on silicon chip, this thickness of dielectric layers depends on the height of active device and passive device;
Step 2, utilizes lithographic definition to go out silicon via regions, etches before-metal medium layer and the silicon chip of described silicon via regions successively, forms deep trench or hole;
Step 3, whole silicon chip surface forms oxide layer, and sidewall and the bottom in deep trench or hole synchronously form oxide layer;
Step 4, deposit one deck titanium and titanium nitride; Described titanium and titanium nitride are also deposited to the surf zone of described deep trench or outside, hole simultaneously;
Step 5, deposit ground floor tungsten on described titanium and titanium nitride, deep trench or hole are not filled up by described ground floor tungsten;
Step 6, carries out back carving to described ground floor tungsten;
Step 7, be formed with deposit second layer tungsten in the deep trench of described ground floor tungsten or hole sidewall and bottom, described deep trench or hole are filled up or are not filled up by described second layer tungsten; Described second layer tungsten is also deposited to the surf zone of described deep trench or outside, hole simultaneously;
Step 8, carries out back carving or cmp to the tungsten layer be made up of described ground floor tungsten and described second layer tungsten;
Step 9, after contact hole etching and front metal have interconnected, carries out thinning to the back side of described silicon chip, the described titanium be filled in described deep trench or hole and titanium nitride, described ground floor tungsten and second layer tungsten is exposed from the bottom in described deep trench or hole;
Step 10, the back side of silicon chip is carried out Metal deposition and is made back metal figure, is formed be electrically connected with the tungsten in groove or hole.
Further, in step one, active device on silicon chip and passive device cover by the before-metal medium layer of deposit completely.
Further, in step 8, return and to carve or cmp exposes to the titanium of substrate surface and titanium nitride layer.
Silicon via process method of the present invention, what can realize with active device technique on the basis not changing Conventional processing methods and flow process is integrated, reduces resistance and the inductance of interiors of products interconnection, improves the performance of RF product.
Accompanying drawing explanation
Fig. 1 ~ 10 are block diagram of silicon via process method of the present invention;
Figure 11 is the process chart of silicon via process method of the present invention.
Description of reference numerals
1 is silicon substrate, and 2 is before-metal medium layers, and 3 is deep trench or hole, and 4 is oxide layers, and 5 is titanium and titanium nitride, and 6 is tungsten (6A is first layer metal tungsten, and 6B is second layer metal tungsten), and 7 is metal interconnecting wires, and 8 is dielectric layers, and 9 is back metals.
Embodiment
A kind of silicon via process method of the present invention, is mutually integrated with active device technique, comprises following step:
Step one, as shown in Figure 1, after silicon chip completing the making of active device, deposit layer of metal front medium layer on silicon chip, this thickness of dielectric layers depends on the height of active device and passive device.
Step 2, as shown in Figure 2, utilizes lithographic definition to go out silicon via regions, etches before-metal medium layer and the silicon chip of described silicon via regions successively, forms deep trench or hole.
Step 3, as shown in Figure 3, whole silicon chip surface forms oxide layer, and sidewall and the bottom in deep trench or hole synchronously form oxide layer.
Step 4, as shown in Figure 4, deposit one deck titanium and titanium nitride; Described titanium and titanium nitride are also deposited to the surf zone of described deep trench or outside, hole simultaneously.
Step 5, as shown in Figure 5, deposit ground floor tungsten on described titanium and titanium nitride, deep trench or hole are not filled up by described ground floor tungsten.
Step 6, as shown in Figure 6, carries out back carving to described ground floor tungsten.
Step 7, as shown in Figure 7, be formed with deposit second layer tungsten in the deep trench of described ground floor tungsten or hole sidewall and bottom, described deep trench or hole are filled up by described second layer tungsten; Described second layer tungsten is also deposited to the surf zone of described deep trench or outside, hole simultaneously.
Step 8, as shown in Figure 8, carries out back carving or cmp to the tungsten layer be made up of described ground floor tungsten and described second layer tungsten; Return and to carve or cmp exposes to the titanium of substrate surface and titanium nitride layer.
Step 9, as shown in Figure 9, after contact hole etching and front metal have interconnected, carry out thinning to the back side of described silicon chip, from the bottom in described deep trench or hole, the described titanium be filled in described deep trench or hole and titanium nitride, described ground floor tungsten and described second layer tungsten are exposed.
Step 10, as shown in Figure 10, the back side of silicon chip is carried out Metal deposition and is made back metal figure, and formed with the tungsten in groove or hole and be electrically connected, silicon via process completes.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. a silicon via process method, is mutually integrated with active device technique, it is characterized in that: comprise following step:
Step one, after silicon chip completing the making of active device, deposit layer of metal front medium layer on silicon chip, this thickness of dielectric layers depends on the height of active device and passive device;
Step 2, utilizes lithographic definition to go out silicon via regions, etches before-metal medium layer and the silicon chip of described silicon via regions successively, forms deep trench or hole;
Step 3, whole silicon chip surface forms oxide layer, and sidewall and the bottom in deep trench or hole synchronously form oxide layer;
Step 4, deposit one deck titanium and titanium nitride; Described titanium and titanium nitride are also deposited to the surf zone of described deep trench or outside, hole simultaneously;
Step 5, deposit ground floor tungsten on described titanium and titanium nitride, deep trench or hole are not filled up by described ground floor tungsten;
Step 6, carries out back carving to described ground floor tungsten;
Step 7, be formed with deposit second layer tungsten in the deep trench of described ground floor tungsten or hole sidewall and bottom, described deep trench or hole are filled up by described second layer tungsten; Described second layer tungsten is also deposited to the surf zone of described deep trench or outside, hole simultaneously;
Step 8, carries out back carving or cmp to the tungsten layer be made up of described ground floor tungsten and described second layer tungsten;
Step 9, after contact hole etching and front metal have interconnected, carries out thinning to the back side of described silicon chip, the described titanium be filled in described deep trench or hole and titanium nitride, described ground floor tungsten and second layer tungsten is exposed from the bottom in described deep trench or hole;
Step 10, the back side of silicon chip is carried out Metal deposition and is made back metal figure, is formed be electrically connected with the tungsten in groove or hole.
2. silicon via process method as claimed in claim 1, it is characterized in that: in step one, active device on silicon chip and passive device cover by the before-metal medium layer of deposit completely.
3. silicon via process method as claimed in claim 1, is characterized in that: in step 8, returns to carve or cmp exposes to the titanium of substrate surface and titanium nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310557105.2A CN104637861A (en) | 2013-11-11 | 2013-11-11 | Silicon through-hole process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310557105.2A CN104637861A (en) | 2013-11-11 | 2013-11-11 | Silicon through-hole process |
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| Publication Number | Publication Date |
|---|---|
| CN104637861A true CN104637861A (en) | 2015-05-20 |
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| CN201310557105.2A Pending CN104637861A (en) | 2013-11-11 | 2013-11-11 | Silicon through-hole process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611018A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of method and crystal circle structure for improving wafer stress |
| CN107934907A (en) * | 2017-12-12 | 2018-04-20 | 成都海威华芯科技有限公司 | A kind of depth Si through-hole structures |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412194A (en) * | 2011-08-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Manufacturing method of through silicon via |
| CN102412193A (en) * | 2011-06-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Through silicon via filling method |
| US20130113105A1 (en) * | 2009-03-23 | 2013-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd | Barrier For Through-Silicon Via |
| US20130181330A1 (en) * | 2012-01-13 | 2013-07-18 | Qualcomm Incorporated | Integrating through substrate vias into middle-of-line layers of integrated circuits |
-
2013
- 2013-11-11 CN CN201310557105.2A patent/CN104637861A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130113105A1 (en) * | 2009-03-23 | 2013-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd | Barrier For Through-Silicon Via |
| CN102412193A (en) * | 2011-06-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Through silicon via filling method |
| CN102412194A (en) * | 2011-08-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Manufacturing method of through silicon via |
| US20130181330A1 (en) * | 2012-01-13 | 2013-07-18 | Qualcomm Incorporated | Integrating through substrate vias into middle-of-line layers of integrated circuits |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611018A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of method and crystal circle structure for improving wafer stress |
| CN107934907A (en) * | 2017-12-12 | 2018-04-20 | 成都海威华芯科技有限公司 | A kind of depth Si through-hole structures |
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Application publication date: 20150520 |