CN104636290B - Fpga chip configuration structure and collocation method based on multi-configuration chain group - Google Patents

Abstract

The present invention relates to an FPGA chip configuration structure and configuration method based on a multi-configuration chain group. The structure includes: a main controller that receives and parses multiple sets of bit stream files sent serially from the outside to generate serial multiple sets of bit streams Configuration information; wherein each group of bit stream configuration information is used to realize an application; the multiplexer receives the configuration chain group selection signal, and sends the current group of bit stream configuration information according to the current configuration chain group selection signal; A plurality of configuration chain groups, each configuration chain group includes a plurality of configuration chain groups; among the plurality of configuration chain groups, the set of a configuration chain group of the same application in each configuration chain group is a group of the application Configuration chain group; each group of configuration chain groups receives and stores a corresponding set of bit stream configuration information; multiple demultiplexers receive and obtain from a corresponding group of configuration chain groups according to the configuration chain group selection signal The bitstream configuration information initiates the configuration of the FPGA chip.

Description

FPGA chip configuration structure and configuration method based on multi-configuration chain group

technical field

The present invention relates to a field programmable logic gate array (Field Programmable Gate Array, FPGA) chip configuration structure, in particular to an FPGA chip configuration structure and configuration method based on a multi-configuration chain group that can realize fast reconfiguration.

Background technique

FPGA is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability. These features make FPGA more and more widely used in data processing, communication, network and many other fields. Especially its reconfigurability, users can make it perform different functions by downloading different configuration files. Therefore, FPGA is often used in embedded systems that need to change functions according to the situation, such as software defined radio (Software DefinedRadio, SDR) system, remote sensor (Remote Sensors, RS) system, etc. However, for embedded systems with strict performance requirements, such as real-time embedded systems, the system response needs to meet strict timing constraints. These timing constraints are usually calculated in units of milliseconds and microseconds. The configuration structure of a traditional FPGA is shown in FIG. 1 , and the flowchart of its configuration and reconfiguration is shown in FIG. 2 . After the FPGA is powered on, it needs to go through three main processes: power-on detection and initialization, initial bitstream file download, and startup configuration process (startup). The startup configuration process is a process in which all configuration links receive the parsed content and complete the configuration of all content. When the FPGA needs to perform the reconfiguration switching function in the user mode, the user needs to download the complete bitstream file and perform the startup configuration process. During this process, the FPGA has been in a state of suspending work until the end of the startup configuration process, and the FPGA begins to perform new functions. The reconfiguration of a traditional FPGA is for the entire device, so the bitstream file downloaded during the reconfiguration process is the same size as the initialization bitstream file and is a complete bitstream file. With the continuous increase of user requirements, the hardware resources contained in the FPGA are constantly increasing, and the size of the corresponding bitstream file is also increasing, resulting in an increase in the time required for FPGA reconfiguration. Therefore, it has become more and more difficult for FPGAs reconfigured by traditional configuration methods to meet the timing requirements of real-time systems. The long reconfiguration time of FPGA has become a restrictive factor for FPGA application. How to speed up the process of FPGA reconfiguration has always been a hot spot in FPGA research.

In order to strengthen the reconfigurable capability of the FPGA and reduce the time required for FPGA reconfiguration. FPGA manufacturers Xilinx and Altera proposed the concept of Partial Reconfiguration (PR) in 2004 and 2011 respectively. The configuration and reconfiguration flowchart of the PR technology is shown in Figure 3. Compared with traditional FPGA configuration, PR technology needs to go through three main processes after power-on to execute user mode. The biggest advantage of PR technology is that in the process of reconfiguration, only a partial bitstream file (Partial Bitstream) needs to be downloaded to configure the dynamic area of the FPGA, so that the FPGA can dynamically change its function. The dynamic area of the FPGA, that is, the area that needs to change its function, can be defined by the user according to the design, and it can be one area or multiple areas. Compared with the bitstream file that configures the entire FPGA, the partial bitstream file only contains configuration data for the dynamic area, and the dynamic area is usually only a part of the FPGA, so the partial bitstream file is much smaller than the traditional full bitstream file. Download It also takes a lot less time. On the other hand, PR technology does not involve the configuration of resources such as the global clock and input/output I/O, so when the download of some bitstream files is completed, only the local registers, lookup tables, etc. model. Therefore, during the startup configuration process, PR technology is also faster than traditional FPGA reconfiguration. However, the existing PR technology is only applicable to multiple different application occasions with common functions, and the FPGA can realize dynamic switching of multiple different applications only by changing local functions. Therefore, the PR reconfiguration capability has certain limitations and cannot completely change all functions of the FPGA.

Contents of the invention

The purpose of the present invention is to provide a kind of FPGA chip configuration structure and configuration method based on multi-configuration chain group for the defect of prior art, by adding multiple groups of configuration chain groups, each configuration chain group includes a plurality of configuration chain groups It is used to store the bitstream configuration information of a function of different applications, so that during the FPGA configuration or reconfiguration process, it is only necessary to select the configuration chain group of the same application in the corresponding multiple configuration chain groups to read the bitstream configuration information to complete the startup Just configure it.

In the first aspect, the embodiment of the present invention provides a FPGA chip configuration structure based on a multi-configuration chain group, including:

The main controller receives multiple sets of bit stream files sent serially from the outside, and sequentially parses the bit stream files to generate multiple sets of serial bit stream configuration information; wherein, each set of bit stream configuration information is used to realize an application;

The multiplexer receives the configuration chain group selection signal, and sends the current set of bit stream configuration information according to the current configuration chain group selection signal;

A plurality of configuration chain groups, each configuration chain group includes a plurality of configuration chain groups; among the plurality of configuration chain groups, the set of a configuration chain group of the same application in each configuration chain group is a group of the application Configure chain groups; each group of configuration chain groups receives and stores a corresponding set of bit stream configuration information sent by the multiplexer according to the configuration chain group selection signal;

Multiple groups of demultiplexers respectively receive the configuration chain group selection signals, and obtain bitstream configuration information from a corresponding group of configuration chain groups according to the configuration chain group selection signals to start configuring the FPGA chip.

Preferably, the structure further includes a configuration chain group selection signal input port, and an external configuration chain group selection signal is transmitted to the multiplexer or demultiplexer through the configuration chain group selection signal input port .

Preferably, each group of bit stream configuration information includes a plurality of function configuration information, and each configuration chain group receives and stores a corresponding function sent by the multiplexer according to the configuration chain group selection signal configuration information.

Preferably, the number of the demultiplexers matches the number of the configuration chain groups.

Preferably, each demultiplexer selects a corresponding configuration chain group from the matched configuration chain groups according to the configuration chain group selection signal to obtain bit stream configuration information to start the configuration of the FPGA chip.

Preferably, when the serial multiple groups of bit stream configuration information are stored in a plurality of configuration chain groups, the FPGA chip enters the working state; when the FPGA chip is in the working state, and when the multiplexer receives again When the chain group selection signal and bit stream configuration information are configured, the multiplexer sends the currently received set of bit stream configuration information to the corresponding configuration chain group for storage according to the configuration chain group selection signal, and overwrites all Bitstream configuration information previously stored in the configuration chain group.

In the second aspect, the embodiment of the present invention provides a configuration method of FPGA chip configuration structure based on multi-configuration chain group, including:

The main controller receives multiple sets of bit stream files sent serially from the outside, and sequentially parses the bit stream files to generate multiple sets of serial bit stream configuration information; wherein, each set of bit stream configuration information is used to realize a application;

The multiplexer receives the configuration chain group selection signal, and sends the current set of bit stream configuration information according to the current configuration chain group selection signal;

Each group of configuration chain groups receives and stores a corresponding set of bit stream configuration information sent by the multiplexer according to the configuration chain group selection signal; wherein the group of configuration chain groups is: a plurality of configuration chain groups , a set of configuration chain groups for the same application in each configuration chain group;

The demultiplexer receives the configuration chain group selection signal, and obtains bitstream configuration information from a corresponding group of configuration chain groups according to the configuration chain group selection signal to start the configuration of the FPGA chip.

Preferably, when the FPGA chip is in the working state, and when the multiplexer receives the configuration chain group selection signal and the bit stream configuration information again, the multiplexer will The bitstream configuration information is sent to the corresponding configuration chain group for storage according to the configuration chain group selection signal, and the previously stored bitstream configuration information in the configuration chain group is overwritten.

The FPGA chip configuration structure and configuration method based on multiple configuration chain groups provided by the embodiment of the present invention, by adding multiple groups of configuration chain groups, each configuration chain group includes multiple configuration chain groups to store a function of different applications Bitstream configuration information, so that each group of configuration chains can store bitstream configuration information for a variety of different applications, so that in the FPGA configuration or reconfiguration process, you only need to select the corresponding multiple The configuration chain group of the same application in a configuration chain group can read the bitstream configuration information to complete the startup configuration, so that the FPGA can realize the bitstream configuration information without waiting for the external download of a new bitstream file during the reconfiguration process. The startup configuration is read out from multiple configuration chain groups in parallel, giving full play to the advantages of the FPGA's parallel configuration structure with multiple configuration chains, greatly accelerating the speed of reconfiguration and improving configuration efficiency.

Description of drawings

Fig. 1 is the configuration structure schematic diagram of the traditional FPGA provided by prior art;

Fig. 2 is a schematic flow diagram of the configuration and reconfiguration of the traditional FPGA provided by the prior art;

Fig. 3 is a schematic flow diagram of FPGA configuration and reconfiguration based on PR technology provided by the prior art;

Fig. 4 is the FPGA chip configuration structure schematic diagram based on multi-configuration chain group provided by the embodiment of the present invention;

Fig. 5 is a schematic flow chart of the configuration and reconfiguration of the FPGA provided by the embodiment of the present invention;

FIG. 6 is a flowchart of FPGA configuration and reconfiguration provided by the embodiment of the present invention.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

FIG. 4 is a schematic diagram of an FPGA chip configuration structure based on an application memory provided by an embodiment of the present invention. The chip configuration structure includes: a main controller 1, a multiplexer 2, a plurality of configuration chain groups (the configuration chain group 31, the configuration chain group 32, the configuration chain group 33 and the configuration chain group 34 are shown as examples in the figure ) and multiple demultiplexers (demultiplexer 41, demultiplexer 42, demultiplexer 43 and demultiplexer 44 are shown as examples in the figure).

The main controller 1 receives multiple sets of bit stream files sent serially from the outside, and sequentially parses the bit stream files to generate multiple sets of serial bit stream configuration information; wherein, each set of bit stream configuration information is used to realize An FPGA application;

Preferably, there will be a certain time interval between inputting each two groups of adjacent bitstream files.

The multiplexer 2 receives the configuration chain group selection signal, and sends the current set of bit stream configuration information according to the current configuration chain group selection signal;

A plurality of configuration chain groups, each configuration chain group includes a plurality of configuration chain groups; among the plurality of configuration chain groups, the set of a configuration chain group of the same application in each configuration chain group is a group of the application Configure chain groups; each group of configuration chain groups receives and stores a corresponding set of bit stream configuration information sent by the multiplexer according to the configuration chain group selection signal;

In this embodiment, FIG. 4 shows a situation specifically including a configuration chain group 31, a configuration chain group 32, a configuration chain group 33, and a configuration chain group 34. Each configuration chain group corresponds to an FPGA function, such as a global clock ( GCLK), memory (Reg.), look-up table (LUT), input/output (I/O), etc. Taking the configuration chain group 31 as an example, it stores the GCLK information in the bit stream configuration information, which is used to configure the global clock of the FPGA chip. The configuration chain group 31 includes four configuration chain groups, which are GCLK configuration chain group 1 , GCLK configuration chain group 2 , GCLK configuration chain group 3 and GCLK configuration chain group 4 . In these configuration chain groups, a set of global clock information corresponding to different FPGA applications is stored respectively. Correspondingly, a set of Reg. information, a set of LUT information, and a set of I/O information corresponding to different FPGA applications are also stored in several other configuration chain groups.

A set of configuration chain groups of the same application in different configuration chain groups becomes a group of configuration chain groups corresponding to an FPGA application; as shown in the figure, GCLK configuration chain group 1, Reg. configuration chain group 1, and LUT configuration chain group 1 and I/O configuration chain group 1 constitute a set of configuration chain groups. The configuration chain group receives and stores a set of bit stream configuration information sent by the multiplexer 2 according to the configuration chain group selection signal. The role of the bitstream configuration information may be to configure the FPGA as the application 1 .

Further specifically, each configuration chain group includes multiple configuration chains.

A plurality of demultiplexers respectively receive the configuration chain group selection signal, and obtain bit stream configuration information from a corresponding group of configuration chain groups according to the configuration chain group selection signal to start configuring the FPGA chip.

Preferably, the number of demultiplexers matches the number of configuration chain groups.

FIG. 4 shows a case where a demultiplexer 41 , a demultiplexer 42 , a demultiplexer 43 and a demultiplexer 44 are specifically included. When each of the above-mentioned demultiplexers receives the configuration chain group selection signal to obtain the bitstream configuration information that FPGA is configured as application 1, the demultiplexer 41 obtains the GCLK configuration chain group 1 from the configuration chain group 31 GCLK information stored in. Correspondingly, the demultiplexer 42 obtains the Reg. information stored in the Reg. configuration chain group 1 from the configuration chain group 31; the demultiplexer 43 obtains the Reg. Stored LUT information; the demultiplexer 44 acquires the I/O information stored in the I/O configuration chain group 1 from the configuration chain group 34 . These information are used to start the configuration of the FPGA, so that the FPGA can realize the function of application 1 after the configuration is completed.

Further, the chip configuration structure provided by this embodiment also includes a configuration chain group selection signal input port 5, and the configuration chain group selection signal sent externally is transmitted to the multiplexer through the configuration chain group selection signal input port 5 or a demultiplexer.

The working process of the FPGA chip configuration structure based on the multi-configuration chain group provided by the embodiment of the present invention will be described in detail below.

The number of configuration chain groups is determined by the number of configurable functions of the FPGA. In each configuration chain group, the number of configuration chain groups is determined by the number of application libraries supported by the system (this patent takes four functions and four applications as Example. In other specific embodiments, the number of configuration chain groups or configuration chain groups may be less or more). In this embodiment, the FPGA chip configuration structure includes: a configuration chain group selection signal input port 5 . The configuration chain group selection signal APP_ADDR[1:0] received by the configuration chain group selection signal input port 5 controls the selection of the configuration chain group in each configuration chain group.

After the FPGA chip passes the power-on detection, after the bit stream file downloaded for the first time is analyzed by the main controller 1, according to the configuration chain group selection signal APP_ADDR[1:0] received by the multiplexer 2, all Bit stream configuration information such as global clock GCLK, register Reg., lookup table LUT, I/O, etc. are all stored in the corresponding configuration chain group of "Application 1". Similarly, the bitstream configuration information downloaded for the second, third, and fourth times are respectively stored in the corresponding configuration chain groups of "Application 2", "Application 3", and "Application 4". At this time, the application library supported by the FPGA has four different applications. During the process of FPGA configuration or reconfiguration, you only need to select the configuration chain group of the corresponding application, and according to the stored configuration content, the FPGA can quickly complete the startup configuration process within a few cycles and execute the corresponding user mode. During the reconfiguration process, there is no need to wait for the download of any new bitstream file, which maximizes the reconfiguration speed of the FPGA.

After the multi-configuration chain group structure is adopted in the FPGA chip configuration structure, the configuration content stored in different configuration chain groups can be read out multiple times to configure the FPGA according to system requirements.

In addition, after the storage of multiple sets of serial bitstream configuration information is completed, the FPGA chip enters the working state; when the FPGA chip is in the working state, the configuration system supports downloading new bitstream configuration information to implement the application library supported by the configuration chain group. renew. When the multiplexer receives the configuration chain group selection signal again, the currently received set of bit stream configuration information will be written into the relatively infrequently used configuration chain group for storage according to user needs, and overwrite the original The bitstream configuration information in the configuration chain group enables the FPGA storing the bitstream configuration information to quickly perform function switching in the most commonly used applications.

Therefore, the FPGA chip configuration structure of the present invention supports downloading and parsing the bitstream files of different applications when the FPGA works normally, and stores them in corresponding configuration chain groups under the control of the configuration chain group selection signal and can update them. . This updateable mechanism can add new applications to the configuration chain group at any time, so that the FPGA can dynamically and quickly switch among multiple commonly used applications at any time, thereby enhancing the self-adaptive ability of the system.

FIG. 5 is a schematic flowchart of FPGA configuration and reconfiguration provided by an embodiment of the present invention. As can be seen from the figure, between the working hours of two different applications of the FPGA, the selection, reading and configuration time spent are greatly reduced. The required acquisition time of the bitstream configuration information is greatly shortened compared with the time required to download the bitstream file from the outside before reconfiguration in the traditional FPGA configuration structure to obtain the bitstream configuration information.

Compared with the traditional FPGA chip reconfiguration process and the FPGA chip reconfiguration process using PR technology, the FPGA chip provided by the embodiment of the present invention can greatly speed up the reconfiguration process from the following two points during the reconfiguration process: .

1. Apply the configuration structure of the FPGA chip provided by the embodiment of the present invention. In the reconfiguration process, there is no need to wait for the process of downloading a new bitstream file from the outside. It is only necessary to select the configuration chain group connection of different applications. According to the configuration chain group The stored configuration content enables the FPGA chip to quickly complete the startup configuration function in just a few clock cycles.

2. Usually, FPGA downloads the bit stream in a serial way, such as Joint Test Action Group (JTAG) download. After the bit stream file downloaded in this way is parsed by the main controller, the configuration content will enter different The configuration chain performs configuration, and multiple configuration chains cannot execute the startup configuration process at the same time, so the configuration efficiency is not high. After adopting the configuration structure of the FPGA chip provided by the embodiment of the present invention, by selecting and activating the state of all configuration chain groups of a certain application, all configuration chain groups of the application can simultaneously configure the entire FPGA chip in parallel, thereby maximizing configuration efficiency.

Correspondingly, the embodiment of the present invention also provides a method for configuring the FPGA chip configuration structure based on the application memory provided in the above embodiments. As shown in Figure 6, the method includes the following steps:

Step 610, the main controller receives multiple sets of bit stream files sent serially from the outside, and sequentially parses the bit stream files to generate serial multiple sets of bit stream configuration information;

Wherein, each group of bit stream configuration information is used to realize an application;

Step 620, the multiplexer receives the configuration chain group selection signal, and sends the current group of bit stream configuration information according to the current configuration chain group selection signal;

Step 630, each group of configuration chain groups receives and stores a corresponding set of bit stream configuration information sent by the multiplexer according to the configuration chain group selection signal; wherein the group of configuration chain groups is: a plurality of In the configuration chain group, a set of configuration chain groups of the same application in each configuration chain group;

Step 640: The demultiplexer receives the configuration chain group selection signal, and obtains bitstream configuration information from a corresponding group of configuration chain groups according to the configuration chain group selection signal to start configuration of the FPGA chip.

In addition, after the storage of multiple sets of serial bitstream configuration information is completed, the FPGA chip enters the working state; when the FPGA chip is in the working state, the configuration system supports downloading new bitstream configuration information to implement the application library supported by the configuration chain group. renew. When the multiplexer receives the configuration chain group selection signal again, the currently received set of bit stream configuration information will be written into the relatively infrequently used configuration chain group for storage according to user needs, and overwrite the original The bitstream configuration information in the configuration chain group enables the FPGA storing the bitstream configuration information to quickly perform function switching in the most commonly used applications.

The configuration method provided in this embodiment is used to configure the FPGA chip configuration structure based on the application memory provided in the above embodiments. The specific configuration process has been described in detail in the foregoing embodiments, and will not be repeated here.

Professionals should further realize that the units and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the relationship between hardware and software Interchangeability. In the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (3)

1. a kind of fpga chip configuration structure based on multi-configuration chain group, which is characterized in that the structure includes：

Master controller receives multigroup bit stream file that external series are sent, and the bit stream file is parsed successively, The serial multigroup bit stream configuration information of generation；Wherein, each group of bit stream configuration information is realizing a kind of application；It is inputting Between every two groups adjacent bit stream files between meeting at regular intervals；

Multiplexer receives configuration chain group selection signal, will work as previous group bit according to current configuration chain group selection signal Stream configuration information is sent；

Multiple configuration chain groups, each chain group that configures include multiple configuration chain groups；In the multiple configuration chain group, chain is each configured The collection of a configuration chain group of identical application is combined into one group of configuration chain group of the application in group；Each group of configuration chain is small Group receives and stores corresponding one group of bit stream configuration that the multiplexer is sent according to the configuration chain group selection signal Information；Each configuration chain group includes multiple configuration chains；

Multiple demultiplexer receive the configuration chain group selection signal respectively, and according to the configuration chain group selection signal Configuration of the bit stream configuration information startup to fpga chip is obtained from corresponding one group of configuration chain group；

The each group of bit stream configuration information includes multiple functional configuration information, and each configuration chain group receives and stores The corresponding functional configuration information that the multiplexer is sent according to the configuration chain group selection signal；

The number of the demultiplexer and the number of the configuration chain group match；

Each demultiplexer selects corresponding configuration chain small according to configuration chain group selection signal from matched configuration chain group Group obtains the configuration that bit stream configuration information starts fpga chip；

After the completion of serial multigroup bit stream configuration information stores in multiple configuration chain groups, fpga chip enters work shape State；It is in running order in the fpga chip, and when the multiplexer is received again by configuration chain group selection signal and ratio During special stream configuration information, the multiplexer is by be currently received one group of bit stream configuration information according to configuration chain group selection letter It number is sent to corresponding configuration chain group to be stored, and covers the bit stream configuration letter formerly stored in the configuration chain group Breath.

2. chip configuration structure according to claim 1, which is characterized in that the structure further includes configuration chain group selection letter Number input port, the configuration chain group selection signal that outside is sent are sent to institute by the configuration chain group selection signal input port State multiplexer or demultiplexer.

3. a kind of collocation method of the fpga chip configuration structure based on multi-configuration chain group, which is characterized in that the described method includes：

Master controller receives multigroup bit stream file that external series are sent, and the bit stream file is parsed successively, The serial multigroup bit stream configuration information of generation；Wherein, each group of bit stream configuration information is realizing a kind of application；It is inputting Between every two groups adjacent bit stream files between meeting at regular intervals；

Multiplexer receives configuration chain group selection signal, will work as previous group bit stream according to current configuration chain group selection signal Configuration information is sent；

Each group of configuration chain group receives and stores the phase that the multiplexer is sent according to the configuration chain group selection signal The one group of bit stream configuration information answered；Wherein described one group of configuration chain group is：It is each to configure in chain group in multiple configuration chain groups The set of one configuration chain group of identical application；Wherein, each configuration chain group includes multiple configuration chains；

Demultiplexer receives the configuration chain group selection signal, and according to the chain group selection signal that configures from corresponding one The configuration that bit stream configuration information starts fpga chip is obtained in group configuration chain group；

The each group of bit stream configuration information includes multiple functional configuration information；

The number of the demultiplexer and the number of the configuration chain group match；

After the completion of serial multigroup bit stream configuration information stores in multiple configuration chain groups, fpga chip enters work shape State；It is in running order in the fpga chip, and when the multiplexer is received again by configuration chain group selection signal and ratio During special stream configuration information, the multiplexer is by be currently received one group of bit stream configuration information according to configuration chain group selection letter It number is sent to corresponding configuration chain group to be stored, and covers the bit stream configuration letter formerly stored in the configuration chain group Breath.