CN104618821B - Space satellite communication multiplexing method based on FPGA - Google Patents

Abstract

The invention discloses an FPGA-based space satellite communication multiplexing method. The specific implementation process is as follows: first, a computer local area network and an IP telephone local area network sharing the same multiplexer are set; an image encoder and an image decoder are respectively connected to two independent The multiplexer in the computer local area network and IP telephone LAN; the image signal enters the image encoder, and the image encoder encodes the image signal into four E1 signals, and then sends it to the multiplexer; After receiving the four-way E1 signal tapped by the splitter, the image is decoded, and then sent to the display device to display the image. Compared with the existing technology, this FPGA-based space satellite communication multiplexing method realizes laser space transmission by receiving and sending signals through laser, with fast transmission rate, large amount of information, and wide coverage space; strong practicability and easy promotion .

Description

An FPGA-based space satellite communication multiplexing method

technical field

The invention relates to the technical field of data multiplexing, in particular to an FPGA-based space satellite communication multiplexing method with strong practicability.

Background technique

The development of the information age requires the establishment of a communication network system with fast transmission rate, large amount of information, and wide coverage space. The use of light waves with extremely short wavelengths for space satellite communication is the best solution to achieve high bit rate communication, and is even considered the only means, especially in today's increasingly crowded space satellites, which has been achieved by many experts and scholars in the field of communication consensus. In order to make full use of the advantages of space laser communication, the mature digital multiplexing technology can be used to serve space laser communication. If the digital multiplexing technology can be used to perform multiplexing before the electrical signal enters the laser modulation part, it is obvious that the capacity of the laser channel can be fully used.

The application of digital multiplexing technology first started from the relay transmission of local calls. At that time, in order to adapt to the flexible multiplexing of non-synchronous branches, the quasi-synchronous low-speed branch signals were multiplexed into high-speed code streams by using the plug-in pulse technology. At the beginning, the transmission medium was cable. Due to the shortage of frequency band resources, it mainly focused on controlling the jitter and saving auxiliary bit overhead. According to the technical history of the country/region, a quasi-synchronous series with three different rate structures in the United States, Japan, and Europe was formed. (PDH). These three asynchronous multiplexing systems are incompatible with each other, difficult to intercommunicate, and the PDH multiplexing structure is complex, so although it can well adapt to traditional point-to-point channels, it cannot adapt to the requirements of dynamic networking, and it is difficult to support new Business development and modern network management cannot support Broadband Integrated Services Digital Network (B-ISDN).

In order to adapt to the rapid development of the telecommunication network and meet the increasing requirements for networking, based on the considerations of network operation flexibility, reliability, convenience and effectiveness of maintenance and management, and adaptability to future development, as well as PDH A series of shortcomings, SDH appeared.

The SDH system was proposed by TIU-T on the basis of the US Synchronous Optical Network (SONET) system. SONET was first proposed by the Bell Communications Research Institute in the United States. The original purpose of formulating the SONET standard was to prevent the proliferation of incompatible optical interfaces, realize standard optical interfaces, and facilitate the intercommunication of equipment from various manufacturers on the optical path. But the subsequent development has greatly exceeded this initial goal. SONET has expanded into a new transmission network system, which is suitable for both optical fiber channels and general counting systems for channels such as microwaves and satellites. SDH stipulates the interface standard for effectively multiplexing various high-speed services and original low-speed services.

Of course, as a new technical system, it is impossible to be perfect, and there are still some shortcomings in the synchronous digital series. For example, the frequency band utilization rate is not as high as the traditional quasi-synchronous system; the so-called pointer adjustment count is used, which increases the complexity of the equipment; at the same time, the boundary jitter is difficult to meet the network performance requirements. In addition, the synchronous network system is controlled by a complete set of software. If there is a problem with the software, it is likely to cause the entire network to be paralyzed. Therefore, stable and reliable software is required.

Because the synchronous network is introduced in the quasi-synchronous network environment, it involves the intercommunication of quasi-synchronous and synchronous series. For quite a long period of time in the future, there will be both synchronous series and quasi-synchronous series in the telecommunication network. In the near future, the world's telecommunications will be unified in the synchronous digital network.

Today's society is a digital society and a society where digital integrated circuits are widely used. However, in the previous PDH multiplexing circuit, many parts of the system used analog circuits, so there were great limitations. Now, digital integrated circuits have been updated, and system designers are more willing to design application-specific integrated circuit (ASIC) chips themselves, and hope that the ASIC design cycle is as short as possible. It is best to design a suitable ASIC chip in the laboratory. And it was immediately put into practical application, so the field logic programmable logic device (FPGA) was launched, and the most widely used ones were field logic gate array (FPGA) and complex programmable logic device (CPLD).

Based on the above technology, an FPGA-based space satellite communication multiplexing method is now provided.

Contents of the invention

The technical task of the present invention is to provide a highly practical FPGA-based space satellite communication multiplexing method for the above deficiencies.

An FPGA-based space satellite communication multiplexing method, its specific implementation process is:

First set the computer local area network and the IP telephone local area network sharing the same multiplexer, the computer local area network includes computers, Internet phones, and the computers and Internet phones are all connected to the multiplexer through the HUB interface; the IP telephone local area network includes the IP phone directly connected to the multiplexer Telephone, the multiplexer is also connected with RS232 interface;

The image encoder and the image decoder are respectively connected to two sets of multiplexers in the independent computer local area network and IP telephone local area network to form two sets of digital multiplexing systems. The multiplexers of the two sets of digital multiplexing systems are connected through laser communication. Wherein the image encoder is connected to an image source, and the image source includes DVD and CCD; the image decoder is connected to a display device, and the display device includes a TV set;

The image signal enters the image encoder, which encodes the image signal into four E1 signals, and then sends it to the multiplexer;

The image decoder decodes the image after receiving the four E1 signals tapped from the multiplexer, and then sends it to the display device to display the image.

The laser communication of the two sets of digital multiplexing systems refers to setting a laser communicator with a transmitting antenna on one set of multiplexers, and setting a laser communicator with a receiving antenna on the other set of multiplexers.

The transmission code rate adopted by the digital multiplexing system is 33.792M, and a total of 16 time sequences are used, and the capacity of each time sequence is 2.112M.

Described digital multiplexing system completes telephone interface multiplexing, serial data multiplexing, Ethernet data multiplexing, E1 signal multiplexing, wherein

The multiplexing process of the telephone interface is: use the standard clock clk2048k to generate a narrow pulse narrowclk as an analog sampling mark to obtain an eight-digit digital signal; pass through the shift register SM module, cache it, and wait for the fourth timing to be sent out;

Serial port data multiplexing is realized by asynchronous multiplexing method. The multiplexing process is as follows: first, sampling is performed at the rising edge of the clock 2.112M, and after two consecutive beats, it is sent to a 16-bit shift register. Convert to 2.112M clock synchronization data;

The multiplexing process of the E1 signal is as follows: firstly, the bit synchronization is extracted; the code rate is adjusted by using a positive code rate, and pulses are inserted, so that the code rate of each base group is adjusted from 2048kb/s to 2112kb/s. The main body of the adjustment device is a buffer memory. When the number of information bits in the buffer memory drops to a specified number, a control signal is sent, and the control gate is closed at this time, and one bit is deducted from the readout clock; since there is no readout clock, the information in the buffer register The information cannot be read out, and at this time the information is still stored in the buffer register, so the information in the buffer register is increased by one bit; so repeated, the digital stream is sent out through the buffer memory.

A kind of FPGA-based space satellite communication multiplexing method of the present invention has the following advantages:

An FPGA-based space satellite communication multiplexing method of this invention uses an Ethernet interface, a serial port based on RS232, a telephone subscriber line interface, and an E1 interface, and externally completes the space satellite through a laser modulation drive circuit and a receiving demodulation circuit. Communication, through laser receiving and sending signals, realizes the space transmission of laser, with fast transmission rate, large amount of information, and wide coverage space; strong practicability and easy promotion.

Description of drawings

Accompanying drawing 1 is the overall structural block diagram of the present invention.

Accompanying drawing 2 is a schematic block diagram of the FPGA multiplexing system.

Accompanying drawing 3 is the sequence diagram of telephone interface.

Accompanying drawing 4 is the clock that FPGA sends to RJ017 and the data graph of RJ017.

Accompanying drawing 5 is the bit synchronization diagram of HDB3.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

An FPGA-based space satellite communication multiplexing method, as shown in Figure 1, its specific implementation process is:

First set the computer local area network and the IP telephone local area network sharing the same multiplexer, the computer local area network includes computers, Internet phones, and the computers and Internet phones are all connected to the multiplexer through the HUB interface; the IP telephone local area network includes the IP phone directly connected to the multiplexer Telephone, the multiplexer is also connected with RS232 interface;

The image encoder and the image decoder are respectively connected to two sets of multiplexers in the independent computer local area network and IP telephone local area network to form two sets of digital multiplexing systems. The multiplexers of the two sets of digital multiplexing systems are connected through laser communication. Wherein the image encoder is connected to an image source, and the image source includes DVD and CCD; the image decoder is connected to a display device, and the display device includes a TV set, and the whole digital multiplexing system is externally connected to a laser modulation drive circuit and a receiving demodulation circuit;

The image signal enters the image encoder, which encodes the image signal into four E1 signals, and then sends it to the multiplexer;

The image decoder decodes the image after receiving the four E1 signals tapped from the multiplexer, and then sends it to the display device to display the image.

In the above steps, the present invention uses the existing digital multiplexing technology to serve the spatial optical communication. Its multiplexed channel is no longer an optical cable, but a wireless laser. The overall block diagram of the system is shown in Figure 1, in which V200D is an image encoder and V200E is an image decoder. V200D encodes the image signal into four channels of E1 signals, and then sends them to the multiplexer. V200E decodes the image after receiving the four-way E1 signal tapped from the multiplexer, and then sends it to the TV to display the image. The multiplexer connects the two LANs, and the computer and IP phone communicate through the LAN. In this way, the multiplexer realizes the remote laser communication between the IP phone and the computer. The business phone and RS-232 signals are multiplexed with other signals through the multiplexer, thus realizing the respective duplex communication of the business phone and RS-232. After the two multiplexers undergo photoelectric conversion, the laser is used as the communication carrier. The laser transmitting antenna emits laser light, and the laser receiving antenna receives the laser signal, thus realizing the spatial transmission of the laser light.

The laser communication of the two sets of digital multiplexing systems refers to setting a laser communicator with a transmitting antenna on one set of multiplexers, and setting a laser communicator with a receiving antenna on the other set of multiplexers.

The transmission code rate adopted by the digital multiplexing system is 33.792M, and a total of 16 time sequences are used, and the capacity of each time sequence is 2.112M.

Described digital multiplexing system completes telephone interface multiplexing, serial data multiplexing, Ethernet data multiplexing, E1 signal multiplexing, wherein

The multiplexing process of the telephone interface is as follows: As shown in Figure 3, use the standard clock clk2048k (the actual frequency is 2.112M) to generate a narrow pulse narrowclk as an analog sampling mark to obtain an eight-bit digital signal. After the shift register SM module is shown in Figure 2, it is cached and waits for the fourth timing to be sent out. The capacity of a telephone signal is 8K, and a time slot can transmit a capacity of 2M. Such a time slot can transmit 32 telephone calls.

The multiplexing process of the serial port data is as follows: the present invention selects the asynchronous multiplexing method to multiplex the serial port signals. In order to send the serial port data to the FPGA, it is first sampled at the rising edge of the clock 2.112M, and after two consecutive beats, it is sent to a 16-bit shift register. After asynchronous sampling, it is directly converted into 2.112M clock synchronous data, occupying one time slot.

The multiplexing process of Ethernet data is as follows: the network interface circuit is mainly composed of TP module and chip RJ017 composed of RJ45 interface and a coupling transformer. The RJ017 (ChipBridge) produced by Israel's RAD Company is a high-performance application-specific integrated circuit chip that can complete the remote bridge function with a single chip and is compatible with the IEEE802.3 protocol. The timing is shown in Figure 4, as long as the 8.448M clock with the same source as the standard clock is sent to the RJ017, the sent data can be obtained.

The embodiment of the present invention adopts a network transmission rate of 8 megabytes. Since one time slot can only transmit 2 megabytes during transmission in this design, it needs to take up 4 time slots for transmission. Finally, it is sent into a 4-bit serial-to-parallel converted buffer area and waits to be retrieved. Walk.

The multiplexing process of the E1 signal is as follows: First, the bit synchronization is extracted. As shown in Figure 5, the E1 signal is transmitted using the HDB3 encoding method, and after decoding, it becomes a zero-returning unipolar code. Although it has synchronization information, considering the complexity and inconvenience of the filtering method, the digital phase-locked loop method is still used to extract bit synchronization.

The code rate of the E1 signal is the same as the nominal value of the multiplex clock 2.048M, but there is a certain deviation in fact, and the code rate must be adjusted. The present invention adopts positive code rate adjustment mode to adjust. By inserting pulses, the digital rate of each base group is adjusted from 2048kb/s to 2112kb/s. Once the clock adjustment is complete, one of the 16 time slots is occupied for transmission. The main body of the code rate adjustment device is the buffer memory, and also includes some necessary control circuits, the digital rate of the input branch =2.048Mbit/s±100bit/s, output digital rate =2.112Mbit/s. The so-called positive code speed adjustment is because And got its name.

Assuming that the information in the buffer is originally in a half-full state, as time goes by, due to the read clock greater than the write clock , the information in the buffer is bound to be less and less, if no special measures are taken, the information in the buffer will eventually be taken out, and the information read out will be false information. In order to prevent the information in the buffer from being emptied, some measures need to be taken. Once the number of information bits in the buffer drops to a specified number, a control signal is issued, at this time the control gate is closed, and one bit is deducted from the readout clock. Since there is no read clock, the information in the buffer cannot be read out, and at this time the information is still stored in the buffer, so the information in the buffer increases by one bit. Repeating this way, the digital stream can be sent out through the buffer memory.

The above-mentioned specific embodiment is only a specific case of the present invention, and the scope of patent protection of the present invention includes but is not limited to the above-mentioned specific embodiment, any claim of a kind of FPGA-based space satellite communication multiplexing method of the present invention and any Appropriate changes or substitutions made by persons of ordinary skill in the technical field shall fall within the patent protection scope of the present invention.

Claims (4)

1. a kind of Aerospace Satellite communication multiplexing method based on FPGA, it is characterised in that it implements process and is：

The LAN and official telephone LAN for sharing same multiplexer are set first, and the LAN includes Computer, IP phone, the computer, IP phone connect multiplexer by HUB interfaces；Official telephone LAN includes directly connecting The official telephone of multiplexer is connect, the multiplexer is also associated with RS232 interfaces；

Respectively by image encoder, image decoder connection two groups of LANs and official telephone LAN of independence Multiplexer, so as to form two groups of Digital Multiplex Systems, two groups of multiplexers of Digital Multiplex System are connected by laser communication, wherein Image encoder connects image source, and the image source includes DVD, CCD；Image decoder connects display device, the display device bag Include television set；

Picture signal enters image encoder, and the image encoder will be changed into four road E1 signals after image signal encoding, then send In entering multiplexer；

Image decoder is then passed to display device to carrying out image decoding from after the road E1 signal receptions of multiplexer tap Chu tetra- Carry out display image.

2. it is according to claim 1 it is a kind of based on FPGA Aerospace Satellite communication multiplexing method, it is characterised in that described two The laser communication of group Digital Multiplex System refers to that the laser communication device with transmitting antenna is set on one group of multiplexer, and another group is answered Connect and the laser communication device with reception antenna is set on device.

3. it is according to claim 1 it is a kind of based on FPGA Aerospace Satellite communication multiplexing method, it is characterised in that the number The transmission code rate that word redundant system is used is 33.792M, and altogether using 16 sequential, the capacity of each sequential is 2.112M.

4. it is according to claim 3 it is a kind of based on FPGA Aerospace Satellite communication multiplexing method, it is characterised in that the number Word redundant system completes telephony interface multiple connection, serial data multiple connection, Ethernet data multiple connection, E1 signal multiplexings, wherein

Telephony interface multiple connection process is：A burst pulse narrowclk is produced as analog sampling with standard time clock clk2048k Mark, obtains eight-digit number word signal；By shift register SM modules, it is cached, waits the 4th sequential to send out；

Serial data multiple connection realizes that its multiple connection process is using asynchronous multiplexing method：Carried out in clock 2.112M rising edges first Sampling, the shift register of feeding one 16, by after asynchronous-sampling, being converted directly into 2.112M clock synchronization datas；

The multiple connection process of E1 signals is：First have to carry out the extraction of bit synchronization；Justification is carried out using code speed, arteries and veins is inserted Punching, makes the numeric code rate of each basic group be adjusted to 2112kb/s by 2048kb/s, and the main body of the code quick adjusting device is deposited for buffering Reservoir, when the information bit in buffer storage drops to specified quantity, sends control signal, at this moment controls door to close, and reads Go out clock and deducted a bit；Due to being not read out clock, the information in buffer register cannot read, and at this moment believe Breath is still stored in toward buffer register, therefore information in buffer register is increased by a bit；So repeat down, by number Stream is sent out by buffer storage.