CN104600120B - A kind of p-type rf-ldmos semiconductor devices - Google Patents
A kind of p-type rf-ldmos semiconductor devices Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 19
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 28
- 230000015556 catabolic process Effects 0.000 description 9
- 239000012212 insulator Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000005481 NMR spectroscopy Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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- H10D64/00—Electrodes of devices having potential barriers
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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Abstract
一种P型射频横向双扩散金属氧化物半导体器件，包括：N型衬底、N型外延层，在N型外延层中形成有P型轻掺杂漏区和N阱，N阱的一侧和所述P型轻掺杂漏区的一侧相接触；在所述P型轻掺杂漏区中形成有P型重掺杂漏区；在所述N阱中形成有P型重掺杂源区，在N阱的另一侧形成有N型重掺杂引出区，N型重掺杂引出区穿过N型外延层与N型硅衬底相接触；在N阱上形成有栅氧化层，且栅氧化层的两个边界分别位于P型重掺杂源区及P型轻掺杂漏区的边界上方；在N型重掺杂引出区和P型重掺杂源区上连接有源极金属，在P型重掺杂漏区上连接有漏极金属，其特征在于，所述栅氧化层为阶梯状，在栅氧化层的下方设有P型掺杂区且所述P型掺杂区位于N阱中。
A P-type radio frequency lateral double-diffused metal oxide semiconductor device, comprising: an N-type substrate, an N-type epitaxial layer, a P-type lightly doped drain region and an N well are formed in the N-type epitaxial layer, and one side of the N well It is in contact with one side of the P-type lightly doped drain region; a P-type heavily doped drain region is formed in the P-type lightly doped drain region; a P-type heavily doped drain region is formed in the N well In the source region, an N-type heavily doped lead-out region is formed on the other side of the N well, and the N-type heavily doped lead-out region passes through the N-type epitaxial layer and contacts the N-type silicon substrate; a gate oxide region is formed on the N well layer, and the two boundaries of the gate oxide layer are located above the boundaries of the P-type heavily doped source region and the P-type lightly doped drain region; the N-type heavily doped lead-out region and the P-type heavily doped source region are connected with The source metal is connected to the P-type heavily doped drain region. The drain metal is characterized in that the gate oxide layer is stepped, and a P-type doped region is provided under the gate oxide layer, and the P-type The doped region is located in the N well.
Description
技术领域technical field
本发明主要涉及一种半导体器件，特别是涉及一种应用于射频领域的P型横向双扩散金属氧化物半导体器件。The invention mainly relates to a semiconductor device, in particular to a P-type lateral double-diffused metal oxide semiconductor device applied in the field of radio frequency.
背景技术Background technique
射频功率器件主要应用于无线通讯中移动通信系统基站的射频功率放大器。然而由于CMOS射频功率性能的不足，在射频功率半导体市场上，直到上世纪90年代中期，射频功率器件还都是使用双极型晶体管或GaAs MOSFET。直到90年代后期，硅基横向扩散金属氧化物半导体晶体管LDMOS的出现改变了这一状况。射频横向双扩散金属氧化物半导体(RFLDMOS)器件是半导体集成电路技术与微波电子技术融合入而成的新一代集成化的固体微波功率半导体产品，具有线性度好、增益高、耐压高、输出功率大、热稳定性好、效率高、宽带匹配性能好、易于和MOS工艺集成等优点，并且其价格远低于砷化镓器件，是一种非常具有竞争力的功率器件，被广泛应用于GSM、PCS、W-CDMA基站的功率放大器，以及无线广播与核磁共振等方面。RF power devices are mainly used in RF power amplifiers of mobile communication system base stations in wireless communications. However, due to the lack of CMOS RF power performance, in the RF power semiconductor market, until the mid-1990s, RF power devices still used bipolar transistors or GaAs MOSFETs. Until the late 1990s, the emergence of silicon-based laterally diffused metal oxide semiconductor transistor LDMOS changed this situation. Radio Frequency Lateral Double Diffused Metal Oxide Semiconductor (RFLDMOS) device is a new generation of integrated solid-state microwave power semiconductor products that integrate semiconductor integrated circuit technology and microwave electronic technology. It has good linearity, high gain, high withstand voltage, and output It has the advantages of high power, good thermal stability, high efficiency, good broadband matching performance, and easy integration with MOS technology, and its price is much lower than that of gallium arsenide devices. It is a very competitive power device and is widely used in Power amplifiers for GSM, PCS, and W-CDMA base stations, as well as wireless broadcasting and nuclear magnetic resonance.
射频横向双扩散金属氧化物半导体器件在漏极和沟道之间引入的低掺杂漂移区，提高了器件的击穿电压，减小了源漏极之间的寄生电容，提高了器件的频率特性。通过调整低掺杂漏区的长度和掺杂浓度，可以调整器件的导通电阻和击穿电压。P型射频横向双扩散金属氧化物半导体器件的N型重掺杂引出区实现了源极和衬底的连接，以降低射频应用时的源极的接线电感，增大共源放大器的射频增益，提高器件的性能。The low-doped drift region introduced between the drain and the channel of the radio frequency lateral double-diffused metal oxide semiconductor device improves the breakdown voltage of the device, reduces the parasitic capacitance between the source and drain, and increases the frequency of the device characteristic. By adjusting the length and doping concentration of the low-doped drain region, the on-resistance and breakdown voltage of the device can be adjusted. The N-type heavily doped lead-out region of the P-type radio frequency lateral double-diffused metal oxide semiconductor device realizes the connection between the source and the substrate, so as to reduce the wiring inductance of the source in radio frequency applications and increase the radio frequency gain of the common source amplifier. improve device performance.
在射频横向双扩散金属氧化物半导体器件的设计过程中，除了要求较小的导通电阻和大的击穿电压外，还要求较小的寄生电容，包括栅源寄生电容、栅漏寄生电容和源漏寄生电容。对于击穿电压和导通电阻一定的射频横向双扩散金属氧化物半导体器件来说，栅源寄生电容和栅漏寄生电容的大小在一定程度上决定了截止频率的大小，栅源寄生电容和栅漏寄生电容越大，器件的截止频率就越小。另外，源漏寄生电容对器件的输出功率、功率增益和效率有很大影响，减小源漏寄生电容可以提高器件的输出功率、功率增益和效率。因此减小器件的寄生电容对提高射频器件电学性能具有重要意义。In the design process of radio frequency lateral double-diffused metal oxide semiconductor devices, in addition to requiring small on-resistance and large breakdown voltage, small parasitic capacitances are also required, including gate-source parasitic capacitance, gate-drain parasitic capacitance and Source-drain parasitic capacitance. For RF lateral double-diffused metal oxide semiconductor devices with a certain breakdown voltage and on-resistance, the gate-source parasitic capacitance and gate-drain parasitic capacitance determine the cut-off frequency to a certain extent, and the gate-source parasitic capacitance and gate The larger the drain parasitic capacitance, the smaller the cutoff frequency of the device. In addition, the source-drain parasitic capacitance has a great influence on the output power, power gain and efficiency of the device, and reducing the source-drain parasitic capacitance can improve the output power, power gain and efficiency of the device. Therefore, reducing the parasitic capacitance of the device is of great significance to improving the electrical performance of the radio frequency device.
发明内容Contents of the invention
本发明提供了一种能够提高截止频率且同时又能保证阈值电压不降低的P型射频横向双扩散金属氧化物半导体器件。The invention provides a P-type radio-frequency lateral double-diffused metal oxide semiconductor device capable of increasing the cut-off frequency while ensuring that the threshold voltage does not decrease.
本发明采用如下技术方案：一种P型射频横向双扩散金属氧化物半导体器件，包括：N型衬底，在N型硅衬底上形成有N型外延层；在N型外延层中形成有P型轻掺杂漏区和N阱，且N阱在所述P型轻掺杂漏区的一侧，N阱的一侧和所述P型轻掺杂漏区的一侧相接触，在所述P型轻掺杂漏区中形成有第一P型重掺杂漏区；在所述N阱中形成有第二P型重掺杂源区，在N阱的另一侧形成有N型重掺杂引出区，N型重掺杂引出区与P型重掺杂源区和N阱相接触，并穿过N型外延层与N型硅衬底相接触；在N阱上形成有栅氧化层，且栅氧化层的两个边界分别位于P型重掺杂源区的边界及P型轻掺杂漏区的边界上方，在栅氧化层的表面形成有多晶硅栅；在N型重掺杂引出区和P型重掺杂源区上连接有源极金属，在P型重掺杂漏区上连接有漏极金属，源极金属和漏极金属分别通过场氧与多晶硅栅相隔离，其特征在于，所述栅氧化层为阶梯状，在栅氧化层的下方设有P型掺杂区且所述P型掺杂区位于N阱中。The present invention adopts the following technical scheme: a P-type radio frequency lateral double-diffused metal oxide semiconductor device, comprising: an N-type substrate, an N-type epitaxial layer is formed on the N-type silicon substrate; The P-type lightly doped drain region and the N well, and the N well is on one side of the P-type lightly doped drain region, and one side of the N well is in contact with one side of the P-type lightly doped drain region. A first P-type heavily doped drain region is formed in the P-type lightly doped drain region; a second P-type heavily doped source region is formed in the N well, and a N well is formed on the other side of the N well. Type heavily doped lead-out region, the N-type heavily doped lead-out region is in contact with the P-type heavily doped source region and the N well, and is in contact with the N-type silicon substrate through the N-type epitaxial layer; The gate oxide layer, and the two boundaries of the gate oxide layer are respectively located above the boundary of the P-type heavily doped source region and the boundary of the P-type lightly doped drain region, and a polysilicon gate is formed on the surface of the gate oxide layer; The source metal is connected to the doped lead-out region and the P-type heavily doped source region, and the drain metal is connected to the P-type heavily doped drain region. The source metal and the drain metal are respectively isolated from the polysilicon gate by field oxygen. , characterized in that the gate oxide layer is stepped, a P-type doped region is provided under the gate oxide layer, and the P-type doped region is located in an N well.
与现有技术相比，本发明具有如下优点：Compared with prior art, the present invention has following advantage:
(1)、本发明组合使用阶梯状栅氧化层8和P型掺杂区13，解决了单独采用阶梯栅氧、P型掺杂区以及非阶梯方式增厚的栅氧与P型掺杂区组合所带来的问题，使得器件的栅源寄生电容和栅漏寄生电容得以减小、截止频率得以提高，同时又能保证阈值电压的不降低。(1), the present invention uses the stepped gate oxide layer 8 and the P-type doped region 13 in combination to solve the problem of using the step gate oxide alone, the P-type doped region and the thickened gate oxide and P-type doped region in a non-step manner The problems brought about by the combination make the gate-source parasitic capacitance and gate-drain parasitic capacitance of the device be reduced, the cut-off frequency is improved, and the threshold voltage is not lowered at the same time.
阶梯状栅氧化层8和P型掺杂区13存在的好处在于器件的截止频率得到了提高。截止频率作为射频横向双扩散金属氧化物半导体器件的一个重要参数，一般通过减小栅源寄生电容和栅漏寄生电容来提高其大小。栅源寄生电容和栅漏寄生电容均为金属-绝缘体-半导体电容，该电容为绝缘体电容和半导体耗尽区电容的并联，要想减小该电容一般从两方面入手：一是增大栅氧厚度，从而减小绝缘体电容；二是增大半导体耗尽的宽度。P型掺杂区13的存在辅助了N阱区4向N型外延层2和P型轻掺杂区3的耗尽，使得耗尽区面积增大，这样半导体耗尽区电容得到了减小，因此减小了栅源寄生电容和栅漏寄生电容。The advantage of the stepped gate oxide layer 8 and the P-type doped region 13 is that the cut-off frequency of the device is improved. As an important parameter of radio frequency lateral double-diffused metal-oxide-semiconductor devices, the cutoff frequency is generally increased by reducing the gate-source parasitic capacitance and the gate-drain parasitic capacitance. Both the gate-source parasitic capacitance and the gate-drain parasitic capacitance are metal-insulator-semiconductor capacitances. This capacitance is a parallel connection of the insulator capacitance and the semiconductor depletion region capacitance. To reduce this capacitance, there are generally two ways to start: one is to increase the gate oxide Thickness, thereby reducing the capacitance of the insulator; the second is to increase the width of semiconductor depletion. The existence of the P-type doped region 13 assists the depletion of the N well region 4 to the N-type epitaxial layer 2 and the P-type lightly doped region 3, so that the area of the depletion region is increased, and the capacitance of the semiconductor depletion region is reduced like this , thus reducing the gate-to-source parasitic capacitance and the gate-to-drain parasitic capacitance.
但是，P型掺杂区13的引入会缩短沟道长度，显著减小阈值电压，为了不影响器件的导通特性，保持器件的沟道长度不变，只有增加栅极覆盖N阱4的长度，这样势必会带来绝缘体电容的增加。阶梯状栅氧化层8通过增加覆盖N阱4中P型掺杂区13上方的栅氧厚度，且由于P型掺杂区13的存在，其上方的栅氧厚度可以做到很厚，这样就完全抑制了由于P型掺杂区13的引入所带来的绝缘体电容的增大。However, the introduction of the P-type doped region 13 will shorten the channel length and significantly reduce the threshold voltage. In order not to affect the conduction characteristics of the device, keep the channel length of the device unchanged, and only increase the length of the gate covering the N well 4 , which will inevitably lead to an increase in the capacitance of the insulator. The stepped gate oxide layer 8 increases the thickness of the gate oxide covering the top of the P-type doped region 13 in the N well 4, and due to the existence of the P-type doped region 13, the thickness of the gate oxide above it can be made very thick, so that The increase of the capacitance of the insulator due to the introduction of the P-type doped region 13 is completely suppressed.
(2)、附图3、附图4和附图5分别为本发明器件与常规器件结构的截止频率、栅源寄生电容和栅漏寄生电容的对比图，可以发现本发明器件与常规器件相比，由于栅源寄生电容和栅漏寄生电容明显减小了，因此器件的频率特性得到了改善。(2), accompanying drawing 3, accompanying drawing 4 and accompanying drawing 5 are respectively the cut-off frequency of the device of the present invention and conventional device structure, gate-source parasitic capacitance and gate-drain parasitic capacitance contrast figure, can find that the device of the present invention and conventional device Compared with that, since the gate-source parasitic capacitance and the gate-drain parasitic capacitance are significantly reduced, the frequency characteristics of the device are improved.
(3)、本发明的好处在于P型掺杂区13的存在还在一定程度上减小了栅极电阻。由优点(1)所述，引入P型掺杂区13之后，为了不改变器件的阈值电压，只有保证器件的沟道长度不发生变化，因此只有增加栅极覆盖N阱4的长度，这样器件的栅极面积就增大了，从而栅极电阻得到了减小。在射频领域，栅极电阻的减小，可以提高器件的最高震荡频率和功率增益。(3) The advantage of the present invention is that the existence of the P-type doped region 13 also reduces the gate resistance to a certain extent. Described by advantage (1), after introducing the P-type doped region 13, in order not to change the threshold voltage of the device, only the channel length of the device is guaranteed not to change, so only the length of the gate covering the N well 4 is increased, so that the device The gate area is increased, thereby reducing the gate resistance. In the radio frequency field, the reduction of gate resistance can improve the highest oscillation frequency and power gain of the device.
(4)、本发明器件的好处在于提高了器件的频率特性，减小了栅极电阻的基础上，击穿电压基本保持不变。附图6为本发明器件与常规器件的击穿电压对比图，可以发现本发明器件与常规器件相比，器件的击穿电压基本保持不变。(4) The advantage of the device of the present invention is that the frequency characteristic of the device is improved, and the breakdown voltage remains basically unchanged on the basis of reducing the grid resistance. Accompanying drawing 6 is the comparison diagram of the breakdown voltage of the device of the present invention and the conventional device, it can be found that the breakdown voltage of the device of the present invention remains basically unchanged compared with the conventional device.
(5)、本发明器件的好处在于提高了器件的频率特性，减小了栅极电阻的基础上，器件的开态导通特性基本保持不变。附图7为本发明器件与常规器件的I-V特性对比图，可以发现本发明器件与常规器件相比，器件的开态导通特性基本保持不变。(5) The advantage of the device of the present invention is that the frequency characteristic of the device is improved, and on the basis of reducing the gate resistance, the on-state conduction characteristic of the device remains basically unchanged. Accompanying drawing 7 is the comparison chart of I-V characteristics of the device of the present invention and the conventional device, it can be found that compared with the conventional device, the on-state conduction characteristic of the device of the present invention remains basically unchanged.
附图说明Description of drawings
图1是现有的P型射频横向双扩散金属氧化物半导体器件结构剖面图。FIG. 1 is a cross-sectional view of the structure of an existing P-type radio frequency lateral double-diffused metal oxide semiconductor device.
图2是本申请的P型射频横向双扩散金属氧化物半导体器件结构剖面图。Fig. 2 is a cross-sectional view of the structure of the P-type radio frequency lateral double-diffused metal oxide semiconductor device of the present application.
图3是本发明器件与常规器件的截止频率的比较图，可以看出本发明器件使得截止频率得到了提高。Fig. 3 is a comparison diagram of the cut-off frequency of the device of the present invention and the conventional device, it can be seen that the cut-off frequency of the device of the present invention is improved.
图4是本发明器件与常规器件的栅源寄生电容的比较图。可以看出本发明器件使得栅源寄生电容得到了明显的减小。Fig. 4 is a comparison diagram of gate-source parasitic capacitance between the device of the present invention and the conventional device. It can be seen that the device of the present invention significantly reduces the gate-source parasitic capacitance.
图5是本发明器件与常规器件的栅漏寄生电容的比较图。可以看出本发明器件使得栅漏寄生电容得到了明显的减小。Fig. 5 is a graph comparing the gate-drain parasitic capacitance of the device of the present invention and the conventional device. It can be seen that the device of the present invention significantly reduces the gate-to-drain parasitic capacitance.
图6是本发明器件与常规器件的击穿电压的比较图。可以看出本发明器件与常规器件相比，击穿电压基本保持不变。Fig. 6 is a graph comparing breakdown voltages of devices of the present invention and conventional devices. It can be seen that the breakdown voltage of the device of the present invention remains basically unchanged compared with the conventional device.
图7是本发明器件与常规器件的I-V特性的比较图。可以看出本发明器件与常规器件相比，开态导通特性基本保持不变。Fig. 7 is a graph comparing I-V characteristics of the device of the present invention and a conventional device. It can be seen that compared with the conventional device, the on-state conduction characteristics of the device of the present invention remain basically unchanged.
具体实施方式detailed description
下面结合附图2详细说明，一种P型射频横向双扩散金属氧化物半导体器件，包括：N型衬底1，在N型硅衬底1上形成有N型外延层2；在N型外延层2中形成有P型轻掺杂漏区3和N阱4，且N阱4在所述P型轻掺杂漏区3的一侧，N阱4的一侧和所述P型轻掺杂漏区3的一侧相接触，在所述P型轻掺杂漏区3中形成有第一P型重掺杂漏区5；在所述N阱4中形成有第二P型重掺杂源区6，在N阱4的另一侧形成有N型重掺杂引出区7，N型重掺杂引出区7与P型重掺杂源区6和N阱4相接触，并穿过N型外延层2与N型硅衬底1相接触；在N阱4上形成有栅氧化层8，且栅氧化层8的两个边界分别位于P型重掺杂源区6的边界及P型轻掺杂漏区3的边界上方，在栅氧化层8的表面形成有多晶硅栅9；在N型重掺杂引出区7和P型重掺杂源区6上连接有源极金属11，在P型重掺杂漏区5上连接有漏极金属12，源极金属11和漏极金属12分别通过场氧10与多晶硅栅9相隔离，其特征在于，所述栅氧化层8为阶梯状，在栅氧化层8的下方设有P型掺杂区13且所述P型掺杂区13位于N阱4中。A P-type radio frequency lateral double-diffused metal oxide semiconductor device includes: an N-type substrate 1, an N-type epitaxial layer 2 is formed on the N-type silicon substrate 1; A P-type lightly doped drain region 3 and an N well 4 are formed in the layer 2, and the N well 4 is on one side of the P-type lightly doped drain region 3, and one side of the N well 4 is connected to the P-type lightly doped drain region. One side of the miscellaneous drain region 3 is in contact, and a first P-type heavily doped drain region 5 is formed in the P-type lightly doped drain region 3; a second P-type heavily doped drain region 5 is formed in the N well 4 The impurity source region 6 is formed with an N-type heavily doped lead-out region 7 on the other side of the N well 4, and the N-type heavily doped lead-out region 7 is in contact with the P-type heavily doped source region 6 and the N well 4, and passes through The N-type epitaxial layer 2 is in contact with the N-type silicon substrate 1; a gate oxide layer 8 is formed on the N well 4, and the two boundaries of the gate oxide layer 8 are respectively located at the boundary of the P-type heavily doped source region 6 and the Above the boundary of the P-type lightly doped drain region 3, a polysilicon gate 9 is formed on the surface of the gate oxide layer 8; a source metal 11 is connected to the N-type heavily doped lead-out region 7 and the P-type heavily doped source region 6 , the drain metal 12 is connected to the P-type heavily doped drain region 5, and the source metal 11 and the drain metal 12 are respectively separated from the polysilicon gate 9 by the field oxygen 10, and it is characterized in that the gate oxide layer 8 is In a stepped shape, a P-type doped region 13 is provided under the gate oxide layer 8 and the P-type doped region 13 is located in the N well 4 .
所述的阶梯状栅氧化层(8)的第二阶梯与第一阶梯的厚度比为10:1至15:1。The thickness ratio of the second step to the first step of the step-shaped gate oxide layer (8) is 10:1 to 15:1.
所述的P型掺杂区(13)的长度与栅氧化层(8)的第二阶梯的长度相等。The length of the P-type doped region (13) is equal to the length of the second step of the gate oxide layer (8).
所述的P型掺杂区(13)的厚度小于N阱(4)的厚度，大小为大于0且小于0.5μm。The thickness of the P-type doping region (13) is smaller than that of the N well (4), and the size is greater than 0 and less than 0.5 μm.
所述的P型掺杂区(13)的掺杂浓度小于或者等于N阱(4)的掺杂浓度，大小为2.0e17～9.0e17cm-3。The doping concentration of the P-type doping region (13) is less than or equal to the doping concentration of the N well (4), and the size is 2.0e17-9.0e17cm -3 .
所述的P型射频横向双扩散金属氧化物半导体器件，其沟道长度为0.8～1.2μm。The channel length of the P-type radio-frequency lateral double-diffused metal oxide semiconductor device is 0.8-1.2 μm.
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| US6198129B1 (en) * | 1999-08-31 | 2001-03-06 | Oki Electric Industry Co., Ltd. | Vertical type insulated gate transistor |
| CN101573799A (en) * | 2007-01-04 | 2009-11-04 | 飞兆半导体公司 | Integrated complementary low voltage rf-ldmos |
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