CN104598163B - A kind of storage method of the high speed memory modules based on load ground test interface adapter - Google Patents
A kind of storage method of the high speed memory modules based on load ground test interface adapter Download PDFInfo
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- CN104598163B CN104598163B CN201410710709.0A CN201410710709A CN104598163B CN 104598163 B CN104598163 B CN 104598163B CN 201410710709 A CN201410710709 A CN 201410710709A CN 104598163 B CN104598163 B CN 104598163B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
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Abstract
The invention discloses a kind of storage method of the high speed memory modules based on load ground test interface adapter, it comprises the following steps：PHY chip receives the control command from main control computer；First processor is parsed to described control command；Second processor according to control command control its GTP receiving submodule carry out receive data preparation；GTP receiving submodules receive the data from several transmitting/receiving modules；The multistage submodules of streamline top controller control FLASH keep in data in corresponding buffer area；Streamline top controller controls multi-stage pipeline controller that the data in buffer area are stored in into corresponding memory cell according to store instruction, meanwhile, multi-stage pipeline controller also sends corresponding storage state information by streamline top controller to second processor；Second processor is by first processor by storage state feedback of the information to main control computer.The present invention is using multi-stage pipeline control, it is ensured that the real-time reliable memory of high-speed data.
Description
Technical field
The present invention relates to a kind of storage method of the high speed memory modules based on load ground test interface adapter.
Background technology
Artificial satellite be transmitting quantity at most, spacecraft with fastest developing speed, be widely used in telecommunications, meteorology, resource investigation and
The fields such as military surveillance.Present artificial satellite is main by structural system, propulsion system, heat control system, power supply-distribution system, star thing system
The some such as system, telemetering and remote control system, posture control system, data transmission system and payload are constituted.Wherein have
Effect load is that the subsystem of directly execution particular task in satellite is the core of satellite, and it is to determine satellite performance level
Primary sub-system.And data transmission system is to realize that the key of payload information real-time Transmission between space and ground is divided to be
System.With the lifting of satellite performance and index, higher requirement is there has also been to payload and data transmission system.Due to satellite
The particularity of operation on orbit, safeguards extremely difficult after lift-off to it, therefore, and the ground test work before transmitting seems particularly heavy
Will.For load ground test interface adapter, the performance impact of itself high speed memory modules to whole interface adapter
Performance.
The content of the invention
Load ground test interface adapter is based on it is an object of the invention to overcome the deficiencies of the prior art and provide one kind
High speed memory modules storage method, realize the reliable memory of data.
The purpose of the present invention is achieved through the following technical solutions：One kind is based on load ground test interface adapter
High speed memory modules storage method, it comprises the following steps：
S1. PHY chip receives the control command from main control computer by network interface, and sends control command to the
One processor；
S2. first processor is parsed to described control command, and the control command after parsing is sent into second
Processor, second processor controls its GTP receiving submodule to carry out the preparation for receiving data；
S3. the GTP receiving submodules are that interface J3 receives the data from several transmitting/receiving modules by GTP interfaces；
S4. second processor refers to according to the control command after parsing to the forwarding storage of corresponding streamline top controller
Order, streamline top controller controls the multistage submodules of corresponding FLASH to be connect GTP receiving submodules according to the store instruction
The data received are kept in corresponding buffer area；
S5. streamline top controller controls multi-stage pipeline controller to deposit the data in buffer area according to store instruction
Corresponding memory cell is put into, corresponding storage operation is completed, meanwhile, multi-stage pipeline controller also passes through streamline top layer control
Device processed sends corresponding storage state information to second processor；
S6. second processor by first processor by storage state feedback of the information to main control computer.
The beneficial effects of the invention are as follows：Controlled using multi-stage pipeline, it is ensured that the real-time reliable memory of high-speed data.
Brief description of the drawings
Fig. 1 is the flow of the storage method of the high speed memory modules of the invention based on load ground test interface adapter
Figure；
Fig. 2 is the structured flowchart of one embodiment of the present of invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, a kind of storage method of the high speed memory modules based on load ground test interface adapter, it is wrapped
Include following steps：
S1. PHY chip receives the control command from main control computer by network interface, and sends control command to the
One processor；
S2. first processor is parsed to described control command, and the control command after parsing is sent into second
Processor, second processor controls its GTP receiving submodule to carry out the preparation for receiving data；
S3. the GTP receiving submodules are that interface J3 receives the data from several transmitting/receiving modules by GTP interfaces；
S4. second processor refers to according to the control command after parsing to the forwarding storage of corresponding streamline top controller
Order, streamline top controller controls the multistage submodules of corresponding FLASH to be connect GTP receiving submodules according to the store instruction
The data received are kept in corresponding buffer area；
S5. streamline top controller controls multi-stage pipeline controller to deposit the data in buffer area according to store instruction
Corresponding memory cell is put into, corresponding storage operation is completed, meanwhile, multi-stage pipeline controller also passes through streamline top layer control
Device processed sends corresponding storage state information to second processor；
S6. second processor by first processor by storage state feedback of the information to main control computer.
As shown in Fig. 2 a kind of high speed memory modules based on load ground test interface adapter, it include PHY chip,
Fiber optical transceiver, LED state display, memory, first processor and second processor, first processor connect with PHY chip
Connect, PHY chip is connected by network interface with external piloting control computer, first processor is connected by EMIF interfaces with second processor
Data exchange is carried out, second processor is connected by fiber optical transceiver with optical port, the display output and LED state of second processor
Display is connected, and second processor is connected progress data exchange with memory, and second processor is passed by interface J3 and external number
Receiving module connection carries out data exchange.
Described memory is the memory being made up of 32 MLC Nand Flash.
Described first processor includes C6455 main process task chips.
Described second processor is FPGA integrated circuits.
Described memory is by FLASH multi-level buffers submodule, multi-stage pipeline controller and streamline top controller
Composition.
Described FLASH multi-level buffers submodule is made up of multiple buffer units, is received from the control of streamline top layer
The control of device；Multi-stage pipeline controller is the control submodule of one group of independence, includes two levels：One is logical layer, is completed
The functions such as interactive interfacing, the feedback of status of the streamline and top controller；Two be physical layer, completes the sequential of FLASH chip
Control.Streamline top controller realizes top layer control, realizes the functions such as flowing water wire management.
Claims (1)
1. a kind of storage method of the high speed memory modules based on load ground test interface adapter, load is based on based on one kind
The high speed memory modules of ground test interface adapter, it includes PHY chip, fiber optical transceiver, LED state display, storage
Device, first processor and second processor, first processor are connected with PHY chip, and PHY chip passes through network interface and external piloting control meter
Calculation machine is connected, and first processor is connected progress data exchange with second processor by EMIF interfaces, and second processor passes through light
Fine transceiver is connected with optical port, and the display output of second processor is connected with LED state display, second processor and memory
Connection carries out data exchange, and second processor is connected progress data exchange with external number transmitting/receiving module by interface J3；
Described memory is the memory being made up of 32 MLC Nand Flash；
Described first processor includes C6455 main process task chips；
Described second processor is FPGA integrated circuits；
Described memory is made up of FLASH multi-level buffers submodule, multi-stage pipeline controller and streamline top controller；
Characterized in that, it comprises the following steps：
S1. PHY chip receives the control command from main control computer by network interface, and control command is sent at first
Manage device；
S2. first processor is parsed to described control command, and the control command after parsing is sent into second processing
Device, second processor controls its GTP receiving submodule to carry out the preparation for receiving data；
S3. the GTP receiving submodules are that interface J3 receives the data from several transmitting/receiving modules by GTP interfaces；
S4. second processor forwards store instruction, stream according to the control command after parsing to corresponding streamline top controller
Waterline top controller is according to received by the multistage submodules of the corresponding FLASH of store instruction control by GTP receiving submodules
Data keep in corresponding buffer area；
S5. streamline top controller controls multi-stage pipeline controller to be stored in the data in buffer area according to store instruction
Corresponding memory cell, completes corresponding storage operation, meanwhile, multi-stage pipeline controller also passes through streamline top controller
Corresponding storage state information is sent to second processor；
S6. second processor by first processor by storage state feedback of the information to main control computer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410710709.0A CN104598163B (en) | 2014-11-28 | 2014-11-28 | A kind of storage method of the high speed memory modules based on load ground test interface adapter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410710709.0A CN104598163B (en) | 2014-11-28 | 2014-11-28 | A kind of storage method of the high speed memory modules based on load ground test interface adapter |
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| Publication Number | Publication Date |
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| CN104598163A CN104598163A (en) | 2015-05-06 |
| CN104598163B true CN104598163B (en) | 2017-10-17 |
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| CN104360960A (en) * | 2014-11-28 | 2015-02-18 | 成都龙腾中远信息技术有限公司 | High-speed storage module based on load ground test interface adapter and storage method thereof |
| FR3060792B1 (en) * | 2016-12-19 | 2018-12-07 | Safran Electronics & Defense | DATA LOADING DEVICE IN COMPUTERIZED DATA PROCESSING UNITS FROM A DATA SOURCE |
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| US7243212B1 (en) * | 2004-08-06 | 2007-07-10 | Xilinx, Inc. | Processor-controller interface for non-lock step operation |
| CN101980139A (en) * | 2010-11-12 | 2011-02-23 | 北京理工大学 | A storage board based on NAND |
| CN102473126A (en) * | 2009-08-11 | 2012-05-23 | 桑迪士克科技股份有限公司 | Controller and method for providing read status and spare block management information in flash memory system |
| CN103384877A (en) * | 2011-06-07 | 2013-11-06 | 株式会社日立制作所 | Storage system comprising flash memory, and storage control method |
| CN104360960A (en) * | 2014-11-28 | 2015-02-18 | 成都龙腾中远信息技术有限公司 | High-speed storage module based on load ground test interface adapter and storage method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100318824A1 (en) * | 2009-06-10 | 2010-12-16 | Seagate Technology Llc | Storage device with advanced power management |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7243212B1 (en) * | 2004-08-06 | 2007-07-10 | Xilinx, Inc. | Processor-controller interface for non-lock step operation |
| CN102473126A (en) * | 2009-08-11 | 2012-05-23 | 桑迪士克科技股份有限公司 | Controller and method for providing read status and spare block management information in flash memory system |
| CN101980139A (en) * | 2010-11-12 | 2011-02-23 | 北京理工大学 | A storage board based on NAND |
| CN103384877A (en) * | 2011-06-07 | 2013-11-06 | 株式会社日立制作所 | Storage system comprising flash memory, and storage control method |
| CN104360960A (en) * | 2014-11-28 | 2015-02-18 | 成都龙腾中远信息技术有限公司 | High-speed storage module based on load ground test interface adapter and storage method thereof |
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Effective date of registration: 20190509 Address after: Room 208, 2nd floor, No. 599 Gaojing Road, Qingpu District, Shanghai, 201799 Patentee after: SHANGHAI V&G INFORMATION TECHNOLOGY CO.,LTD. Address before: Room 1202, No. 19, 1168 Lane, Tongchuan Road, Putuo District, Shanghai, 2003 Patentee before: Wu Jia Effective date of registration: 20190509 Address after: Room 1202, No. 19, 1168 Lane, Tongchuan Road, Putuo District, Shanghai, 2003 Patentee after: Wu Jia Address before: 610000 No. 88 Tianchen Road, Chengdu High-tech Zone, Sichuan Province Patentee before: CHENGDU LONGTENG ZHONGYUAN INFORMATION TECHNOLOGY Co.,Ltd. |
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