CN104579267A - Pulse drive circuit and pulse drive method - Google Patents
Pulse drive circuit and pulse drive method Download PDFInfo
- Publication number
- CN104579267A CN104579267A CN201310489134.XA CN201310489134A CN104579267A CN 104579267 A CN104579267 A CN 104579267A CN 201310489134 A CN201310489134 A CN 201310489134A CN 104579267 A CN104579267 A CN 104579267A
- Authority
- CN
- China
- Prior art keywords
- driving element
- pulse
- described driving
- control signal
- synchronized loading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000001360 synchronised effect Effects 0.000 claims abstract description 67
- 230000005669 field effect Effects 0.000 claims description 10
- 230000000630 rising effect Effects 0.000 claims description 10
- 230000001105 regulatory effect Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 33
- 238000004088 simulation Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 6
- 238000009434 installation Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000004422 calculation algorithm Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Abstract
The invention provides pulse drive equipment and a pulse drive method which can be used for improving turn-off delay. The pulse drive circuit comprises a drive part and a delay regulating part, wherein the drive part is connected to a user load, comprises a drive element, and is used for receiving an input control signal to provide an output control signal to the user load; the delay regulating part comprises a synchronous load; when the drive element is turned off, the synchronous load is connected to the drive element for regulating the turn-off delay of the drive element.
Description
Technical field
The present invention relates to a kind of pulse driving circuit and pulse drive method, more particularly, relate to a kind of pulse driving circuit and the pulse drive method that use transistor or field effect transistor (FET) to carry out driving pulse ripple.
Background technology
In the field such as electronic technology and mechano-electronic, usually use the driving element of such as transistor or FET to drive ideal pulse ripple, and the output of transistor or FET is applied to load.But, due to transistor and the input equivalent capacity of FET and the impact of output equivalent electric capacity, cause transistor and FET open time delay and turn off delay time is long, cause the impulse waveform generation distortion of output.
Usually, determined to open time delay by the input impedance of input control logic circuit and the input equivalent capacity of transistor or FET, because the input equivalent capacity of transistor or FET is relatively fixing, if therefore designer can minimize input impedance, can guarantee to open time delay preferably.
But for turn off delay time, because its output impedance primarily of transistor or FET and output equivalent electric capacity are determined, even if so the output equivalent electric capacity of transistor or FET is relatively fixing, output impedance also changes with the load in different application.
Current exist a kind of by being connected the method that dummy load regulates turn off delay time by user, but the dummy load that this method connects is difficult to meet all user's applied environments, therefore need differently to be determined dummy load and carry out outside to be connected with frequency application according to different loads by user, extra amount of calculation is brought to user, and the installation of dummy load is also cumbersome, this makes user feel very inconvenient.
Summary of the invention
The embodiment of the present invention provides a kind of pulsed drive equipment and pulse drive method, can improve turn off delay time, and has nothing to do with user's applied environment, calculates and install without the need to user.
According to an aspect of the embodiment of the present invention, a kind of pulse driving circuit is provided, comprises: drive part, be connected to user load and comprise driving element, for receiving input control signal to provide output control signal to user load; And delay adjustment part, comprise synchronized loading, and this synchronized loading is connected to described driving element when driving element starts to turn off, to regulate the turn off delay time of described driving element.
According to the another aspect of the embodiment of the present invention, a kind of pulse drive method is provided, comprises: receive input control signal by drive part; Output control signal is provided to user load when the driving element in drive part is opened; And when driving element starts to turn off, the synchronized loading comprised in delay adjustment part is connected to described driving element, to regulate the turn off delay time of described driving element.
Therefore, according to the embodiment of the present invention, in pulse driving circuit, be furnished with delay adjustment part, be used for regulating the turn off delay time of driving element.Because the synchronized loading comprised in this delay adjustment part is only just connected to driving element when driving element turns off, be namely only just connected to driving element when driving element turns off user load, so the value of synchronized loading and user's applied environment have nothing to do.Thus, all user's applied environments can be applied to according to the pulse driving circuit of the embodiment of the present invention, neither need by user to determine that load value does not need user to carry out extra installation yet, save the time of user and simplify operation, this brings great advantage to the user.
Accompanying drawing explanation
By the following detailed description by accompanying drawing, more easily will understand the present invention, wherein identical label specifies the unit of same structure, and wherein:
Fig. 1 (a) and Fig. 1 (b) is the schematic diagram of the principle of diagram pulse driving circuit;
Fig. 2 illustrates to utilize dummy load to regulate the schematic circuit of turn off delay time in the prior art;
Fig. 3 is the schematic block diagram of diagram according to the pulse driving circuit for improving turn off delay time of the embodiment of the present invention;
Fig. 4 is the simplified schematic circuit diagram of diagram according to the pulse driving circuit for improving turn off delay time of the embodiment of the present invention;
Fig. 5 is the simplified schematic circuit diagram of diagram according to the pulse driving circuit for improving turn off delay time of the embodiment of the present invention;
Fig. 6 (a) is the schematic circuit of diagram according to a kind of specific implementation of the pulse driving circuit of the embodiment of the present invention;
Fig. 6 (b) is the schematic diagram of diagram according to the simulation result of a kind of specific implementation of the pulse driving circuit of the embodiment of the present invention;
Fig. 7 is the schematic circuit of diagram according to the another kind of specific implementation of the pulse driving circuit of the embodiment of the present invention;
Fig. 8 (a) to Fig. 8 (e) is the schematic diagram of the wave simulation of pulsed drive equipment; And
Fig. 9 is the indicative flowchart of diagram according to the pulse drive method 900 of the embodiment of the present invention.
Embodiment
The one exemplary embodiment of the present invention that the following describes to help complete understanding by claim and equivalents thereof with reference to accompanying drawing is provided.It comprises various details to help understanding, but they should be thought it is only exemplary.Therefore, those of ordinary skill in the art will be appreciated that, can make various change and amendment, and can not deviate from scope and spirit of the present invention to the embodiments described herein.Equally, for clarity and conciseness, the description to known function and structure is eliminated.
Although it should be understood that and term first, second, third, etc. can be used here to describe various element, assembly, region, layer and/or part, these elements, assembly, region, layer and/or part do not should be these terms and limited.These terms are only used to an element, assembly, region, layer and/or part and another element, assembly, region, layer and/or part to distinguish mutually.Thus, the first element discussed below, assembly, region, layer and/or part can be called the second element, assembly, region, layer and/or part, and can not deviate from instruction of the present invention.
The term here used is only used to the object describing specific embodiment, and is not intended to limit the present invention.As used herein, singulative " ", " one " and " being somebody's turn to do " are intended to also comprise plural form, unless context explicitly points out really not so.Be to be further appreciated that, when using in this manual, term " comprise " and/or " comprising ... " or " comprising " and/or " comprising ... " specify set forth feature, region, integer, step, operation, element and/or assembly existence, but do not get rid of and exist or add other features one or more, region, integer, step, operation, element and/or assembly and/or its group.
Unless otherwise defined, otherwise all terms used here have the identical implication usually understood with field belonging to the present invention those of ordinary skill.Be to be further appreciated that, those terms such as defined in general dictionary should be interpreted as having the implication consistent with correlation technique and its implication contextual of the present disclosure, and with idealized or too formal meaning, it should not made an explanation, unless so define clearly here.
Fig. 1 (a) and Fig. 1 (b) is the schematic diagram of the principle of diagram pulse driving circuit, and wherein, Fig. 1 (a) schematically illustrates the simplified electrical circuit diagram of pulse driving circuit, and Fig. 1 (b) schematically illustrates the comparison of the waveform quality of input pulse and output pulse.
As shown in Figure 1 (a), R1 represents user load, and Co represents the output equivalent electric capacity of driving element (transistor or FET) T1, and therefore, when R1 has larger resistance, the electric current flowing through R1 is less.
Illustrate input pulse in Fig. 1 (b) and export the comparing of pulse, can see, although input pulse has the square-wave form of standard, due to T1, when turning off, Co can not quick charge and cause the waveform generation distortion exporting pulse.If R1 is very large, namely output impedance is very high, then higher output impedance causes the poor performance of the turn off delay time of T1 together with Co, so that T1 can not turn off immediately.When some are serious, if there is the very short shutoff period because of frequency applications, then when turning off, once open finally on before Co is also charged to far away the predetermined voltage that user wants, as a result, seem that driving element seems not turn off at all, so that export the frequency that pulse can not follow input pulse, which has limited the switching frequency of driving element, be degrading circuit performance.
Fig. 2 illustrates to utilize dummy load to regulate the schematic circuit of turn off delay time in the prior art.
As shown in Figure 2, a dummy load is connected in parallel with user load.The impedance of dummy load is designed to be enough little usually, enough short with the charging interval and discharge time of guaranteeing Co.But, because the dummy load in this scheme is relevant with user's applied environment, so different user's applied environments can not be applied to, need differently to be determined dummy load and carry out outside to be connected with frequency application according to different loads by user, extra amount of calculation is brought to user, and the installation of dummy load is also cumbersome, this makes user feel very inconvenient.
In addition, once select and be connected to dummy load, this dummy load will be connected in loop always, and no matter T1 opens or turns off.Therefore, when T1 is in opening state, dummy load unnecessarily consumes energy, causes waste.Dummy load also may cause other problems.Such as, because the impedance of dummy load needs enough little, so there is the defect of the aspects such as the too high and volume of temperature rise is larger.If user selects improper, also may not reach because dummy load is excessive and improve effect, or circuit may be caused because dummy load is too small to damage.
Although illustrated that T1 is the situation of NPN transistor in Fig. 1 (a), Fig. 1 (b) and Fig. 2, it will be appreciated by those skilled in the art that, T1 also can be N channel fet, such as N-MOSFET or N-JFET.Further, when T1 be PNP transistor or P channel fet time, there will be similar situation.Here, P channel fet can comprise P-MOSFET, P-JFET etc.
Fig. 3 is the schematic block diagram of diagram according to the pulse driving circuit 300 for improving turn off delay time of the embodiment of the present invention.
As shown in Figure 3, pulse driving circuit 300 comprises drive part 301 and delay adjustment part 302.
Drive part 301 is connected to user load, for receiving input control signal to provide output control signal to user load.Comprise driving element (not shown) at drive part 301, such as, this driving element can be transistor or field effect transistor (FET).
Delay adjustment part 302 comprises synchronized loading, and this synchronized loading is connected to driving element when driving element starts to turn off, to regulate the turn off delay time of driving element.
Therefore, according to the embodiment of the present invention, in pulse driving circuit, be furnished with delay adjustment part, be used for regulating the turn off delay time of driving element.Because the synchronized loading comprised in this delay adjustment part is only just connected to driving element when driving element turns off, be namely only just connected to driving element when driving element turns off user load, so the value of synchronized loading and user's applied environment have nothing to do.Thus, all user's applied environments can be applied to according to the pulse driving circuit of the embodiment of the present invention, neither need by user to determine that load value does not need user to carry out extra installation yet, save the time of user and simplify operation, this brings great advantage to the user.
Fig. 4 is the simplified schematic circuit diagram of diagram according to the pulse driving circuit 400 for improving turn off delay time of the embodiment of the present invention.Although in the diagram driving element T1 is depicted as NPN transistor, obviously it can also be FET, such as N-MOSFET.
As shown in Figure 4, except synchronized loading, the delay adjustment circuit according to the embodiment of the present invention also comprises switch element S1, for the connection between control synchronization load and driving element T1.S1 is connected to input control signal, thus can and described input control signal synchronously carry out between control synchronization load and driving element T1 connection.
Particularly, when T1 opens, namely when T1 is connected with user load, S1 is always in off state, not to be connected with T1 by synchronized loading.When T1 turns off, S1 is open-minded, and now synchronized loading is connected to T1, and the shutoff along with T1 disconnects by the current path between user load and T1.When T1 prepares to turn off, the output equivalent electric capacity of T1 needs charging, to realize the shutoff of T1, but, in traditional pulse driving circuit, because the impedance of user load is usually comparatively large, so the time spent of charging is longer, cause the turn off delay time of T1 excessive.By contrast, according in the pulse driving circuit 400 of the embodiment of the present invention, when T1 starts to turn off, the current path between synchronized loading and T1 is switched on, so T1 can carry out quick charge by synchronized loading.
Usually, in order to shorten the T1 time that its output equivalent capacitor charging spends when turning off as far as possible, wish that the electric current flowing through synchronized loading is the bigger the better, so can be set to less by the resistance value of synchronized loading.
Driving element T1 shown in Fig. 4 is NPN transistor, and synchronized loading is connected to T1 by the trailing edge that therefore switch element S1 can be set to follow input control signal, to realize being charged by synchronized loading when T1 starts to turn off.Such as, when T1 turns off, S1 is open-minded, and this S1 is in off state when T1 opens.That is, synchronized loading is connected to T1 when each T1 starts to turn off by S1, and keeps connecting in the period of opening of S1.In other words, the period that S1 is in opening state can be less than or equal to the period that T1 is in off state, to guarantee, when T1 opens user load, not having electric current to flow through between synchronized loading and T1.
In one example, consider some tolerance limits, open that the period can be the shutoff period of T1 1/4th of S1.Therefore, synchronized loading only starts to close in a period of time of having no progeny at T1 the current path kept between T1, and all the other times outside this period all disconnect with T1.
Illustrated in table 1 below according to the user load of the present embodiment and synchronized loading according to input control signal respectively with the connection status of T1.
Table 1
| Input control signal | User load and T1 | Synchronized loading and T1 | Remarks |
| Rising edge | Prepare to connect | Disconnect | |
| High level | Connect | Disconnect | |
| Trailing edge | Prepare to disconnect | Connect a period of time | Disconnect after one section time |
| Low level | Disconnect | Disconnect |
Because synchronized loading is inoperative when T1 opens and opens user load, the size of synchronized loading can have nothing to do with user load, thus the load value of synchronized loading can be fixed, and can be applied to different user's applied environments.In addition, when T1 opens, synchronized loading can not consumed energy, saves electric power, also there is not the problem that temperature rises.Because synchronized loading is integrated in the pulse driving circuit according to the embodiment of the present invention and its load value can be fixing, so user is without the need to spended time and energy are selected and installed extra load again.
Certainly, it is adjustable for also synchronized loading can being configured to its size, so that user regulates when needed voluntarily.
In addition, when T1 is FET, such as N-MOSFET, situation is similar, repeats no more here.
Fig. 5 is the simplified schematic circuit diagram of diagram according to the pulse driving circuit 500 for improving turn off delay time of the embodiment of the present invention.Although in Figure 5 driving element T1 is depicted as PNP transistor, obviously it can also be FET, such as P-MOSFET.
Be (user load in Fig. 4 is leakage type) except the type of source except driving element T1 is PNP transistor or P channel fet and user load, those are similar for pulse driving circuit 400 in the configuration of the pulse driving circuit 500 in Fig. 5 and the course of work and Fig. 4, therefore for avoiding repetition to eliminate description to it.
T1 shown in Fig. 5 is PNP transistor, and synchronized loading is connected to T1 by the rising edge that therefore switch element S1 can be set to follow input control signal.In addition, when T1 is FET, situation is similar, repeats no more here.
Illustrated in table 2 below according to the user load of the present embodiment and synchronized loading according to input control signal respectively with the connection status of T1.
Table 2
| Input control signal | User load and T1 | Synchronized loading and T1 | Remarks |
| Rising edge | Prepare to disconnect | Connect a period of time | Disconnect after one section time |
| High level | Disconnect | Disconnect | |
| Trailing edge | Prepare to connect | Disconnect | |
| Low level | Connect | Disconnect |
Be connected in parallel with user load although in figures 4 and 5 the delay adjustment comprising synchronized loading and S1 is partially configured to, but this is only a kind of connected mode physically and not in logic, and be only schematic, it will be appreciated by those skilled in the art that, the embodiment of the present invention is not limited thereto, concrete connected mode can be designed, as long as T1 can when starting to turn off by synchronized loading charge or discharge according to specific implementation.
Fig. 6 (a) is the schematic circuit of diagram according to a kind of specific implementation 600 of the pulse driving circuit of the embodiment of the present invention, and Fig. 6 (b) is the schematic diagram of diagram according to the simulation result of a kind of specific implementation of the pulse driving circuit of the embodiment of the present invention.
Although driving element is shown as in figure 6 (a) is P-MOSFET Q3, obviously it also can be PNP transistor.
As shown in Figure 6 (a), the part in dotted line frame is delay adjustment part, and comprising that switch element Q2(is shown as is NPN transistor) and synchronized loading R5, also comprise capacitor C1, diode D1 and resistance R3 and R4.Co represents the output equivalent electric capacity of Q3.
In figure 6 (a), user load R6(1000K Ω) and synchronized loading R5 be connected to same input control signal V2.As an example, V2 can be that in industrial circle, server and motor are commonly used to the square wave with 100Khz and 24Vdc as input.Q3 turns on and off under the control of V2, thus the current path when V2 is in low level between user load R6 and Q3 is switched on, R6 is unlocked to work, and the current path when V2 is in high level between R6 and Q3 is disconnected, R6 is turned off, thus R6 does not work.
When the rising edge of V2 comes interim, Q3 prepares to cut off the connection between R6.Meanwhile, the rising edge of V2 will be charged to C1 by R3, and this makes Q2 open to be connected by the current path between synchronized loading R5 and Q3.In this case, current path between synchronized loading R5 and Q3 is that the output equivalent electric capacity Co of Q3 provides a quick charge path, thus the voltage on Co promptly can change into 24V from 0V by this current path, result is, the turn off delay time of Q3 is shortened, and thus Q3 can promptly turn off.
Q2 open period, i.e. Q2 open make the current path between R5 and Q3 keep connect time period determined by the capacitance of C1 and the resistance value of R3, namely determined by timeconstantτ, wherein τ=C1 × R3.Current path when being switched in order to ensure the current path between Q3 and user load R6 between R5 and Q3 disconnects, and the period of opening of Q2 should not be long, is preferably no more than the shutoff period of Q3.Also namely, Q2 open the shutoff period that the period can be less than or equal to Q3.When considering some tolerance limits, can by open that period, i.e. timeconstantτ are set to the shutoff period being Q3 1/4th of Q2.In one example in which, for the frequency of 100Khz, the shutoff period of Q3 is 10 μ s, therefore timeconstantτ can be set to 2.5 μ s, i.e. C1=0.22nF and R3=10K Ω.
Therefore, the current path between R5 and Q3 is had no progeny in each Q3 preparation pass and is switched on a period of time, then automatically disconnects, until the rising edge of V2 arrives for it next time, so repeatedly.
General small-signal transistor or small-signal FET can be selected to be used as Q2, and Q2 have the type contrary with the type of Q3 (N-type or P type).But the embodiment of the present invention is not limited thereto, those skilled in the art can select the combination of other devices or device to be used as Q2, as long as it can realize turning off when Q3 opens and opening when Q3 turns off.R4 is the current-limiting resistor of Q2, and D1 is the protection diode of Q2, does not do too much restriction for their embodiment of the present invention, and those skilled in the art can come to select suitable element voluntarily as required.
Although the electric current flowing through R5 in order to the charging interval of accelerating Co is the bigger the better, also need to consider that the power dissipation of R5 and temperature rise.In the example of Fig. 6 (a), the value of R5 is chosen as 470 Ω, to obtain the synchronizing current up to 50mA flowing through R5.
The value of R5 can be determined relatively with Q3.Once designer have selected Q3, R5 can be determined.Such as, can select the value meeting R5 × Co<1/ (10 × f), here, Co is the equivalent output capacitance of Q3, and f is user's maximum impulse frequency.
Fig. 6 (b) schematically illustrates the waveform of V2 and the waveform comparison figure at B point place.
As can be seen from Fig. 6 (b), Q2 follows the rising edge of V2 and open-minded, and namely turns off after opening a period of time, and all keeps turning off in all the other times.Thus, both ensure that the turn-off performance of Q3, and make again R5 and user's applied environment have nothing to do.
Fig. 7 is the schematic circuit of diagram according to the another kind of specific implementation 700 of the pulse driving circuit of the embodiment of the present invention, although driving element is shown as in the figure 7 is N-MOSFET M1, obviously it also can be NPN transistor.
As shown in Figure 7, the part in dotted line frame is delay adjustment part, and comprising that switch element Q2(is shown as is PNP transistor) and synchronized loading R9(470 Ω), also comprise capacitor C1, diode D1 and resistance R11 and R10.User load R7 is 1000K Ω.
Except driving element M1 is charged by synchronized loading R9 when starting to turn off, the configuration of the pulsed drive equipment in Fig. 7 is identical with those of the pulsed drive equipment in Fig. 6 with the course of work, therefore for simplicity, repeats no more here.
Fig. 8 (a) to Fig. 8 (e) is the schematic diagram of the wave simulation of pulsed drive equipment, wherein, Fig. 8 (a) be diagram according to the input pulse (Input) in the pulse driving circuit of the embodiment of the present invention and the schematic diagram of simulation result exporting pulse (Output), and Fig. 8 (b) to Fig. 8 (e) is input pulse (Input) in traditional pulse driving circuit and the schematic diagram of simulation result exporting pulse (Output).
Simulation result shown in Fig. 8 (a) operates circuit as shown in Figure 6 (a) and obtains, charge constant is set to 2.2 μ s, C1=0.22nf, R3=10K Ω, synchronized loading R5=470 Ω, user load R6=1000K Ω, and the load current under 100Khz frequency with 24 μ A.
Simulation result shown in Fig. 8 (b) to Fig. 8 (e) operates circuit part remaining after circuit is as shown in Figure 6 (a) removed delay adjustment part and obtains, therefore, except delay adjustment part, its component parameter is identical with circuit as shown in Figure 6 (a).
For Fig. 8 (b), user load R6=1000K Ω, and the load current under 100Khz frequency with 24 μ A.
For Fig. 8 (c), user load R6=10K Ω, and there is the load current of 2.4mA under 100Khz frequency.
For Fig. 8 (d), user load R6=1.2K Ω, and there is the load current of 20mA under 100Khz frequency.
For Fig. 8 (e), user load R6=1000K Ω, and the load current under 100hz frequency with 24 μ A.
Can find out, even if when frequency is up to 100Khz, also can supports according to the pulse driving circuit of the embodiment of the present invention load current being low to moderate 24 μ A, and obvious wave distortion can not occur.But when not applying the pulse driving circuit according to the embodiment of the present invention, in order to support the frequency of 100Khz, load current must higher than 20mA, otherwise, if go for the load current of 24 μ A, then only can support the frequency of 100hz.
Fig. 9 is the indicative flowchart of diagram according to the pulse drive method 900 of the embodiment of the present invention.
At 901 of pulse drive method 900, receive input control signal by drive part.902, provide output control signal when the driving element in drive part is opened to user load.903, when driving element starts to turn off, the synchronized loading comprised in delay adjustment part is connected to described driving element, to regulate the turn off delay time of described driving element.
Therefore, according to the embodiment of the present invention, in pulse driving circuit, be furnished with delay adjustment part, be used for regulating the turn off delay time of driving element.Because the synchronized loading comprised in this delay adjustment part is only just connected to driving element when driving element turns off, be namely only just connected to driving element when driving element turns off user load, so the value of synchronized loading and user's applied environment have nothing to do.Thus, all user's applied environments can be applied to according to the pulse driving circuit of the embodiment of the present invention, neither need by user to determine that load value does not need user to carry out extra installation yet, save the time of user and simplify operation, this brings great advantage to the user.
In addition, the connection between synchronized loading with described driving element and input control signal synchronous.
When driving element be NPN transistor or N channel field-effect pipe (FET) time, synchronized loading is connected to described driving element by the trailing edge of following input control signal, and when driving element be PNP transistor or P-channel field-effect transistor (PEFT) pipe (FET) time, synchronized loading is connected to driving element by the rising edge of following input control signal.
In addition, as previously mentioned, delay adjustment part also comprises switch element, and for the connection between control synchronization load and described driving element, when driving element turns off, this switch element is opened and this switch element is in off state when driving element is opened.
Particularly, by switch element, synchronized loading is connected to driving element when each driving element starts to turn off, and keeps connecting in the period of opening of described switch element.Switch element open the shutoff period that the period is less than or equal to driving element.In one example, switch element open that the period is the shutoff period of driving element 1/4th.
Therefore, be very easy to realize according to the pulsed drive equipment of the embodiment of the present invention and pulse drive method.Each assembly in delay adjustment part is only common resistor, capacitor, small-signal transistor etc., be easy to obtain and with low cost.In addition, because the value of each assembly in delay adjustment part can be fixing, therefore it can be disposed on printed circuit board (PCB) (PCB) during the manufacture of product, to select and installs, which save human cost and the time cost of user without the need to user according to its applied environment.Only just working when driving element turns off according to the synchronized loading in the embodiment of the present invention, can not affect other functions of equipment, and also can not consume extra power, is a kind of solution of green.
On the other hand, the output frequency of whole equipment is no longer subject to the impact of user load place electric current, even if even when the electric current of user load is low to moderate microampere (μ A), frequency response characteristic also can not worsen, as shown in Fig. 8 (a) to Fig. 8 (e).
It should be noted that for clarity and conciseness, illustrate only the part relevant to the embodiment of the present invention, but it will be appreciated by those skilled in the art that in Fig. 3 to Fig. 7, the equipment shown in Fig. 3 to Fig. 7 or device can comprise the unit of other necessity.
Those of ordinary skill in the art can recognize, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
Those skilled in the art can be well understood to, and for convenience and simplicity of description, the specific works process of the system of foregoing description, device and unit, with reference to the corresponding process in preceding method embodiment, can not repeat them here.
In several embodiments that the application provides, should be understood that disclosed system, apparatus and method can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described unit, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of device or unit or communication connection can be electrical, machinery or other form.
The described unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, both can be positioned at a place, or also can be distributed in multiple network element.Some or all of unit wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, also can be that the independent physics of unit exists, also can two or more unit in a unit integrated.Above-mentioned integrated unit both can adopt the form of hardware to realize, and the form of SFU software functional unit also can be adopted to realize.
If described integrated unit using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computer read/write memory medium.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words or all or part of of this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. various can be program code stored medium.
Also it is pointed out that in apparatus and method of the present invention, obviously, each parts or each step can decompose and/or reconfigure.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Further, the step performing above-mentioned series of processes can order naturally following the instructions perform in chronological order, but does not need necessarily to perform according to time sequencing.Some step can walk abreast or perform independently of one another.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection range of claim.
Claims (18)
1. a pulse driving circuit, is characterized in that, comprising:
Drive part, is connected to user load and comprises driving element, for receiving input control signal to provide output control signal to user load; And
Delay adjustment part, comprises synchronized loading, and this synchronized loading is connected to described driving element when driving element starts to turn off, to regulate the turn off delay time of described driving element.
2. pulse driving circuit according to claim 1, is characterized in that, the connection between described synchronized loading with described driving element and described input control signal synchronous.
3. pulse driving circuit according to claim 2, it is characterized in that, when described driving element be NPN transistor or N channel field-effect pipe (FET) time, the trailing edge that described synchronized loading follows input control signal is connected to described driving element, and when described driving element be PNP transistor or P channel fet time, the rising edge that described synchronized loading follows input control signal is connected to described driving element.
4. the pulse driving circuit according to any one in claims 1 to 3, it is characterized in that, described delay adjustment part also comprises switch element, for controlling the connection between described synchronized loading and described driving element, when described driving element turns off, this switch element is opened and this switch element is in off state when described driving element is opened.
5. the pulse driving circuit according to any one in Claims 1-4, it is characterized in that, described synchronized loading is connected to driving element when each driving element starts to turn off by switch element, and keeps connecting in the period of opening of described switch element.
6. pulse driving circuit according to claim 5, is characterized in that, described switch element open the shutoff period that the period is less than or equal to described driving element.
7. pulse driving circuit according to claim 6, is characterized in that, open that the period is the shutoff period of described driving element 1/4th of described switch element.
8. the pulse driving circuit according to any one in claim 1 to 7, is characterized in that, described driving element is transistor or field effect transistor (FET).
9. the pulse driving circuit according to any one in claim 4 to 8, is characterized in that, described switch element is the small-signal transistor contrary with the type of described driving element or small-signal field effect transistor (FET).
10. a pulse drive method, is characterized in that, comprising:
Input control signal is received by drive part;
Output control signal is provided to user load when the driving element in drive part is opened; And
When driving element starts to turn off, the synchronized loading comprised in delay adjustment part is connected to described driving element, to regulate the turn off delay time of described driving element.
11. pulse drive methods according to claim 10, is characterized in that, the connection between described synchronized loading with described driving element and described input control signal synchronous.
12. pulse drive methods according to claim 11, it is characterized in that, when described driving element be NPN transistor or N channel field-effect pipe (FET) time, the trailing edge that described synchronized loading follows input control signal is connected to described driving element, and when described driving element be PNP transistor or P channel fet time, the rising edge that described synchronized loading follows input control signal is connected to described driving element.
13. according to claim 11 to the pulse drive method described in any one in 13, it is characterized in that, described delay adjustment part also comprises switch element, for controlling the connection between described synchronized loading and described driving element, when described driving element turns off, this switch element is opened and this switch element is in off state when described driving element is opened.
14. according to claim 10 to the pulse drive method described in any one in 13, it is characterized in that, by switch element, described synchronized loading is connected to driving element when each driving element starts to turn off, and keeps connecting in the period of opening of described switch element.
15. pulse drive methods according to claim 14, is characterized in that, described switch element open the shutoff period that the period is less than or equal to described driving element.
16. pulse drive methods according to claim 15, is characterized in that, open that the period is the shutoff period of described driving element 1/4th of described switch element.
17. according to claim 10 to the pulse drive method described in any one in 16, and it is characterized in that, described driving element is transistor or field effect transistor (FET).
18. according to claim 13 to the pulse drive method described in any one in 17, and it is characterized in that, described switch element is the small-signal transistor contrary with the type of described driving element or small-signal field effect transistor (FET).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310489134.XA CN104579267A (en) | 2013-10-18 | 2013-10-18 | Pulse drive circuit and pulse drive method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310489134.XA CN104579267A (en) | 2013-10-18 | 2013-10-18 | Pulse drive circuit and pulse drive method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104579267A true CN104579267A (en) | 2015-04-29 |
Family
ID=53094619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310489134.XA Pending CN104579267A (en) | 2013-10-18 | 2013-10-18 | Pulse drive circuit and pulse drive method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104579267A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114567956A (en) * | 2022-03-09 | 2022-05-31 | 北京中瑞方兴科技有限公司 | Method and system for coping with light-load direct-current carrier signal distortion in direct-current lighting power supply |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1667951A (en) * | 2005-03-08 | 2005-09-14 | 南京航空航天大学 | DC solid-state power switching circuit |
| CN1717869A (en) * | 2002-11-29 | 2006-01-04 | 皇家飞利浦电子股份有限公司 | Driver for switching circuit and drive method |
| CN101686586A (en) * | 2009-01-20 | 2010-03-31 | 深圳市众明半导体照明有限公司 | LED dimming device applied to controllable silicon dimmer |
| US20120306464A1 (en) * | 2011-05-31 | 2012-12-06 | Infineon Technologies Austria Ag | Circuit Arrangement with an Adjustable Transistor Component |
| CN102970015A (en) * | 2012-11-01 | 2013-03-13 | 电子科技大学 | Zero dead area grid driving circuit |
-
2013
- 2013-10-18 CN CN201310489134.XA patent/CN104579267A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1717869A (en) * | 2002-11-29 | 2006-01-04 | 皇家飞利浦电子股份有限公司 | Driver for switching circuit and drive method |
| CN1667951A (en) * | 2005-03-08 | 2005-09-14 | 南京航空航天大学 | DC solid-state power switching circuit |
| CN101686586A (en) * | 2009-01-20 | 2010-03-31 | 深圳市众明半导体照明有限公司 | LED dimming device applied to controllable silicon dimmer |
| US20120306464A1 (en) * | 2011-05-31 | 2012-12-06 | Infineon Technologies Austria Ag | Circuit Arrangement with an Adjustable Transistor Component |
| CN102970015A (en) * | 2012-11-01 | 2013-03-13 | 电子科技大学 | Zero dead area grid driving circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114567956A (en) * | 2022-03-09 | 2022-05-31 | 北京中瑞方兴科技有限公司 | Method and system for coping with light-load direct-current carrier signal distortion in direct-current lighting power supply |
| CN114567956B (en) * | 2022-03-09 | 2024-02-20 | 北京中瑞方兴科技有限公司 | Method and system for coping with light-load direct-current carrier signal distortion in direct-current illumination power supply |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205725692U (en) | For driving the gate driver circuit of power switch | |
| CN204131377U (en) | Adaptive M OS gate driver circuit and the gate driver circuit for MOS transistor | |
| JP5706007B2 (en) | Semiconductor device with on-chip voltage regulator | |
| US8710873B2 (en) | System and method for a driver circuit with a referenced control signal | |
| CN203071815U (en) | Hot-plug power system | |
| KR101651499B1 (en) | Programmable frequency range for boost converter clocks | |
| CN103743059A (en) | Air conditioner and pre-heating control method and device of compressor | |
| CN105322522A (en) | Method and circuit for restraining surge current of DC electrical source | |
| CN101836351A (en) | Voltage regulator with ripple compensation | |
| US10763833B2 (en) | Multiphase oscillator circuit | |
| CN104615183B (en) | The control circuit of operation voltage and memorizer thereof | |
| CN107306119A (en) | Circuit system and method for gallium nitride GaN device | |
| TW201946387A (en) | PIN diode driver with energy recovery | |
| CN104467405A (en) | Charge pump circuit and storage device | |
| CN204145445U (en) | For providing device and the system of the power supply of gate | |
| KR20150105809A (en) | control circuit including load switch, electronic apparatus including the load switch and controlling method thereof | |
| CN104518486A (en) | Discharge circuit for quickly discharging capacitor after powering off | |
| CN107086863B (en) | Driving circuit for power switch | |
| CN104579267A (en) | Pulse drive circuit and pulse drive method | |
| CN203747778U (en) | System power supply circuit | |
| US9887625B2 (en) | Output current monitor circuit for switching regulator | |
| CN207926553U (en) | A kind of multifunction switch controller | |
| CN104377957A (en) | Fast high-side power fet gate sense circuit for high voltage applications | |
| US8614598B2 (en) | Output circuit, system including output circuit, and method of controlling output circuit | |
| US20170288660A1 (en) | Ultra-Low Quiescent Current Multi-Function Switching Circuit and Method for Connecting a Voltage Source to an Output Load with Deep Sleep Capability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150429 |