CN104578341B - An on-board charger with adjustable dead time based on phase-shifted full-bridge circuit - Google Patents

Abstract

An on-board charger with adjustable dead time based on a phase-shifting full-bridge circuit, including a sequentially connected three-phase rectifier circuit, an input filter circuit, a phase-shifting full-bridge circuit and an STM32 single-chip microcomputer, an output voltage and current detection circuit, and a dynamic dead-time The adjustment circuit and four gate-driven push-pull amplifier circuits with the same structure, the STM32 MCU generates four PWM drive signals from the timer according to the sampling value of the output voltage and current detection circuit and connects them to the four input terminals of the dead zone dynamic adjustment circuit. The area dynamic adjustment circuit outputs four channels of PWM signals with dead time, respectively connected to the input terminals of the four gate-driven push-pull amplifier circuits, and the output terminals of the four gate-driven push-pull amplifier circuits respectively control the four channels in the phase-shifting full-bridge circuit. The gates of the three switching tubes Q1, Q2, Q3, and Q4 realize the dynamic adjustment of the dead time of the phase-shifting full-bridge circuit and the large power output, which greatly improves the working efficiency of the charger.

Description

An on-board charger with adjustable dead time based on phase-shifted full-bridge circuit

technical field

The invention relates to an on-board charger based on a phase-shifting full-bridge structure, in particular to an on-board charger based on a phase-shifting full-bridge circuit with adjustable dead time. Since the dead time can be dynamically and continuously adjusted, the efficiency within the full load range can be improved .

Background technique

With the depletion of traditional energy, the application of new energy, especially electric energy, is becoming a mainstream development trend in the automotive field. However, the popularization of electric vehicles still has many problems to be solved urgently, especially the on-board charger as its charging equipment still has many places to be optimized. For high-power chargers, it is generally based on a phase-shifted full-bridge structure. The gate of the full-bridge circuit is driven by using a single-chip microcomputer chip to generate four pairs of complementary PWM signals. However, the lagging arm of the traditional charger based on the phase-shifted full-bridge structure is difficult to achieve ZVS (Zero Voltage Switching) under light load conditions, and the heat generated by the switching tube is relatively serious and difficult to achieve soft switching. In addition, due to the existence of the filter inductor, the current on the filter inductor cannot change suddenly. During the phase change of the primary side current, the two diodes on the secondary side are in the freewheeling state, and the voltage of the secondary side transformer is zero, resulting in the loss of the duty cycle of the secondary side.

In order to improve the efficiency of the charger, it is necessary to make the switching tubes of the two bridge arms work in the soft switching state, that is, the requirements for the dead time are very strict, and the switching tubes cannot work if the dead time is too large or too small. In the ZVS (Zero Voltage Switching) state, the traditional method of using a single-chip microcomputer to set the dead time of the PWM driving signal is fixed, that is, it is set in the software by operating the register of the single-chip timer, and the load of the charger Changing the dead time cannot make fast and dynamic adjustments, and there is a danger of making the upper and lower bridge arms pass through. And the charging efficiency is relatively low.

Contents of the invention

The purpose of the present invention is to provide a vehicle-mounted charger with adjustable dead time based on the phase-shifted full-bridge circuit structure in view of the defects in the prior art, and to solve the lag of the existing phase-shifted full-bridge circuit through dynamic adjustment of the dead time It is difficult for the lagging arm to realize ZVS (zero voltage switching), so that the lagging arm can also work in the soft switching state under light load, thereby reducing the switching loss of the MOS tube of the full-bridge circuit during operation, and achieving the purpose of improving charging efficiency.

In order to achieve the above object, the present invention is achieved through the following technical solutions: a vehicle-mounted charger with adjustable dead time based on a phase-shifted full-bridge circuit, including a three-phase rectifier circuit, an input filter circuit, a phase-shifted full-bridge circuit and STM32 single-chip microcomputer, the phase-shifting full-bridge circuit includes DC/AC inverter, high-frequency transformer, output rectification and output filtering, and the DC/AC inverter includes four switching tubes Q1, Q2, Q3 and Q4, switching tube Q1 The leading bridge arm is formed with Q2, and the switching tubes Q3 and Q4 form a lagging bridge arm; the three-phase AC input is connected to the input end of the three-phase rectifier circuit, and the output filter in the phase-shifting full-bridge circuit is connected to the battery, which is characterized in that:

Add an output voltage detection circuit, an output current detection circuit, a dead zone dynamic adjustment circuit, and four gate-driven push-pull amplifier circuits with the same structure. The detected output voltage and output current value are output to the STM32 single-chip microcomputer, and the advanced timer of the STM32 single-chip microcomputer generates four PWM drive signals connected to the four input terminals of the dead zone dynamic adjustment circuit, and the dead zone dynamic adjustment circuit outputs four corresponding bands The PWM signals with dead time are respectively connected to the input terminals of the four gate-driven push-pull amplifier circuits, and the output terminals of the four gate-driven push-pull amplifier circuits are respectively connected to the four DC/AC inverters in the phase-shifted full-bridge circuit. Gates of switching tubes Q1, Q2, Q3, and Q4; where:

The output voltage detection circuit includes a diode D4, resistors R4, R5, and R6. The anode of the diode D4 is connected to the output end of the phase-shifting full-bridge circuit. The cathode of the diode D4 is connected to the series resistors R4, R5, and R6 in sequence, and the output end of the resistor R6 is connected to To STM32 microcontroller;

The output current detection circuit includes resistors R7, R8, R9 and capacitor C5. One end of resistor R7 is connected to the output end of the phase-shifting full bridge circuit. Resistors R8, R9 and capacitor C5 are connected in parallel, and one end of the parallel connection is connected to the other end of resistor R7. , and the other end is connected to the STM32 microcontroller after parallel connection;

The dead zone dynamic adjustment circuit includes three digital programmable finite state machines FSM_1, FSM_2, FSM_3, two counters CounterA and Counter B, two OR gates OR_1 and OR_2, four SR latches with reset and set functions SR1, SR2, SR3, SR4, the advanced timer in the STM32 single-chip microcomputer generates four PWM driving signals PWM1, PWM2, PWM3 and PWM4, among which PWM1 and PWM2 are a pair, PWM3 and PWM4 are another pair, between the two pairs The phase difference is 180°; PWM1 and PWM2 are respectively connected to the input ports in_1 and in_2 of the finite state machine FSM_3, PWM3 and PWM4 are respectively connected to the input ports in_3 and in_4 of the finite state machine FSM_1, and the clock ports and counters of the finite state machines FSM_1, FSM_2 and FSM_3 The clock ports of CounterA and Counter B, the clock ports of SR latches SR1, SR2, SR3, and SR4, and one input terminal of OR gate OR_1 and one input terminal of OR gate OR_2 are connected together with the connection clock signal fclk, finite state The output port reset_A of the machine FSM_1 is respectively connected to the input enable port en of the counter Counter B and the input reset port R of the SR latch SR4, and the output port reset_B of the finite state machine FSM_1 is respectively connected to the input enable port en of the counter CounterA and the SR lock The input reset port R of the register SR3, the output terminals set_C and set_D of the finite state machine FSM_3 are respectively connected to the input setting ports S of the SR latches SR2 and SR1, and the output terminals reset_C and reset_D of the finite state machine FSM_2 are respectively connected to the latches The input reset port R of SR2 and SR1, the output terminals Cnt of the counters CounterA and Counter B are respectively connected to the other input terminal of the OR gate OR_1 and the OR gate OR_2, and the output terminals Q of the SR latches SR1, SR2, SR3 and SR4 output PWM signals 1Y, 2Y, 3Y and 4Y with dead time;

The gate drive push-pull amplifier circuit includes NPN transistor Q5, PNP transistor Q6, resistor R3, electrolytic capacitor C3 and isolation transformer TR, the collector of transistor Q5 is connected to the power supply, the emitter of transistor Q5 is connected to the emitter of transistor Q6 and resistor R3 One end of the transistor Q6, the collector of the transistor Q6 is grounded, the base of the transistor Q5 and the base of the transistor Q6 are connected together as the input terminal of the gate drive push-pull amplifier circuit, and the input end of the dead zone dynamic adjustment circuit is connected to one of the outputs of the dead zone dynamic adjustment circuit. PWM signal 1Y, 2Y, 3Y or 4Y, the other end of the resistor R3 is connected to the positive end of the electrolytic capacitor C3, the negative end of the electrolytic capacitor C3 is connected to the primary end of the isolation transformer TR with the same name, the other end of the primary end of the transformer TR is grounded, and the secondary end of the isolation transformer TR The output of the terminal with the same name of the stage corresponds to the input terminal of the gate drive push-pull amplifier circuit, and is connected to the gate of one of the switching tubes Q1, Q2, Q3 or Q4 of the DC/AC inverter.

On the basis of the above circuit, there is also an input relay and an AC fault detection circuit. The input relay is connected between the three-phase AC input and the three-phase rectifier circuit. The output of the input relay is connected to the STM32 microcontroller through the AC fault detection circuit. The STM32 microcontroller The signal output from the control port of the control port passes through the control circuit to the input relay; the AC fault detection circuit includes the cement resistance PH and the input current sampling circuit, one end of the cement resistance PH is connected to the three-phase AC input, and the other end of the cement resistance PH is connected to the input current sampling circuit To the ADC sampling port of the STM32 microcontroller, the GPIO port output of the STM32 microcontroller controls the input relay through a control circuit composed of a diode D5, an NPN transistor TP2 and a capacitor C6, and the GPIO port output of the STM32 microcontroller is connected to one end of the capacitor C6 and the NPN transistor TP2 The base of the NPN transistor TP2 is grounded, the collector of the NPN transistor TP2 is connected to the anode of the diode D5 and one end of the cement resistor PH, the cathode of the diode D5 is connected to the other end of the cement resistor PH, and the two ends of the diode D5 are connected to Input the control terminal of the relay.

On the basis of the above circuit, there is also an output relay and a battery reverse connection detection circuit. The output relay is connected between the output filter and the battery in the phase-shifted full bridge circuit, and the battery input terminal is connected to the STM32 microcontroller through the battery reverse connection detection circuit. , the signal output by the control port of the STM32 microcontroller passes through the control circuit to the output relay; the battery reverse connection detection circuit includes diode D6, capacitor C7, Zener diode D7 and resistors R10 and R11, the input terminal of the battery is connected to the anode of diode D6, and the diode D6 The cathode of the resistor is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the GPIO port of the STM32 microcontroller, one end of the capacitor C7, the cathode of the Zener diode D7, and one end of the resistor R11. The output of the GPIO port of the STM32 microcontroller is passed by the NPN The control circuit composed of type transistor TP1, capacitor C4 and diode D3 controls the output relay. The GPIO port output of the STM32 microcontroller is connected to one end of capacitor C4 and the base of NPN type transistor TP1. The emitter of NPN type transistor TP1 is grounded. NPN type transistor TP1 The collector of the diode D3 is connected to the anode of the diode D3, and the two ends of the diode D3 are connected to the control terminal of the output relay.

The present invention has following advantage and remarkable effect:

1) The present invention can realize the ZVS (Zero Voltage Switching) of the super forearm and the lagging arm in the full load range, realize the soft switching function of the four switch tubes, and reduce the loss of the switch tubes. Increased efficiency.

2) The circuit is relatively simple, does not require complex control of a dedicated circuit, and has low cost and good reliability.

3) The dead zone dynamic adjustment circuit is different from the general dead zone dynamic adjustment circuit formed by an analog integral circuit. This invention adopts a digital programmable finite state machine and an SR latch to form a dynamic dead zone adjustment circuit. Make the adjustment of the dead time more precise.

4) The dead zone dynamic adjustment circuit can quickly adjust the dead zone time according to the output voltage and current values collected by the single-chip microcomputer, which is faster than the dead zone dynamic adjustment circuit composed of an analog integral circuit.

Description of drawings

Fig. 1 is a block diagram of a charger with a dead zone dynamic adjustment circuit structure according to the present invention;

Fig. 2 is a schematic diagram of a traditional dead time adjustment circuit;

Fig. 3 is a connection diagram of a gate-driven push-pull amplifier circuit and a full-bridge circuit;

Fig. 4 is a PWM driving signal with a dynamic dead time realized by a dead time dynamic adjustment circuit;

Fig. 5 is a schematic diagram of a digitally programmable dead zone dynamic adjustment circuit;

Fig. 6 is an output voltage and current detection circuit;

Figure 7 is an AC fault detection circuit;

Figure 8 is a battery reverse connection detection circuit.

detailed description

As shown in Figure 1, the three-phase AC input is sequentially connected to the input relay 1, the three-phase rectifier circuit 2, the input filter circuit 3, and the phase-shifted full-bridge circuit 4 (including DC/AC inverter, high-frequency transformer, output rectifier and output filter ), the output relay 5, the battery 6, the output voltage and current detection circuit 10 is connected between the output terminal of the output relay 5 and the STM32 single-chip microcomputer 12 (if the output relay is not provided, then it is connected between the phase-shifting full-bridge circuit 4 and the STM32 single-chip microcomputer 12 ), the STM32 single-chip microcomputer 12 outputs four-way PWM signals and is connected to the dead zone dynamic adjustment circuit 8, and the dead zone dynamic adjustment circuit 8 outputs four channels and four PWM signals with dead time, respectively connected to four gate drive push-pull signals with the same structure The input end of the amplifying circuit 9 and the output ends of the four gate-driven push-pull amplifier circuits 9 are respectively connected to the gates of the four switching tubes of the DC/AC inverter in the phase-shifting full-bridge circuit. The input terminal of the battery 6 is also connected to the STM32 single-chip microcomputer 12 through the battery reverse connection detection circuit 11, and the STM32 single-chip microcomputer 12 controls the shutdown of the output relay 5 through the control circuit. The output terminal of the input relay 1 is also connected to the STM32 single-chip microcomputer 12 through the AC fault detection circuit 7, and the STM32 single-chip microcomputer 12 controls the shutdown of the input relay 1 through the control circuit.

As shown in Figure 6, the output voltage and current detection circuit 10 includes two parts: an output voltage detection circuit and an output current detection circuit, the output voltage detection circuit is composed of a resistor voltage divider circuit, the output of the Schottky diode D4 is connected to the input of the voltage divider resistor R4, R4 is connected in series with resistors R5 and R6 in turn, and the output of resistor R6 is connected to the STM32 microcontroller. The output current detection circuit is connected by the output of a 510K resistor R7 to the input terminals of the current sampling resistors R8, R9 and capacitor C5. The resistance values of R8 and R9 are both 0.01Ω, R8, R9 and C5 are connected in parallel, and the output of the three is connected to STM32 MCU.

As shown in Figure 3, the DC/AC inverter in the phase-shifted full-bridge circuit 4 includes four switching tubes Q1, Q2, Q3, and Q4. Switching tubes Q1 and Q2 form a leading bridge arm, and switching tubes Q3 and Q4 form a lagging bridge arm. . The three-phase rectification circuit 2 converts alternating current into direct current. The voltage passing through the three-phase rectification circuit 2 is filtered by the input filter circuit 3 to filter out high-frequency small signals. The input filter circuit 3 is composed of a resistor and two electrolytic capacitors connected in parallel with the output of the three-phase rectifier. The withstand voltage and capacitance of the electrolytic capacitor are 400V/560uF, and the voltage after the input filter 3 is provided to the phase-shifted full-bridge circuit 4 The drains of the two MOS transistors Q1 and Q4 are used as the bus voltage. Lr is the resonant inductance of the primary side of the transformer and is connected to the primary side of the high frequency transformer T1. R1 and C1 are connected in series and D1 in parallel, and R2 and C2 are connected in series and D2 in parallel to form a full-wave rectification circuit, which rectifies the output voltage of the secondary side of the transformer. The gate-driven push-pull amplifier circuit 9 is composed of an NPN transistor Q5 and a PNP transistor Q6 connected in series. The bases of the two NPN and PNP transistors are used as the input terminals for the output signal of the dynamic adjustment circuit in the dead zone, and the emitters of the two transistors output A voltage dividing resistor R3 and a DC blocking capacitor C3 are connected in series, and a transformer TR is connected to the output end of the DC blocking capacitor to electrically isolate the amplified signal, and the isolated output controls a switching tube in the DC/AC inverter on and off. The figure only shows one gate-driven push-pull amplifier circuit, whose input terminal is connected to the 2Y signal output by the dead zone dynamic adjustment circuit, and the isolated output controls the Q2 tube in the DC/AC inverter, and the other three gate-driven push-pull amplifier circuits The input terminals of the pull amplifier circuit are respectively connected to the 1Y, 3Y, and 4Y signals output by the dead zone dynamic adjustment circuit, and the isolated outputs control the Q1 tube, Q3 tube, and Q4 tube in the DC/AC inverter respectively.

As shown in Figure 5, the STM32 single-chip microcomputer can control the level of the GPIO port of the corresponding STM32 single-chip microcomputer connected to the dead zone dynamic adjustment circuit according to the output voltage and current values collected by the output voltage and current detection circuit 10, and perform the finite state machine Programming dynamically sets the width of the dead time, and the SR latch latches the waveform output by the finite state machine and outputs it to the input terminal of the push-pull amplifier circuit. The advanced timer of STM32 MCU generates four complementary PWM driving signals with a frequency of 45KHz. A pair of PWM1 and PWM2, a pair of PWM3 and PWM4, the phase difference of each pair of signal waveforms is 180°, the signal is amplified by a push-pull amplifier circuit and isolated by a transformer as the gate of the super-forearm and lagging-arm MOS tube of the phase-shifting full-bridge circuit The driving voltage controls the turn-on and turn-off of the four switch tubes, and adjusts the size of the output voltage and output current by controlling the phase shift of the gate drive signal of the lead arm and the lag arm MOS tube. When the load changes, the STM32 MCU controls the phase shift of the PWM signal according to the collected voltage and current to maintain the output voltage and current unchanged, and then adjusts the dead time through the dead zone dynamic adjustment circuit 8 to prevent the phase shifting of the full bridge circuit. The upper and lower tubes of the two bridge arms are directly connected to ensure that the dead time of the phase-shifted full-bridge circuit satisfies that the four switching tubes work in the ZVS (Zero Voltage Switching) state. The dead zone dynamic adjustment circuit 8 consists of three digital programmable finite state machines FSM_1, FSM_2, FSM_3 (FSM_3 is a set finite state machine, and the rest are reset finite state machines), two counters CounterA, Counter B, two OR gates OR_1, OR_2 and four SR latches with reset and set functions SR1, SR2, SR3, SR4 constitute. The four-way PWM signals PWM1, PWM2, PWM3, and PWM4 generated by the STM32 microcontroller advanced timer are input to the input ports in_1, in_2, in_3, and in_4 of the finite state machine FSM_3, FSM_1, and fclk is the clock signal of the dead zone dynamic adjustment circuit. The clock signals are respectively connected to the clock ports of FSM_1, FSM_2, FSM_3, CounterA, CounterB, SR1, SR2, SR3, SR4 and one of the input ports of OR_1, OR_2. The output port reset_A of FSM_1 is respectively connected to the input enable port en of Counter B and the input reset port R of SR4, and the output port reset_B of FSM_1 is respectively connected to the input enable port en of CounterA and the input reset port R of SR3. The output terminals Cnt of the counters CounterA and Counter B are connected to one input terminal of the OR gates OR_1 and OR_2 respectively. The output terminals of OR_1 and OR_2 are connected to the set input terminals S of SR4 and SR3 respectively. The output terminals reset_C and reset_D of FSM_2 are connected to the input reset ports R of SR2 and SR1 respectively. The output terminals set_C and set_D of FSM_3 are connected to the input setting ports S of SR2 and SR1 respectively. The STM32 microcontroller can control the level of the GPIO port of the corresponding STM32 microcontroller according to the output voltage and current values collected by the output voltage and current detection circuit. The GPIO port is connected to the dead zone dynamic adjustment circuit to program the finite state machine dynamically. Set the dead time width of PWM1, PWM2, PWM3, PWM4, and four driving signals. The SR latch latches the waveform output by the finite state machine and then outputs the phase-shifted PWM signals 1Y, 2Y, 3Y, 4Y to the input terminals of the four push-pull amplifier circuits. The four-way driving signals generate four different dead-times according to different loads (as shown in FIG. 4 ), which are respectively T0, T1, T2, and T3. The dead-times decrease sequentially. The dead time has an upper limit and a lower limit respectively, and the upper limit and the lower limit cannot be exceeded under any circumstances, otherwise the energy of the primary side resonant inductance and the inductance in the output filter circuit cannot fully charge and discharge the parasitic capacitance of the MOS tube. It is difficult to realize ZVS (Zero Voltage Switching), and the switching tube will work in a hard switching state and the switching loss will increase. 1Y and 2Y are the driving signal waveforms of the advanced forearm, and 3Y and 4Y are the driving signal waveforms of the lagging arm. The phase shifts of 1Y, 3Y and 2Y, 4Y are Tphase. The STM32 microcontroller adjusts the output voltage and current by adjusting the size of the two diagonal tubes Tphase. That is, increasing Tphase can increase the output voltage and current, and decreasing Tphase can decrease the output voltage and current. As shown in Figure 3, 2Y is amplified through the gate-driven push-pull amplifier circuit 9, and then isolated and driven by the transformer TR to drive the gate G2 of the leading bridge arm Q2. 1Y, 3Y, and 4Y are amplified and isolated by the same push-pull amplifier circuit Drives the gates G1, G3, G4 of Q1, Q3, Q4.

As shown in FIG. 7 , the AC fault detection circuit 7 is used to detect whether the instantaneous surge current of the AC input is too large. The AC fault detection circuit is composed of a 390Ω cement resistor PH to suppress surge current and an input current sampling circuit. The output of the PH is connected to the input of the input sampling circuit, and the output of the input sampling circuit is connected to the ADC sampling port of the STM32 microcontroller. The anode of the diode D5 is connected to the collector of the Darlington transistor TP2, the collector of the TP2 and the cathode of the diode D5 are connected to the control terminal of the input relay, and the base of the transistor TP2 is connected to the GPIO of the STM32 microcontroller. At the same time, a 0.1uF capacitor C6 is connected between the base and emitter of TP2. The moment the charger is powered on and starts working, the STM32 single-chip computer detects whether the current exceeds the threshold current through the AC fault detection circuit. When the startup surge current exceeds the threshold current, the STM32 single-chip transfers to the protection program, and the Darlington transistor connected to the input relay control terminal The base of TP2 is set to a low level by the GPIO port of the STM32 microcontroller, and the transistor TP2 is turned off to turn off the input relay 1.

As shown in Figure 8, the battery reverse connection detection circuit 11 is connected by the input terminal of the Schottky diode D6 to the input terminal of the battery, the output of D6 is connected to the input of a 2.2K resistor R10, and the output of the resistor R10 is respectively connected to the STM32 microcontroller. The GPIO port and the input terminal of the parallel network connected by capacitor C7, 18V Zener diode D7, and resistor R11, and the control port of the STM32 microcontroller are connected to the output relay through the circuit (TP1, D3, C4) that controls the output relay switch. The moment the charger is powered on and starts to work, the STM32 single-chip microcomputer detects the polarity of the battery through the battery reverse connection detection circuit. If the battery reverse connection is detected, the corresponding GPIO port is controlled to be low and the output relay is turned off (Figure 6). When the STM32 single-chip microcomputer detects output overvoltage or overcurrent through the output voltage and current detection circuit, control the corresponding GPIO port to be low level and turn off the Darlington transistor TP1, the collector of TP1 and the anode of the diode D3 and the control terminal of the output relay The cathode of the diode D3 is also connected to the control terminal of the output relay, and a capacitor C4 is also connected between the base and the emitter of the TP1. When TP1 is turned off, the control terminal of the relay also controls the relay to turn off accordingly.

The working principle and process of the present invention are illustrated in conjunction with FIG. 3: the four-way complementary PWM drive signals output by the dead zone adjustment circuit are amplified and isolated by the push-pull amplifier circuit 9, and are used as the gate drive signal of the MOS tube to realize the MOS tube. On and off. Among them, Uin is the bus voltage after three-phase rectification and filtering, and Uo is the output DC voltage. Vlr is the voltage across the resonant inductor Lr. When G1 and G3 are high level, G2 and G4 are low level. Q1 and Q3 are turned on, and Q2 and Q4 are turned off. When G2 and G4 are high level, G1 and G3 are low level. Q2 and Q4 are turned on, and Q1 and Q3 are turned off. When Q1 and Q3 are turned on, the Vds of Q1 and Q3 are zero to achieve zero-voltage conduction. When Q1 and Q3 are turned off, due to the existence of resonant inductance and the parallel parasitic capacitance inside the MOS tube, resonance occurs to charge and discharge the capacitor to make the MOS The voltage drop across the tube is zero to achieve zero voltage turn-off. The working process of Q2 and Q4 is the same as that of Q1 and Q3. The advanced timer of the STM32 microcontroller 12 generates a PWM signal with a phase shift, so that the Q1 and Q2 tubes are turned on ahead of the Q3 and Q4, and the output voltage Uo is adjusted by controlling the magnitude of the phase shift.

The invention can realize the ZVS (Zero Voltage Switching) of the leading arm and the lagging arm in the full load range, thereby improving the efficiency. The soft switching function of the four switching tubes is realized to reduce the loss of the switching tubes. At the same time, a method that can adjust the dead time of the PWM driving signal through the dead time dynamic adjustment circuit according to the change of the output voltage and current is proposed. The dead zone dynamic adjustment circuit of the present invention is different from the dead zone dynamic adjustment circuit formed by an analog integration circuit, and a digital programmable finite state machine and an SR latch are used to form a dynamic dead zone adjustment circuit, which can make the adjustment of the dead zone time more accurate. For precision and speed.

Claims (3)

1. one kind is based on the adjustable Vehicular charger of phase whole-bridging circuit Dead Time, including the three phase rectifier electricity being sequentially connected Road, input filter circuit, phase whole-bridging circuit, and also include stm32 single-chip microcomputer, phase whole-bridging circuit include dc/ac inverter, High frequency transformer, output rectification and output filtering, dc/ac inverter therein includes four switching tubes q1, q2, q3 and q4, opens Close pipe q1 and q2 and constitute leading-bridge, switching tube q3 and q4 constitutes lagging leg；Three-phase alternating current input connects rectified three-phase circuit Input, in phase whole-bridging circuit output filtering connect battery it is characterised in that:

Set up output voltage detecting circuit, output current detection circuit, dead band dynamic regulating circuit and four structure identical grid Push-pull amplifier circuit, output voltage detecting circuit and output current detection circuit is driven to be connected to the output of phase whole-bridging circuit End, the output voltage detecting and output current value is exported to stm32 single-chip microcomputer, the senior intervalometer of stm32 single-chip microcomputer produces Raw four road pwm drive signals connect to four inputs of dead band dynamic regulating circuit, and dead band dynamic regulating circuit exports four tunnels The corresponding pwm signal with Dead Time is respectively connecting to the input that four grid drive push-pull amplifier circuit, and four grid drive The outfan of dynamic push-pull amplifier circuit connect respectively four switching tube q1 of dc/ac inverter in phase whole-bridging circuit, q2, q3, The grid of q4；Wherein:

Output voltage detecting circuit includes diode d4, resistance r4, r5, r6, and the anode of diode d4 connects phase whole-bridging circuit Outfan, the negative electrode of diode d4 is sequentially connected resistance r4, r5, r6 of series connection, and the outfan of resistance r6 connects mono- to stm32 Piece machine；

Output current detection circuit includes resistance r7, r8, r9 and electric capacity c5, and one end of resistance r7 connects the defeated of phase whole-bridging circuit Go out end, resistance r8, r9 and electric capacity c5 three are in parallel, and the one end after parallel connection connects the other end of resistance r7, another one end after parallel connection Connect to stm32 single-chip microcomputer；

Dead band dynamic regulating circuit includes three numerals programmable finite state machine fsm_1, fsm_2, fsm_3, two countings Device counter a and counter b, two OR gate or_1 and or_2, four carry the sr latch resetting with set function Sr1, sr2, sr3, sr4, the senior intervalometer in stm32 single-chip microcomputer produce four road pwm drive signal pwm1, pwm2, pwm3 and Pwm4, wherein pwm1 and pwm2 are a pair, and pwm3 and pwm4 is another right, two between 180 ° of phase contrast；Pwm1 and pwm2 divides Not Lian Jie finite state machine fsm_3 input port in_1 and in_2, pwm3 and pwm4 be connected to limit state machine fsm_1 Input port in_3 and in_4, the clock port of finite state machine fsm_1, fsm_2 and fsm_3, enumerator counter a and One input of the clock port of counter b, the clock port of sr latch sr1, sr2, sr3, sr4 and OR gate or_1 And an input of OR gate or_2 links together and is connected the connection of clock signal fclk, the output of finite state machine fsm_1 The port reset_a input enable port en of linkage counter counter b and the input reseting port of sr latch sr4 respectively Input enable port en and sr of the output port reset_b difference linkage counter counter a of r, finite state machine fsm_1 The input reseting port r of latch sr3, outfan set_c and set_d of finite state machine fsm_3 connect sr latch respectively The input set port s of sr2 and sr1, outfan reset_c and reset_d of finite state machine fsm_2 connect latch respectively The input reseting port r of sr2 and sr1, the outfan cnt of enumerator counter a and counter b connect OR gate or_1 respectively And another input of OR gate or_2, when the outfan q of sr latch sr1, sr2, sr3 and sr4 exports respectively with dead band Between pwm signal 1y, 2y, 3y and 4y；

Grid drive push-pull amplifier circuit to include npn audion q5, pnp audion q6, resistance r3, electrochemical capacitor c3 and isolation The colelctor electrode of transformator tr, audion q5 connects power supply, the emitter stage of emitter stage connecting triode q6 of audion q5 and resistance One end of r3, the grounded collector of audion q6, the base stage of audion q5 is connected together as grid with the base stage of audion q6 The input driving push-pull amplifier circuit connects one of pwm letter with Dead Time that dead band dynamic regulating circuit exports Number 1y, 2y, 3y or 4y, the other end of resistance r3 connects the anode of electrochemical capacitor c3, and the negative terminal of electrochemical capacitor c3 connects isolation and becomes The primary Same Name of Ends of depressor tr, the primary other end ground connection of transformator tr, the Same Name of Ends output of tr level of isolating transformer and grid The input driving push-pull amplifier circuit connects correspondence, connects dc/ac inverter one of switching tube q1, q2, q3 or q4 Grid.

2. according to claim 1 based on the adjustable Vehicular charger of phase whole-bridging circuit Dead Time it is characterised in that: It is additionally provided with input relay and ac fault detection circuit, input relay is connected to three-phase alternating current input and rectified three-phase circuit Between, the output of input relay connects to stm32 single-chip microcomputer, the control of stm32 single-chip microcomputer through ac fault detection circuit The signal of port output is through control circuit to input relay；Ac fault detection circuit includes cement resistor ph and input electricity Stream sample circuit, one end of cement resistor ph connects three-phase alternating current input, and the other end of cement resistor ph is adopted through input current Sample circuit connects to the adc sample port of stm32 single-chip microcomputer, the gpio port output of stm32 single-chip microcomputer through by diode d5, The control circuit control input relay that npn audion tp2 and electric capacity c6 is constituted, the gpio port output of stm32 single-chip microcomputer Connect one end of electric capacity c6 and the base stage of npn audion tp2, the grounded emitter of npn audion tp2, npn audion The colelctor electrode of tp2 connects the anode of diode d5 and one end of cement resistor ph, and the negative electrode of diode d5 connects cement resistor ph The other end, the two ends of diode d5 connect the control end of input relay.

3. according to claim 1 and 2 based on the adjustable Vehicular charger of phase whole-bridging circuit Dead Time, its feature exists In: it is additionally provided with output relay and battery inverted connection detecting circuit, output relay is connected to the output filter in phase whole-bridging circuit Between ripple and battery, cell input terminal connects to stm32 single-chip microcomputer, the control of stm32 single-chip microcomputer through battery inverted connection detecting circuit The signal of port processed output is through control circuit to output relay；Battery inverted connection detecting circuit include diode d6, electric capacity c7, Zener diode d7 and resistance r10 and r11, the input of battery connects the anode of diode d6, and the negative electrode of diode d6 is even The gpio port of one end of connecting resistance r10, the other end of resistance r10 and stm32 single-chip microcomputer, one end of electric capacity c7, voltage stabilizing two pole One end of the negative electrode of pipe d7 and resistance r11 links together, and the gpio port output of stm32 single-chip microcomputer is through by npn three The control circuit that pole pipe tp1, electric capacity c4 and diode d3 are constituted controls output relay, and the gpio port of stm32 single-chip microcomputer is defeated Go out to connect one end of electric capacity c4 and the base stage of npn audion tp1, the grounded emitter of npn audion tp1, npn three pole The colelctor electrode of pipe tp1 connects the anode of diode d3, and the two ends of diode d3 connect the control end of output relay.