CN104576507B - Three-dimension packaging method based on silicon hole technology - Google Patents
Three-dimension packaging method based on silicon hole technology Download PDFInfo
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- CN104576507B CN104576507B CN201310504865.7A CN201310504865A CN104576507B CN 104576507 B CN104576507 B CN 104576507B CN 201310504865 A CN201310504865 A CN 201310504865A CN 104576507 B CN104576507 B CN 104576507B
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 20
- 239000010703 silicon Substances 0.000 title claims abstract description 20
- 238000005516 engineering process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 134
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000000126 substance Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 238000000708 deep reactive-ion etching Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of three-dimension packaging method based on silicon hole technology, including：Wafer is provided；Through-hole is formed in wafer frontside；Sacrificial layer is filled into through-hole；After filling sacrificial layer into through-hole, semiconductor devices is formed in wafer frontside；Form the interlayer dielectric layer being covered on wafer frontside, sacrificial layer and semiconductor devices；The opening for exposing sacrificial layer is formed in interlayer dielectric layer；Removal opening lower section, the sacrificial layer in through-hole；Full metal is filled into through-hole and opening, to form conductive plunger.Technical scheme of the present invention had both improved the electric conductivity of conductive plunger, and the metal in turn avoided in conductive plunger pollutes the manufacture craft of semiconductor devices, and then improves the electric property of encapsulating structure.
Description
Technical field
The present invention relates to field of semiconductor package, more particularly to a kind of three-dimension packaging method based on silicon hole technology.
Background technology
Silicon hole（Through Silicon Via, abbreviation TSV）Technology is between a kind of realization chip and chip, wafer
The interconnection technique of line conduction between wafer or between wafer and chip.Salient point is bonded and used with previous IC package
Superimposing technique it is different, density that silicon hole technology can be such that chip is stacked in three-dimensional is maximum, appearance and size minimum.
It is produced on the sequence in entire three-dimension packaging flow, the three-dimension packaging method based on silicon hole technology according to silicon hole
It is divided into three kinds, respectively first through-hole technology（via first）Three-dimension packaging method, middle through-hole technology（via middle）Three
Tie up packaging method, rear through-hole technology（via last）Three-dimension packaging method.Wherein, the three-dimension packaging side of existing first through-hole technology
Method includes：Through-hole is formed in wafer, conductive material is filled into through-hole, to form conductive plunger；It is formed after conductive plunger,
Semiconductor devices is formed on wafer and metal interconnection structure, the metal interconnection structure are electrically connected with conductive plunger.
It is required when making semiconductor devices on wafer without metallic pollution, the conduction material filled in the through-hole in order to prevent
Material can influence the making of Subsequent semiconductor device, and the conductive material filled in the through-hole is polysilicon, rather than metal.But
It is that since the electric conductivity of polysilicon is bad, thus the electric property of encapsulating structure can be influenced.
Invention content
The problem to be solved in the present invention is：In the three-dimension packaging method of existing elder generation's through-hole technology, filling in the through-hole of wafer
Conductive material electric conductivity it is bad, affect the electric property of encapsulating structure.
To solve the above problems, the present invention provides a kind of three-dimension packaging methods based on silicon hole technology, including：
Wafer is provided；
Through-hole is formed in the wafer frontside；
Sacrificial layer is filled into the through-hole；
After filling sacrificial layer into the through-hole, semiconductor devices is formed in the wafer frontside；
Form the interlayer dielectric layer being covered on the wafer frontside, sacrificial layer and semiconductor devices；
The opening for exposing the sacrificial layer is formed in the interlayer dielectric layer；
It removes below the opening, the sacrificial layer in the through-hole；
The full metal of filling into the through-hole and opening, to form conductive plunger.
Optionally, the metal is copper.
Optionally, the material of the sacrificial layer is amorphous carbon.
Optionally, before the wafer frontside forms semiconductor devices, further include：Form the quarter for covering the sacrificial layer
Lose barrier layer.
Optionally, the material of the etching barrier layer is silica.
Optionally, before filling sacrificial layer into the through-hole, further include：It is formed on the bottom of the through-hole and side wall
Insulating layer.
Optionally, the material of the insulating layer is silica, forming method is thermal oxidation process.
The present invention also provides three-dimension packaging method of the another kind based on silicon hole technology, including：
Wafer is provided；
Through-hole is formed in the wafer frontside；
Sacrificial layer is filled into the through-hole；
After filling the sacrificial layer, semiconductor devices is formed in the wafer frontside；
Form the interlayer dielectric layer being covered on the wafer frontside, sacrificial layer and semiconductor devices；
It is formed after the interlayer dielectric layer, from wafer described in thinning back side of silicon wafer, until exposing the sacrificial layer；
Removal is located at the sacrificial layer in the through-hole；
Metal is filled into the through-hole, to form conductive plunger.
Optionally, the metal is copper.
Optionally, the material of the sacrificial layer is amorphous carbon.
Optionally, before the wafer frontside forms semiconductor devices, further include：Form the quarter for covering the sacrificial layer
Lose barrier layer.
Optionally, the material of the etching barrier layer is silica.
Optionally, before filling sacrificial layer into the through-hole, further include：It is formed on the bottom of the through-hole and side wall
Insulating layer.
Optionally, the material of the insulating layer is silica, forming method is thermal oxidation process.
Compared with prior art, technical scheme of the present invention has the following advantages：
The technical program first fills sacrificial layer, then in wafer frontside after wafer frontside forms through-hole in through-hole
Semiconductor devices is formed, is formed after semiconductor devices, the sacrificial layer being filled in through-hole is replaced with into metal to form conduction
Plug had both improved the electric conductivity of conductive plunger, in turn avoided making work of the metal in conductive plunger to semiconductor devices
Skill pollutes, and then improves the electric property of encapsulating structure.
Further, it before filling sacrificial layer in through-hole, is formed in the bottom of through-hole and side wall using thermal oxidation process
High-quality material is the insulating layer of silica.
Description of the drawings
Fig. 1 to Fig. 7 be in the first embodiment of the present invention encapsulating structure in the cross-sectional view of each production phase；
Fig. 8 to Figure 12 is that cross-section structure of the encapsulating structure in each production phase is illustrated in the second embodiment of the present invention
Figure.
Specific implementation mode
As previously mentioned, in the three-dimension packaging method of existing elder generation's through-hole technology, the conductive material filled in the through-hole of wafer is led
Electrical property is bad, affects the electric property of encapsulating structure.
Compared to polysilicon, the electric conductivity of metal is more preferable.But if first directly filling metal in the through-hole of wafer,
The metal is easy to pollute the manufacturing process of Subsequent semiconductor device, and then affects the electric property of encapsulating structure.
In order to solve this problem, the present invention provides a kind of improved three-dimension packaging methods based on silicon hole technology, should
Method first fills sacrificial layer after wafer frontside forms through-hole in through-hole, then forms semiconductor devices in wafer frontside,
It is formed after semiconductor devices, the sacrificial layer being filled in through-hole is replaced with into metal to form conductive plunger, had both improved and has led
The electric conductivity of electric plug, the metal in turn avoided in conductive plunger pollute the manufacturing process of semiconductor devices, in turn
Improve the electric property of encapsulating structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
First embodiment
As shown in Figure 1, providing wafer 100.Wafer 100 is bare silicon wafer, has front S1 and back side S2, wafer 100 is just
Face S1 is used to form semiconductor devices.
In the present embodiment, wafer 100 is Silicon Wafer.
Shown in Fig. 1, through-hole 101 is formed in wafer frontside S1, the depth of through-hole 101 is less than the thickness of wafer 100
Degree.
In the present embodiment, the forming method of through-hole 101 includes：Graphical photoresist layer is formed above wafer frontside S1
（It is not shown）, which defines the position of through-hole 101；It is performed etching as mask using the graphical photoresist layer,
To form through-hole 101 in wafer 100；Then, the graphical photoresist layer is removed.
In a particular embodiment, the lithographic method can be deep reactive ion etching（Deep Reactive Ion
Etching, abbreviation DRIE）.In other embodiments, the method for Laser drill can also be utilized to form through-hole in wafer 100
101。
Shown in Fig. 1, insulating layer 110 is formed in the bottom and side wall of through-hole 101.
In the present embodiment, the material of insulating layer 110 is silica, and the forming method of insulating layer 110 is thermal oxidation process.
In other embodiments, insulating layer 110 can also be formed using chemical vapor deposition method.It is formed compared to other methods
Insulating layer 110, thermal oxidation process is formed by 110 better quality of insulating layer.
As shown in Fig. 2, filling sacrificial layer 120 into through-hole 101.
In the present embodiment, the material of sacrificial layer 120 is amorphous carbon（amorphous carbon）.Into through-hole 101
Filling sacrificial layer 120 method include：It forms covering wafer frontside S1 and fills the sacrificial material layer of full through-hole 101；It is sacrificial to this
Domestic animal material layer carve, and is covered in the sacrificial material layer on wafer frontside S1 with removal, and make the sub-fraction of through-hole 101 not
Layer 120 is sacrificed to fill up.
In the present embodiment, the forming method of amorphous carbon layer is plasma activated chemical vapour deposition（PECVD）.
Shown in Fig. 2, the etching barrier layer 130 being covered on sacrificial layer 120 is formed.
In the present embodiment, the material of etching barrier layer 130 is silica.The forming method of etching barrier layer 130 includes：
The protected material bed of material being covered on wafer frontside S1 and sacrificial layer 120 is formed, the forming method of the protected material bed of material is plasma
Body chemical vapor phase growing（PECVD）；Chemical mechanical grinding is carried out to the protected material bed of material, until removal is covered in wafer frontside S1
On the protected material bed of material, the remaining protected material bed of material constitutes the etching barrier layer 130 being located in groove.
In other embodiments, etching barrier layer 130 can also be not filled by in groove, as long as so that etching barrier layer
130 are covered in 120 top of sacrificial layer.
As shown in figure 3, forming semiconductor devices 140 in wafer frontside S1.
Semiconductor devices 140 is included in semiconductor front end technique（FEOL）The middle all devices to be formed.In the present embodiment
In, semiconductor devices 140 is MOSFET.In other embodiments, the semiconductor devices can also include other kinds of member
Part, such as resistance, capacitance, inductance, MEMS.
In 140 manufacturing process of semiconductor devices, etching barrier layer 130 can prevent sacrificial layer 120 to be etched.
Shown in Fig. 3, formation is covered on wafer frontside S1, etching barrier layer 130 and semiconductor devices 140
Interlayer dielectric layer 150.
Interlayer dielectric layer 150 can be formed by stacking by one layer of dielectric layer or multilayer dielectricity layer.In the present embodiment, interlayer
The material of dielectric layer 150 is silica.
Shown in Fig. 3, the conductive plunger being electrically connected with semiconductor devices 140 is formed in interlayer dielectric layer 150
160。
As shown in figure 4, forming the opening 151 for exposing sacrificial layer 120 in interlayer dielectric layer 150.
In the present embodiment, 151 forming method of being open includes：Graphical photoresist is formed on interlayer dielectric layer 150
Layer, the graphical photoresist layer define the position of opening 151；It is performed etching as mask using the graphical photoresist layer, with removal
The interlayer dielectric layer 150 and etching barrier layer 130 of 120 top of sacrificial layer（As shown in Figure 3）；Then, the graphical photoetching is removed
Glue-line.
Shown in Fig. 4, the sacrificial layer 120 in through-hole 101 is removed.
In the present embodiment, ashing is utilized（ashing）Method removes sacrificial layer 120.Gas used by the ashing method
Body includes oxygen.
The material of sacrificial layer 120 is agraphitic carbon, and the chemical property of amorphous carbon is highly stable, will not be with wafer 100
Other layers react, and are also easy to removal totally, and therefore, introducing sacrificial layer 120 in the making processing procedure of encapsulating structure will not
The electric property of encapsulating structure is impacted.
As shown in figure 5, metal is filled into through-hole 101 and opening 151, to form conductive plunger 170.
In the present embodiment, the forming method of conductive plunger 170 includes：It forms covering interlayer dielectric layer 150 and fills logical
The metal material layer of hole 101 and opening 151, the forming method of the metal material layer can be physical vapour deposition (PVD) or plating；It is right
The metal material layer carries out chemical mechanical grinding, and the metal material layer on interlayer dielectric layer 150 is covered in removal, remaining to fill out
It fills and constitutes conductive plunger 170 in through-hole 101 and the metal material layer of opening 151.
In the three-dimension packaging method of existing elder generation's through-hole technology, the conductive material being filled in through-hole is polysilicon, and at this
In technical solution, the conductive material being filled in through-hole is metal, since the electric conductivity of metal is better than the electric conductivity of polysilicon
Can, therefore, the electric property that encapsulating structure is formed by using the technical program is improved.In addition, filling metal in through-hole
Before, since the semiconductor devices on wafer has completed, thus avoiding metal can be to the making work of semiconductor devices
Skill pollutes.
In the present embodiment, the metal being filled in through-hole 101 and opening 151 is copper.The electric conductivity and hot property of copper
It is superior to polysilicon, is conducive to the electric property for improving encapsulating structure.In this case, into through-hole 101 and opening 151
Before filling the metal material layer, further include：Formation is covered in interlayer dielectric layer 150, the bottom of through-hole 101 and side wall, opens
Diffusion impervious layer on 151 side walls of mouth（It is not shown）, metal seed layer on the diffusion impervious layer（It is not shown）.
As shown in fig. 6, forming metal interconnection structure 180 on interlayer dielectric layer 150.Metal interconnection structure 180 includes electricity
The interconnection line and conductive plunger of connection（It does not identify）.Metal interconnection structure 180 can be one layer of metal interconnection structure or multilayer gold
Belong to interconnection structure.Metal interconnection structure 180 is electrically connected with conductive plunger 170.
As shown in Figure 7（Dotted portion indicates the part being removed in wafer thinning process in figure）, subtract from wafer rear S2
Thin wafer 100, until wafer 100 reaches predetermined thickness.
In thinned wafer 100, first in wafer frontside adhesive silicon wafer carrier（carrier wafer）, then to wafer
Back side S2 is ground, and after wafer 100 is thinned to predetermined thickness, which is opened with wafer separate.
Second embodiment
Between second embodiment and first embodiment difference lies in：In a second embodiment,
In conjunction with shown in Fig. 3 and Fig. 8, sacrificial layer 120 is filled into through-hole 101 and is formed after etching barrier layer 130,
Semiconductor devices 140 is formed in wafer frontside S1；Then, covering wafer frontside S1, semiconductor devices 140 and etch stopper are formed
The interlayer dielectric layer 150 of layer 130；Then, the conduction being electrically connected with semiconductor devices 140 is formed in interlayer dielectric layer 150 to insert
Plug 160；Then, metal interconnection structure 180 is formed on interlayer dielectric layer 150；
As shown in Figure 9（Dotted portion indicates the part being removed in wafer thinning process in figure）, subtract from wafer rear S2
Thin wafer 100, until exposing sacrificial layer 120, in thinned wafer 100, first in wafer frontside adhesive silicon wafer carrier
（carrier wafer）, then wafer rear S2 is ground, until wafer 100 is thinned to predetermined thickness；
As shown in Figure 10, the sacrificial layer 120 and etching barrier layer 130 in through-hole 101 are removed（As shown in Figure 9）；
As shown in figure 11, the interlayer dielectric layer 150 of 101 lower section of removal through-hole, to form opening in interlayer dielectric layer 150
151；
As shown in figure 12, metal is filled into opening 151 and through-hole 101, to form conductive plunger 170, conductive plunger 170
It is electrically connected with metal interconnection structure 180, is formed after conductive plunger 170, wafer carrier and wafer 100 are separated.
In the present invention, each embodiment uses progressive literary style, the difference of emphasis description and previous embodiment each to implement
Same section in example is referred to previous embodiment.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of three-dimension packaging method based on silicon hole technology, which is characterized in that including：
Wafer is provided；
By etching through-hole is formed in the wafer frontside；
Sacrificial layer is filled into the through-hole；
After filling sacrificial layer into the through-hole, semiconductor devices is formed in the wafer frontside；
Form the interlayer dielectric layer being covered on the wafer frontside, sacrificial layer and semiconductor devices；
After forming semiconductor devices and interlayer dielectric layer, before forming metal interconnection structure, by etching in the layer
Between opening is formed in dielectric layer, expose the through-hole in the sacrificial layer；
It removes below the opening, the sacrificial layer in the through-hole；
Formed semiconductor devices and removal sacrificial layer after, before forming metal interconnection structure, to the through-hole and open
The full metal of filling in mouthful, to form conductive plunger；
After forming conductive plunger, metal interconnection structure is formed on interlayer dielectric layer；
After forming conductive plunger and forming metal interconnection structure, from thinning back side of silicon wafer wafer, exposure conductive plunger.
2. three-dimension packaging method according to claim 1, which is characterized in that the metal is copper.
3. three-dimension packaging method according to claim 1, which is characterized in that the material of the sacrificial layer is amorphous carbon.
4. three-dimension packaging method according to claim 1, which is characterized in that form semiconductor devices in the wafer frontside
Before, further include：Form the etching barrier layer for covering the sacrificial layer.
5. three-dimension packaging method according to claim 4, which is characterized in that the material of the etching barrier layer is oxidation
Silicon.
6. three-dimension packaging method according to claim 1, which is characterized in that before filling sacrificial layer into the through-hole,
Further include：Insulating layer is formed on the bottom of the through-hole and side wall.
7. three-dimension packaging method according to claim 6, which is characterized in that the material of the insulating layer is silica, shape
It is thermal oxidation process at method.
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| CN201310504865.7A CN104576507B (en) | 2013-10-23 | 2013-10-23 | Three-dimension packaging method based on silicon hole technology |
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| CN113948457A (en) * | 2021-10-14 | 2022-01-18 | 赛莱克斯微系统科技（北京）有限公司 | Method for manufacturing semiconductor device |
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| US8791009B2 (en) * | 2011-06-07 | 2014-07-29 | International Business Machines Corporation | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via |
| CN102832161B (en) * | 2011-06-13 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through-silicon-via |
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