CN104575619B - A kind of restorative procedure of dram chip - Google Patents
A kind of restorative procedure of dram chip Download PDFInfo
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- CN104575619B CN104575619B CN201410797472.4A CN201410797472A CN104575619B CN 104575619 B CN104575619 B CN 104575619B CN 201410797472 A CN201410797472 A CN 201410797472A CN 104575619 B CN104575619 B CN 104575619B
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000012360 testing method Methods 0.000 abstract description 13
- 238000011084 recovery Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to a kind of restorative procedure of dram chip, using the way for expanding virtual address position, by non-2n(n is equal to integer) individual number of addresses is fitted into the virtual address position expanded, and the mark of chip design address boundary is carried out with virtual address position；This method really reflects the demand of chip designer, is addressed a series of problems related to address boundary positioning in chip testing.For the present invention because two virtual address positions of expansion will not produce any influence to original m positions chip X addresses, therefore, the normally addressing of chip is unaffected, and then ensure that the correct access of test chip address.
Description
Technical field
The present invention relates to a kind of restorative procedure of dram chip.
Background technology
When the design of dram chip is no longer with traditional 2nWhen (n is equal to integer) individual number of addresses is plan boundary, tester
Device will be unable to position the plan boundary of chip, and existing solution method is to give up the true address border of chip, still
Using 2nIndividual number of addresses is the way on border.The way can not really reflect the demand of chip designer, and then trigger core
A series of problems related to address boundary positioning in built-in testing, such as：Dram chip recovery scenario can not be implemented, topological
Write-in is it cannot be guaranteed that accuracy of chip testing result etc..
As shown in figure 1,1.1 in Fig. 1 give chip designer's recovery scenario of offer, it is assumed that the DRAM has m (m
Equal to integer) position X addresses, i.e. the X address numbers of the chip are 2mIt is individual, and 2mIndividual address is evenly distributed in 3 independent reparation areas
Domain (region 0, region 1 and region 2), therefore the X number of addresses of each independent restoring area is 2m/ 3, a redundancy is also with identical
Rule is by trisection, and each decile can independently repair the fail address in the region.Assuming that the test result of the chip such as Fig. 1
In 1.2 parts shown in, each region it is each have by oneself a failpoint (being characterized with x).The reparation provided according to chip designer
Method, the chip can be repaired, it will be embodied in the dose rate of wafer.But due to 2m/ 3 are not equal to 2 integral multiple, therefore
Traditional method of testing can not look for out suitable chip address in the m positions X addresses of chip, and chip is third in the X direction
Point, as shown in 1.3 parts, it gives traditional recovery scenario of chip testing, the program is abandoned to the X-direction of chip
Division so that the design concept of independent restoring area has not existed.Therefore test result such as Fig. 1 of chip 1.2 part institutes are worked as
When showing, the chip can not be repaired, and will not be calculated in the dose rate of wafer.This way does not have the true need of reaction designing personnel
Ask, result in the increase of production cost.
The content of the invention
In order to solve existing to use 2nIndividual number of addresses can not truly reflect the demand of chip designer for the way on border,
The write-in of topology is it cannot be guaranteed that the technical problem of the robustness of chip testing result, present invention offer are a kind of with finding dram chip
The method on location border.
The present invention technical solution be：
A kind of restorative procedure of dram chip, it is characterized in that：Comprise the following steps,
1】On the chip m positions X addresses to be repaired, expand two virtual address positions；
2】The X addresses that will be repaired are divided into odd number restoring area, it is corresponding with same rule by redundant storage unit
It is divided into odd number memory cell；Memory cell corresponds with restoring area；
3】Two virtual addresses of expansion are encoded, find out the reparation border of each restoring area；
4】The reparation border of corresponding restoring area is modified using each memory cell.
Above-mentioned steps 3】In should ensure that expansion two virtual addresses coded combination in the odd number restoring area
Uniqueness.
Above-mentioned steps 2】X addresses are divided into three restoring areas.
Advantage for present invention：
1st, the present invention is using the way for expanding virtual address position, by non-2n(n is equal to integer), individual number of addresses loaded what is expanded
In virtual address position, the mark of chip design address boundary is carried out with virtual address position；This method really reflects chip and set
The demand of meter personnel, it is addressed a series of problems related to address boundary positioning in chip testing.
2nd, two virtual address positions of the invention due to expansion will not produce any influence to original m positions chip X addresses,
Therefore, the normally addressing of chip is unaffected, and then ensure that the correct access of test chip address.
Brief description of the drawings
Fig. 1 is traditional chip restorative procedure schematic diagram；
Fig. 2 is chip restorative procedure schematic diagram provided by the present invention.
Embodiment
By taking the reparation of dram chip as an example, the application that address boundary is positioned at during DRAM is repaired is illustrated, is lifted for trisection
Example.
As shown in Fig. 2 chip designer's recovery scenario of offer is given in a, it is assumed that the DRAM has m, and (m is equal to whole
Number) position X addresses, i.e. the X address numbers of the chip are 2mIt is individual, and 2mIndividual address is evenly distributed in 3 independent restoring area (areas
Domain 0, region 1 and region 2), therefore the X number of addresses of each independent restoring area is 2m/ 3, a redundant storage unit is also with phase
With rule be divided into memory cell by third, and the memory cell of each decile can independently repair this to restoring area
(disabling unit is repaired using redundancy unit is stored in respective reparation border inner) fail address.Shown in c parts, pin
To the situation of chip trisection in the X direction, on the m positions X addresses basis of chip, expanded two virtual address Xm+2 and
Xm+1 and it is encoded, while ensure the coded combination of this two virtual addresses in the unique of these three independent restoring areas
Property.This two virtual addresses will be introduced in the test of chip, for determining the trisection border in chip X-direction
Position, when chip is repaired, can accurately find out the address boundary of chip, correctly repair the test bad of the b parts in Fig. 2
Point, the problems caused by avoiding traditional recovery scenario.Because new caused two virtual X addresses will not be to original m positions core
Piece X addresses produce any influence, and therefore, the normally addressing of chip is unaffected, and then ensure that the correct of test chip address
Access.
Claims (2)
- A kind of 1. restorative procedure of dram chip, it is characterised in that：Comprise the following steps,1】On the chip m positions X addresses to be repaired, expand two virtual address positions；2】The X addresses that will be repaired are divided into odd number restoring area, corresponding to be divided redundant storage unit with same rule Into odd number memory cell；Memory cell corresponds with restoring area；3】Two virtual addresses of expansion are encoded, find out the reparation border of each restoring area；4】The reparation border of corresponding restoring area is modified using each memory cell；Above-mentioned steps 3】In should ensure that expansion two virtual addresses coded combination in the unique of the odd number restoring area Property.
- 2. the restorative procedure of dram chip according to claim 1, it is characterised in that：The step 2】X addresses are divided Into three restoring areas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797472.4A CN104575619B (en) | 2014-12-18 | 2014-12-18 | A kind of restorative procedure of dram chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410797472.4A CN104575619B (en) | 2014-12-18 | 2014-12-18 | A kind of restorative procedure of dram chip |
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| CN104575619A CN104575619A (en) | 2015-04-29 |
| CN104575619B true CN104575619B (en) | 2018-01-23 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106169311B (en) * | 2016-07-06 | 2019-01-15 | 西安紫光国芯半导体有限公司 | The method of fail address is accurately captured in a kind of DRAM wafer test |
| CN111415700B (en) * | 2020-04-24 | 2022-05-06 | 西安紫光国芯半导体有限公司 | Repair method, repair device and computer storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307341A (en) * | 2000-01-28 | 2001-08-08 | 三星电子株式会社 | Integrated circuit semiconductor device and self-repairing circuit and method for built-in storage |
| CN102420016A (en) * | 2011-11-03 | 2012-04-18 | 西安交通大学 | Built-in repair analysis method applied to embedded memory integrated with error check code |
| CN103198870A (en) * | 2013-03-19 | 2013-07-10 | 西安华芯半导体有限公司 | Repairing method of non-uniformly distributed redundances in DRAM (Dynamic Random Access Memory) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5742555A (en) * | 1996-08-20 | 1998-04-21 | Micron Technology, Inc. | Method of anti-fuse repair |
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- 2014-12-18 CN CN201410797472.4A patent/CN104575619B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307341A (en) * | 2000-01-28 | 2001-08-08 | 三星电子株式会社 | Integrated circuit semiconductor device and self-repairing circuit and method for built-in storage |
| CN102420016A (en) * | 2011-11-03 | 2012-04-18 | 西安交通大学 | Built-in repair analysis method applied to embedded memory integrated with error check code |
| CN103198870A (en) * | 2013-03-19 | 2013-07-10 | 西安华芯半导体有限公司 | Repairing method of non-uniformly distributed redundances in DRAM (Dynamic Random Access Memory) |
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Applicant before: Xi'an Sinochip Semiconductors Co., Ltd. |
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Inventor after: Wang Fan Inventor after: Wang Zhengwen Inventor before: Wang Zhengwen |