CN104517846B - A kind of manufacturing method of semiconductor devices - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, forming active/drain regions in the semiconductor substrate on both sides of the gate structure; an ion implantation and a first annealing to form dislocations in the source/drain region; performing a second ion implantation so that the source/drain region is in an amorphous state; forming a stress capping layer covering the gate structure and the semiconductor substrate; performing the second annealing to transfer the tensile stress of the stress capping layer to the channel region of the semiconductor substrate; removing the stress capping layer and forming a self-aligned silicide on the source/drain region; forming an adjustable high stress contact hole etch stop layer. According to the present invention, the first ion implantation forms dislocations in the source/drain region and forms a contact hole etch stop layer with adjustable high stress to improve the stability of the tensile stress acting on the channel region of NMOS, thereby significantly Enhance carrier mobility in the channel region of NMOS.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to a semiconductor manufacturing process, in particular to a method for improving carrier mobility in a channel region of an NMOS.

Background technique

When the node of the semiconductor manufacturing process reaches 90nm and below, the stress technology (Stress Engineering) is widely used to improve the carrier mobility in the channel region of the semiconductor device.

For CMOS, after the source/drain region is implanted, a double stress layer is usually formed on the substrate to increase the carrier mobility in the channel region. Among them, the tensile stress layer is used to increase the carrier mobility in the NMOS channel region. electron mobility, the compressive stress layer is used to improve the hole mobility in the PMOS channel region. However, when the double stress layer is formed, the tensile stress layer and the compressive stress layer constituting the double stress layer overlap each other at the junction of the two. The overlapping portions will produce a boundary proximity effect, which will lead to a significant decrease in carrier mobility in the channel region. At the same time, the overlapping parts will also cause a certain degree of trouble to the implementation of the subsequent contact hole etching process. If a single tensile stress layer is formed, the electron mobility in the NMOS channel region is increased while the hole mobility in the PMOS channel region is reduced.

After performing annealing and removing the above stress layer, a salicide is formed on the source/drain region, and then a contact hole etching stop layer with different stress characteristics is formed on the substrate. Due to the existence of salicide, high temperature annealing cannot be performed to transfer the stress of the contact hole etching stop layer to the channel region, thereby affecting the effect of stress memory.

Therefore, it is necessary to propose a method to solve the problems existing in the stress memory process mentioned above.

Contents of the invention

Aiming at the deficiencies in the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, on which a gate structure is formed, and the semiconductor substrates on both sides of the gate structure forming an active source/drain region; sequentially performing first ion implantation and first annealing to form dislocations in the source/drain region; performing second ion implantation so that the source/drain region is in an amorphous state forming a stress capping layer covering the gate structure and the semiconductor substrate; performing a second annealing to transfer the tensile stress of the stress capping layer to the channel region of the semiconductor substrate.

Further, the implanted ions of the first ion implantation are tin ions, which are performed in two steps: in the first step, the incident direction of the ion implantation is perpendicular to the surface of the semiconductor substrate, and the implantation dose is 3.0×e ¹⁴ - 1.0×e ¹⁵ ions/square centimeter, the implantation energy is 40-100keV; in the second step, the angle of incidence of the ion implantation relative to the surface of the semiconductor substrate is 7-35 degrees, and the implantation dose is 5.0×e ¹⁴ -1.5×e ¹⁵ ions/square centimeter, the implantation energy is 60-200keV.

Further, the order of performing the first step and the second step is exchanged.

Further, the first annealing is peak annealing or laser annealing.

Further, the temperature of the peak annealing is 900-1100°C, and the duration is 10-60s; the temperature of the laser annealing is 1200-1350°C, and the duration is 20-80ms.

Further, the implanted ions of the second ion implantation are germanium ions, the ion implantation is completed in one step, the angle of incidence of the ion implantation relative to the surface of the semiconductor substrate is 0-15 degrees, and the implantation dose is 5.0×e ¹⁴ - 1.0×e ¹⁵ ions/square centimeter, implantation energy is 20-40keV.

Further, the stress covering layer has a thickness of 10-100 nm.

Further, the second annealing is peak annealing or transient annealing.

Further, the temperature of the peak annealing is 950-1100°C, and the duration is 20-60s; the temperature of the transient annealing is 1000-1350°C, and the duration is 10-300ms.

Further, after the second annealing, the following steps are further included: removing the stress covering layer, and forming a self-aligned silicide on the source/drain region; forming a structure covering the gate, the self-aligned Alignment of silicide and contact hole etch stop layer of the semiconductor substrate with adjustable high stress.

Further, the material of the etching stop layer of the contact hole is TaC _x N _y or TiC _x N _y , wherein the value range of x is 0.01-0.2, and the value range of y is 0.05-0.3.

Further, the semiconductor device is NMOS.

Further, the gate structure includes a gate dielectric layer and a gate material layer stacked from bottom to top.

According to the present invention, the formation of the dislocation in the source/drain region of the semiconductor substrate by the first ion implantation and the formation of the contact hole etch stop layer with adjustable high stress enhance the effect on the Stability of the tensile stress of the channel region of the NMOS, thereby significantly enhancing the carrier mobility of the channel region of the NMOS.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1A-FIG. 1G are schematic cross-sectional views of devices respectively obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention;

Fig. 2 is a flow chart of steps executed sequentially in a method according to an exemplary embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be presented in the following description, so as to explain the method for improving the carrier mobility of the NMOS channel region proposed by the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be understood that when the terms "comprising" and/or "comprising" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or Multiple other features, integers, steps, operations, elements, components and/or combinations thereof.

[Exemplary embodiment]

In the following, the detailed steps of improving the carrier mobility in the channel region of the NMOS according to the method according to the exemplary embodiment of the present invention will be described with reference to FIG. 1A-FIG. 1G and FIG. 2 .

Referring to FIG. 1A-FIG. 1G , there are shown schematic cross-sectional views of devices respectively obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention.

First, as shown in FIG. 1A , a semiconductor substrate 100 is provided. The constituent materials of the semiconductor substrate 100 can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI), and stacked on insulator. Silicon (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. As an example, in this embodiment, single crystal silicon is selected as the constituent material of the semiconductor substrate 100 . An isolation structure 101 is formed in the semiconductor substrate 100. As an example, the isolation structure 101 is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure. In this embodiment, the isolation structure 101 divides the semiconductor substrate 100 into an NMOS region and a PMOS region, and only the NMOS region is shown in the figure. Various well structures are also formed in the semiconductor substrate 100 , which are omitted in the illustration for simplicity.

A gate structure 102 is formed on the semiconductor substrate 100 . As an example, the gate structure includes a gate dielectric layer 102 a and a gate material layer 102 b sequentially stacked from bottom to top. The gate dielectric layer 102 a includes an oxide layer, such as a silicon dioxide (SiO ₂ ) layer. The gate material layer 102b includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the constituent material of the metal layer can be tungsten (W ), nickel (Ni) or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer includes an iridium oxide (IrO ₂ ) layer; the metal silicide layer includes a titanium silicide ( TiSi) layer. The formation method of the gate dielectric layer 102a and the gate material layer 102b can adopt any prior art familiar to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor phase Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).

In addition, as an example, offset spacers 103 close to the gate structure 102 are formed on both sides of the gate structure 102 . The offset spacer 103 is made of oxide, nitride or a combination thereof. In this embodiment, the material of the offset spacer 103 is oxide. The process of forming the offset sidewall 103 is familiar to those skilled in the art, and will not be repeated here.

Side walls 104 are formed on both sides of the offset side wall 103 . The process steps of forming the sidewall 104 include: forming a sidewall material layer completely covering the gate structure 102 and the offset sidewall 103 on the semiconductor substrate 100, and its constituent material is preferably silicon nitride; using sidewall etching (blanket etch) The process etches the layer of sidewall material to form sidewalls 104 .

Next, performing source/drain region implantation 105 and annealing to form source/drain regions in the semiconductor substrate 100 , which are omitted in the illustration for simplicity. The process of forming the source/drain region 105 is familiar to those skilled in the art, and will not be repeated here. In order to reduce the thermal budget, the annealing can be moved to the subsequent implementation of stress memory. Before or simultaneously with source/drain region implantation 105, a pre-amorphization implantation may optionally be performed to reduce the short channel effect. The implanted ions for pre-amorphization implantation include group III and group V ions such as germanium and carbon.

Next, as shown in FIG. 1B , the sidewall 105 is removed, and a first ion implantation 106 is performed. In this embodiment, the implanted ions of the first ion implantation 106 are tin (Sn) ions, which are performed in two steps: in the first step, the incident direction of the ion implantation is perpendicular to the surface of the semiconductor substrate 100, and the implantation dose is 3.0×e ¹⁴ -1.0×e ¹⁵ ions/square centimeter, the implantation energy is 40-100keV; in the second step, the incident direction of the ion implantation has an intersection angle with respect to the surface of the semiconductor substrate 100, and the intersection angle is preferably 7-35 The implantation dose is 5.0×e ¹⁴ -1.5×e ¹⁵ ions/cm2, and the implantation energy is 60-200keV. It should be noted that the order of performing the first step and the second step can be interchanged.

Next, as shown in FIG. 1C , a first anneal is performed to form dislocations 107 in the source/drain regions of the semiconductor substrate 100 . Taking the implanted ions of the first ion implantation 106 as tin ions as an example, the dislocation 107 is composed of lattice dislocation defects generated at the interface between the tin ion implantation region and the silicon in the semiconductor substrate 100, which can significantly enhance Stress acting on the channel region of the semiconductor substrate 100 . After the first ion implantation 106 is performed, the silicon in the ion implantation region is in an amorphous state, and the lattice volume increases (approximately 6-8%); after the first annealing is performed, the silicon in the ion implantation region is recrystallized , the lattice volume returns to the state before the first ion implantation 106 is performed, and the above-mentioned change in the silicon lattice volume leads to the generation of the lattice dislocation defect. In this embodiment, the first annealing is peak annealing or laser annealing. The temperature of the peak annealing is 900-1100°C, and the duration is 10-60s; the temperature of the laser annealing is 1200-1350°C, and the duration is 20-80ms.

Next, as shown in FIG. 1D , a second ion implantation 108 is performed to make the source/drain regions amorphous. In this embodiment, the implanted ions of the second ion implantation 108 are germanium (Ge) ions, the ion implantation is completed in one step, the angle of incidence of the ion implantation relative to the surface of the semiconductor substrate 100 is 0-15 degrees, and the implantation dose is 5.0×e ¹⁴ -1.0×e ¹⁵ ions/square centimeter, the implantation energy is 20-40keV. After the second ion implantation 108 is performed, the silicon in the ion implantation region becomes amorphous again, and the tensile stress generated by the increase in lattice volume is locked by the dislocations 107 , and this process is equivalent to a stress memory process.

Next, as shown in FIG. 1E , a stress capping layer 109 covering the gate structure 102 and the semiconductor substrate 100 is formed. In this embodiment, the stress covering layer 109 is formed using a conformal deposition process, so that the formed stress covering layer 109 has a good step coverage property. The stress of the stress covering layer 109 is related to the process conditions of the deposition process used to form the stress covering layer 109, which is not specifically limited here, and its constituent material is preferably silicon nitride, and its thickness is 10-100 nm. It should be noted that, before forming the stress covering layer 109, a thin oxide layer may be formed first to prevent damage to the semiconductor substrate 100 when the stress covering layer 109 is subsequently removed. the thin oxide layer.

Then, a second anneal is performed to transfer the tensile stress of the stress capping layer 109 to the channel region in the semiconductor substrate 100 . The transfer of the above stress is realized by the dislocation 107. After the second annealing, the silicon in the ion implantation region recrystallizes, and the tensile stress generated by the reduction of the lattice volume (6% reduction of the lattice volume induces 4GPa The tensile stress) is locked by dislocation 107. Due to the presence of the stress capping layer 109 , the lattice volume of silicon in the ion implantation region will not be completely restored to the state before the second ion implantation 108 is performed. In this embodiment, the second annealing is peak annealing or transient annealing. The temperature of the peak annealing is 950-1100°C, and the duration is 20-60s; the temperature of the transient annealing is 1000-1350°C, and the duration is 10-300ms.

Next, as shown in FIG. 1F , the stress capping layer 109 is removed, and a salicide 110 is formed on the source/drain regions in the semiconductor substrate 100 . In this embodiment, the stress capping layer 109 is removed by a wet etching process. The process of forming the salicide 110 is well known to those skilled in the art and will not be repeated here.

Next, as shown in FIG. 1G , an etch stop layer 111 covering the gate structure 102 , the salicide 110 and the contact hole with adjustable high stress in the semiconductor substrate 100 is formed. In this embodiment, the contact hole etch stop layer 111 is formed using a conformal deposition process, so that the formed contact hole etch stop layer 111 has good step coverage characteristics. The material of the contact hole etching stop layer 111 is preferably TaC _x N _y or TiC _x N _y to enhance the carrier mobility and saturation current in the channel region of NMOS, wherein the value of x is in the range of 0.01-0.2, and the value of y is in the range of 0.05-0.3.

So far, the process steps implemented by the method according to the exemplary embodiment of the present invention are completed. Next, the fabrication of the entire semiconductor device can be completed through subsequent processes, including: forming an interlayer dielectric layer on the contact hole etching stop layer 111, and A contact hole communicating with the salicide 110 is formed in the interlayer dielectric layer, and the contact hole is filled with a metal material constituting a contact plug. According to the present invention, the dislocation 107 is formed in the source/drain region of the semiconductor substrate 100 by the first ion implantation 106 and the contact hole etch stop layer 111 with adjustable high stress is formed to enhance the effect on the channel region of the NMOS. The stability of the tensile stress, thereby significantly enhancing the carrier mobility of the NMOS channel region.

Referring to FIG. 2 , there is shown a flow chart of improving carrier mobility in a channel region of an NMOS according to a method according to an exemplary embodiment of the present invention, which is used to briefly illustrate the flow of the entire manufacturing process.

In step 201, a semiconductor substrate is provided, a gate structure is formed on the semiconductor substrate, and source/drain regions are formed in the semiconductor substrate on both sides of the gate structure;

In step 202, the first ion implantation and the first annealing are sequentially performed to form dislocations in the source/drain regions;

In step 203, a second ion implantation is performed, so that the source/drain region is in an amorphous state;

In step 204, forming a stress covering layer covering the gate structure and the semiconductor substrate;

In step 205, a second anneal is performed to transfer the tensile stress of the stress capping layer to the channel region of the semiconductor substrate;

In step 206, the stress material layer is removed, and salicide is formed on the source/drain region;

In step 207 , an etch stop layer covering the gate structure, the salicide and the semiconductor substrate with adjustable high stress is formed for the contact hole.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, a gate structure is formed on the semiconductor substrate, and source/drain regions are formed in the semiconductor substrate on both sides of the gate structure; performing the first ion implantation and the first annealing in order to form dislocations in the source/drain regions, wherein the implantation of the first ion implantation is performed in two steps: in the first step, the incident direction of the ion implantation perpendicular to the surface of the semiconductor substrate, in the second step, the angle of incidence of the ion implantation relative to the surface of the semiconductor substrate is 7-35 degrees; performing a second ion implantation so that the source/drain region is amorphous; forming a stress capping layer covering the gate structure and the semiconductor substrate; performing a second anneal to transfer the tensile stress of the stress capping layer to the channel region of the semiconductor substrate; removing the stress covering layer, and forming salicide on the source/drain region; forming a contact hole etch stop layer with adjustable high stress covering the gate structure, the salicide and the semiconductor substrate, the material of the contact hole etch stop layer is TaC _x N _y or TiC _x N _y , wherein, the value range of x is 0.01-0.2, and the value range of y is 0.05-0.3. 2. The method according to claim 1, wherein the implanted ions of the first ion implantation are tin ions, and the implantation dose of the first step is 3.0×e ¹⁴ -1.0×e ¹⁵ ions/square centimeter , the implantation energy is 40-100keV; the implantation dose in the second step is 5.0×e ¹⁴ -1.5×e ¹⁵ ions/square centimeter, and the implantation energy is 60-200keV. 3. The method according to claim 2, characterized in that the order of performing the first step and the second step is interchanged. 4. The method according to claim 1, wherein the first annealing is peak annealing or laser annealing. 5. The method according to claim 4, wherein the temperature of the peak annealing is 900-1100° C., and the duration is 10-60 s; the temperature of the laser annealing is 1200-1350° C., and the duration is 20 s. -80ms. 6. The method according to claim 1, wherein the implanted ions of the second ion implantation are germanium ions, and the second ion implantation is completed in one step, and its incident direction is relative to the surface of the semiconductor substrate. The intersection angle is 0-15 degrees, the implantation dose is 5.0×e ¹⁴ -1.0×e ¹⁵ ions/square centimeter, and the implantation energy is 20-40keV. 7. The method according to claim 1, characterized in that the thickness of the stress covering layer is 10-100 nm. 8. The method according to claim 1, wherein the second annealing is peak annealing or transient annealing. 9. The method according to claim 8, characterized in that, the temperature of the peak annealing is 950-1100° C., and the duration is 20-60 s; the temperature of the transient annealing is 1000-1350° C., and the duration is 10 s. -300ms. 10. The method according to claim 1, wherein the semiconductor device is an NMOS. 11. The method according to claim 1, wherein the gate structure comprises a gate dielectric layer and a gate material layer stacked from bottom to top.