CN104517573A - Bias voltage generating circuit and liquid crystal drive circuit - Google Patents
Bias voltage generating circuit and liquid crystal drive circuit Download PDFInfo
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- CN104517573A CN104517573A CN201410421491.7A CN201410421491A CN104517573A CN 104517573 A CN104517573 A CN 104517573A CN 201410421491 A CN201410421491 A CN 201410421491A CN 104517573 A CN104517573 A CN 104517573A
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Abstract
The invention discloses a bias voltage generating circuit comprising a first bias voltage generating circuit and a second bias voltage generating circuit. The first bias voltage generating circuit comprises a plurality of divider resistors serially connected between a power source voltage and a ground. Drive current of the second bias voltage generating circuit is higher than that of the first bias voltage generating circuit. The second bias voltage generating circuit comprises a plurality of source follower circuits; the output end of each source follower circuit is connected with a bias voltage output end and provides bias voltage equal to the first bias voltage generating circuit; each source follower circuit comprises more than one MOS (metal oxide semiconductor) transistor source follower and more than one first MOS (metal oxide semiconductor) transistor switch; on and off of the first MOS transistor switches is controlled through clock signals to control make or break of the source follower circuits, thereby switching the drive current of the whole bias voltage generating circuit. The invention further provides a liquid crystal drive circuit. The bias voltage generating circuit and the liquid crystal drive circuit have the advantages that the drive current of the output voltage can be changed, signal switching speed can be increased and drive circuit power consumption can be decreased.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit), particularly relate to a kind of bias-voltage generating circuit; The invention still further relates to a kind of liquid crystal display drive circuit.
Background technology
The kind of liquid crystal display is many, the segment encode type liquid crystal display that such as electronic watch and metering instrument field use is exactly one wherein. and this liquid crystal display self has low-voltage and low-power dissipation, slab construction, the features such as the life-span is long are widely used. and the low-power consumption MCU of current metering field applies, and requires the segment encode type liquid crystal display drive circuit of more low-power consumption.
The tow sides of panel of LCD include public electrode and segmented electrode, the driving circuit of liquid crystal display generally provides public (COM) signal and segmentation (SEG) signal to the electrode of liquid crystal panel, had to each section of liquid crystal panel by common signal, block signal is then given to the specific section of liquid crystal panel, is lighted by the difference of common signal and block signal or is extinguished the section corresponding to liquid crystal panel.
Common signal comprises multiple, and the waveform of multiple common signal is identical and postpone a phase bit each other, and when the number of common signal is m, the type of drive of driving circuit is that 1/m dutycycle drives (1/m Duty mode).The voltage of common signal and block signal can change, the number of voltages of change is provided by the bias-voltage generating circuit of liquid crystal display drive circuit, bias-voltage generating circuit generally provides multiple equal portions magnitudes of voltage between the supply voltage and ground, as when the timesharing of liquid crystal panel drives as carrying out the driving of 1/s bias voltage (1/s Bias mode), supply voltage is divided into s equal portions, difference between every two voltages is the 1/s of supply voltage, and the quantity of the magnitude of voltage that each common signal and block signal can be got is s+1.
Existing segment encode liquid crystal display drive circuit adopts existing bias-voltage generating circuit as shown in Figure 1; Bias-voltage generating circuit 101 uses a string divider resistance string to produce bias voltage, illustrate 4 divider resistances in Fig. 1 and be respectively resistance 100,101,102 and 103,3 medium voltages and VLC100, VLC101, VLC102 can be formed between 4 divider resistances, add that supply voltage VLCD and earth potential can export 5 dividing potential drops.The switching tube that a PMOS M100 that divider resistance string has also been connected forms, control signal LIPS_B is connected to the grid of PMOS M100 and realizes the conducting of divider resistance string and the control of disconnection.The dividing potential drop of bias-voltage generating circuit 101 is input in bias control circuit 102, bias control circuit 102 exports common signal and block signal, common signal is connected to the public electrode of liquid crystal panel 103, and block signal is connected to the segmented electrode of liquid crystal panel 103.Change between the dividing potential drop that common signal and block signal can export at bias-voltage generating circuit 101, thus realize lighting or extinguishing liquid crystal display.Namely there is larger electric capacity between public electrode and segmented electrode between liquid crystal display pros and cons, and there is larger resistance and a certain amount of leakage current can be produced, the switching rate of each signal and each common signal or block signal can be improved when the divider resistance value of the bias-voltage generating circuit 101 shown in Fig. 1 is little, drive current is large, but bring like this problem is when each signal does not change, electric current meeting one direct current of bias-voltage generating circuit 101, obvious drive current increase can cause the power consumption of liquid crystal display drive circuit to increase; And although the drive current reducing bias-voltage generating circuit 101 can reduce the power consumption of liquid crystal display drive circuit, this can increase the switching time that each signal intensity is; So existing bias-voltage generating circuit 101 cannot solve improving the contradiction between the switching rate of each signal and the power consumption reducing driving circuit.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of bias-voltage generating circuit, the change of the drive current of output voltage can be realized, the switching rate of each common signal or block signal can be improved when being applied to liquid crystal display drive circuit, the power consumption of driving circuit can be reduced again.For this reason, the present invention also provides a kind of liquid crystal display drive circuit.
For solving the problems of the technologies described above, bias-voltage generating circuit provided by the invention comprises:
First bias-voltage generating circuit, comprise the multiple divider resistances be series between supply voltage and ground, the cascaded structure of described divider resistance carries out dividing potential drop to described supply voltage and forms multiple bias voltage, and the output terminal of each described bias voltage of described first bias-voltage generating circuit is respectively as a bias voltage output of whole bias-voltage generating circuit.
Drive current is greater than the second bias-voltage generating circuit of described first bias-voltage generating circuit, comprise the source follower circuit identical with the number of described bias voltage output, the output terminal of each described source follower circuit connects a described bias voltage output.
Each described source follower circuit comprises more than one MOS transistor source follower and more than one first mos transistor switch; The break-make being controlled described first mos transistor switch by clock signal controls being turned on or off of described source follower circuit.
The source voltage of each described MOS transistor source follower is as the output end voltage of the described source follower circuit of correspondence, and the voltage that output terminal during each described source follower circuit conducting exports is identical with the voltage that described first bias-voltage generating circuit exports at the described bias voltage output of correspondence; Add grid voltage at the grid of each described MOS transistor source follower, the gate source voltage of each described MOS transistor source follower is a threshold voltage and is determined the On current of corresponding described source follower circuit by this gate source voltage.
The drive current of bias voltage output corresponding during described source follower circuit conducting is formed by the drive current superposition of described first bias-voltage generating circuit and described second bias-voltage generating circuit; The drive current of bias voltage output corresponding when described source follower circuit disconnects is determined by the drive current of described first bias-voltage generating circuit.
Further improvement is, each described source follower circuit comprises two described MOS transistor source followers and two described first mos transistor switches, two described first mos transistor switches are respectively the first PMOS and the 4th NMOS tube, and two described MOS transistor source followers are respectively the 2nd NOMS pipe, the 3rd PMOS; Described first PMOS, described 2nd NOMS pipe, described 3rd PMOS and described 4th NMOS tube series connection are between the supply voltage and ground, the source electrode of described first PMOS connects described supply voltage, the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, the source electrode of described second NMOS tube be connected with the source electrode of described 3rd PMOS and this link position as the output terminal of the described source follower circuit of correspondence; The drain electrode of described 3rd PMOS is connected with the drain electrode of described 4th NMOS tube, the source ground of described 4th NMOS tube.
The second clock signal that first clock signal of the grid connection of described first PMOS is connected with the grid of described 4th NMOS tube is anti-phase each other, the grid of described second NMOS tube connects primary grid voltage, the grid of described 3rd PMOS connects second grid voltage, arranges the output end voltage of corresponding described source follower circuit by arranging described primary grid voltage and described second grid voltage.
Further improvement is, the output voltage of the bias voltage output of described bias-voltage generating circuit is input to bias control circuit, the output terminal of described bias control circuit exports multiple common signal and multiple block signal, each described common signal and each described block signal are input to liquid crystal panel and drive described liquid crystal panel work, and each described common signal or each described block signal can change respectively between the bias voltage of each bias voltage output of described bias-voltage generating circuit; When each described common signal or each described block signal change, with the described source follower circuit conducting corresponding to the described bias voltage output corresponding to the bias voltage after each described common signal or each described block signal change, described source follower circuit corresponding after postponing certain hour disconnects.
Further improvement is, the size of the drive current of described second bias-voltage generating circuit meets makes transformation period when each described common signal or each described block signal change narrow down to required value; The drive current of described first bias-voltage generating circuit maintains required value scope for making the size of the described common signal or each described block signal that are input to described liquid crystal panel between twice change.
Further improvement is, regulate the drive current size of described first bias-voltage generating circuit by adjusting each described divider resistance, the size of the drive current of described first bias-voltage generating circuit is wanted to compensate the leakage current produced between the public pole of described liquid crystal panel and segmentation pole.
Further improvement is, described first bias-voltage generating circuit also comprises one second mos transistor switch, the source-drain electrode of described second mos transistor switch is connected on the path of each described divider resistance, and the grid of described second mos transistor switch connects a control signal to control the turn-on and turn-off of described first bias-voltage generating circuit.
Further improvement is, described second bias-voltage generating circuit also comprises one source pole follower control circuit, for providing described clock signal to control the break-make of described first mos transistor switch and to provide the grid voltage of described MOS transistor source follower to control the output end voltage of described source follower circuit.
For solving the problems of the technologies described above, the bias-voltage generating circuit of liquid crystal display drive circuit provided by the invention comprises:
First bias-voltage generating circuit, comprise the multiple divider resistances be series between supply voltage and ground, the cascaded structure of described divider resistance carries out dividing potential drop to described supply voltage and forms multiple bias voltage, and the output terminal of each described bias voltage of described first bias-voltage generating circuit is respectively as a bias voltage output of whole bias-voltage generating circuit.
Drive current is greater than the second bias-voltage generating circuit of described first bias-voltage generating circuit, comprise the source follower circuit identical with the number of described bias voltage output, the output terminal of each described source follower circuit connects a described bias voltage output.
Each described source follower circuit comprises more than one MOS transistor source follower and more than one first mos transistor switch; The break-make being controlled described first mos transistor switch by clock signal controls being turned on or off of described source follower circuit.
The source voltage of each described MOS transistor source follower is as the output end voltage of the described source follower circuit of correspondence, and the voltage that output terminal during each described source follower circuit conducting exports is identical with the voltage that described first bias-voltage generating circuit exports at the described bias voltage output of correspondence; Add grid voltage at the grid of each described MOS transistor source follower, the gate source voltage of each described MOS transistor source follower is a threshold voltage and is determined the On current of corresponding described source follower circuit by this gate source voltage.
The drive current of bias voltage output corresponding during described source follower circuit conducting is formed by the drive current superposition of described first bias-voltage generating circuit and described second bias-voltage generating circuit; The drive current of bias voltage output corresponding when described source follower circuit disconnects is determined by the drive current of described first bias-voltage generating circuit.
Further improvement is, the output voltage of the bias voltage output of described bias-voltage generating circuit is input to bias control circuit, the output terminal of described bias control circuit exports multiple common signal and multiple block signal, each described common signal and each described block signal are input to liquid crystal panel and drive described liquid crystal panel work, and each described common signal or each described block signal can change respectively between the bias voltage of each bias voltage output of described bias-voltage generating circuit; When each described common signal or each described block signal change, with the described source follower circuit conducting corresponding to the described bias voltage output corresponding to the bias voltage after each described common signal or each described block signal change, described source follower circuit corresponding after postponing certain hour disconnects.
Bias-voltage generating circuit of the present invention comprises two-way, first bias-voltage generating circuit forms dividing potential drop by resistance string, second bias-voltage generating circuit is formed by multiple source follower circuit and exports the dividing potential drop identical with resistance string dividing potential drop, source follower circuit can be form large drive current, source follower circuit is in series with mos transistor switch, the turn-on and turn-off of source follower circuit can be controlled by mos transistor switch, the drive current of corresponding bias voltage output can be made to increase when the conducting of source follower circuit, the drive current of corresponding bias voltage output can be made the level of the first bias-voltage generating circuit is reduced to when the disconnection of source follower circuit, so the present invention can realize the change of the drive current of output voltage.
When circuit application of the present invention is in liquid crystal display drive circuit, enable the second bias-voltage generating circuit conducting realize switching under large-drive-current when each signal of liquid crystal display drive circuit and each common signal or block signal change, thus the switching rate of each signal can be improved.And when each signal does not change, the second bias-voltage generating circuit disconnects, the magnitude of voltage of each signal is only kept by the first bias-voltage generating circuit, and the drive current of the first less bias-voltage generating circuit can reduce the power consumption of driving circuit.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing bias-voltage generating circuit;
Fig. 2 is the structural representation of embodiment of the present invention bias-voltage generating circuit;
Fig. 3 is the structural representation of the source follower circuit of present pre-ferred embodiments bias-voltage generating circuit;
Fig. 4 is the output waveform schematic diagram under timing control signal of the common signal of the liquid crystal display drive circuit adopting embodiment of the present invention circuit.
Embodiment
As shown in Figure 2, be the structural representation of embodiment of the present invention bias-voltage generating circuit; Embodiment of the present invention bias-voltage generating circuit comprises:
First bias-voltage generating circuit 1, comprises the multiple divider resistances be series between supply voltage VLCD and ground, shows four divider resistances and be labeled as divider resistance R0, R1, R2 and R3 respectively in Fig. 2; The cascaded structure of described divider resistance carries out dividing potential drop to described supply voltage VLCD and forms multiple bias voltage, show four bias voltages in Fig. 2 and be labeled as bias voltage VLC0, VLC1, VLC2 and VLC3 respectively, wherein bias voltage VLC0 gets the size of supply voltage VLCD; Bias voltage VLC1, VLC2 and VLC3 are respectively the voltage at divider resistance R0, R1, R2 and R3 link position place.The output terminal of each described bias voltage of described first bias-voltage generating circuit 1 is respectively as a bias voltage output of whole bias-voltage generating circuit.
Drive current is greater than the second bias-voltage generating circuit 2 of described first bias-voltage generating circuit 1, comprise the source follower circuit 3 identical with the number of described bias voltage output, the output terminal of each described source follower circuit 3 connects a described bias voltage output.
Each described source follower circuit 3 comprises more than one MOS transistor source follower and more than one first mos transistor switch; The break-make being controlled described first mos transistor switch by clock signal controls being turned on or off of described source follower circuit 3.
The voltage that output terminal during each described source follower circuit 3 conducting exports is identical with the voltage that described first bias-voltage generating circuit 1 exports at the described bias voltage output of correspondence, the output end voltage of described source follower circuit 3 differs a gate source voltage with the grid voltage of the grid being added in described MOS transistor source follower, and this gate source voltage is determined by the On current of described source follower circuit 3.
The drive current of bias voltage output corresponding during described source follower circuit 3 conducting is formed by the drive current superposition of described first bias-voltage generating circuit 1 and described second bias-voltage generating circuit 2; The drive current of bias voltage output corresponding when described source follower circuit 3 disconnects is determined by the drive current of described first bias-voltage generating circuit 1.
As shown in Figure 3, be the structural representation of source follower circuit of present pre-ferred embodiments bias-voltage generating circuit; Each described source follower circuit 3 comprises two described MOS transistor source followers and two described first mos transistor switches, two described first mos transistor switches are respectively the first PMOS M1 and the 4th NMOS tube M4, and two described MOS transistor source followers are respectively the 2nd NOMS pipe M2, the 3rd PMOS M3; Described first PMOS M1, described 2nd NOMS pipe M2, described 3rd PMOS M3 and described 4th NMOS tube M4 are connected between supply voltage VLCD and ground, the source electrode of described first PMOS M1 connects described supply voltage VLCD, the drain electrode of described first PMOS M1 connects the drain electrode of described second NMOS tube M2, the source electrode of described second NMOS tube M2 be connected with the source electrode of described 3rd PMOS M3 and this link position as the output terminal of the described source follower circuit 3 of correspondence; The drain electrode of described 3rd PMOS M3 is connected with the drain electrode of described 4th NMOS tube M4, the source ground of described 4th NMOS tube M4.
Second clock signal/CLK that first clock signal clk of the grid connection of described first PMOS M1 is connected with the grid of described 4th NMOS tube M4 is anti-phase each other, the grid of described second NMOS tube M2 connects primary grid voltage VB1, the grid of described 3rd PMOS M3 connects second grid voltage VB2, arranges the output end voltage of corresponding described source follower circuit 3 by arranging described primary grid voltage VB1 and described second grid voltage VB2.
Described second bias-voltage generating circuit 2 also comprises one source pole follower control circuit 4, for providing described clock signal to control the break-make of described first mos transistor switch and to provide the grid voltage of described MOS transistor source follower to control the output end voltage of described source follower circuit 3.When described source follower circuit adopts better embodiment as shown in Figure 3, described source follower control circuit 4 is for providing described first clock signal clk, described second clock signal/CLK, described primary grid voltage VB1 and described second grid voltage VB2.
In the embodiment of the present invention, described bias-voltage generating circuit for realizing the driving to liquid crystal panel 6, and as the part of liquid crystal display drive circuit, realize the driving to liquid crystal panel 6, also comprise following circuit structure:
The output voltage of the bias voltage output of described bias-voltage generating circuit is input to bias control circuit 5, the output terminal of described bias control circuit 5 exports multiple common signal and multiple block signal, and each described common signal and each described block signal are input to liquid crystal panel 6 and drive described liquid crystal panel 6 to work; The segmented electrode that wherein said common signal is input to the public electrode of described liquid crystal panel 6, described block signal is input to described liquid crystal panel, the segmented electrode of described liquid crystal panel 6 and public electrode are positioned at the tow sides of liquid crystal panel 6, by lighting at described segmented electrode with the described public electrode institute different liquid crystal of respective segments that makes of making alive or extinguish.
Described segmented electrode and described public electrode institute making alive change with the described common signal of correspondence or the change of described block signal, and each described common signal or each described block signal can change respectively between the bias voltage of each bias voltage output of described bias-voltage generating circuit; When each described common signal or each described block signal change, with described source follower circuit 3 conducting corresponding to the described bias voltage output corresponding to the bias voltage after each described common signal or each described block signal change, described source follower circuit 3 corresponding after postponing certain hour disconnects.
Larger electric capacity is had between the segmented electrode of described liquid crystal panel 6 and public electrode, if the drive current of described bias-voltage generating circuit is too little when the current potential of segmented electrode and public electrode needs to change, then when the change of the current potential of segmented electrode and public electrode needs the longer time, and by adding described second bias-voltage generating circuit 2 in the embodiment of the present invention, and narrow down to required value by the transformation period that the size of the drive current making described second bias-voltage generating circuit 2 meets when making each described common signal or each described block signal change; Namely also the present invention, by after adding described second bias-voltage generating circuit 2, can increase transformation rate when the change of the current potential of segmented electrode and public electrode.
In addition, be not insulate completely between the segmented electrode of described liquid crystal panel 6 and public electrode, but there is a larger resistance, so have certain electric leakage; Each described common signal or each described block signal are also after the change in voltage of each described segmented electrode and described public electrode completes, if do not provide corresponding drive current to compensate electric leakage between two electrodes to each described segmented electrode and described public electrode, then corresponding voltage difference between described segmented electrode and described public electrode can reduce, thus affects the display of liquid crystal.In the embodiment of the present invention, described second bias-voltage generating circuit 2 had compared with large-drive-current can be turned off in the voltage maintenance stage of each described segmented electrode and described public electrode, and only adopt described first bias-voltage generating circuit 1 to provide drive current, in the embodiment of the present invention, the drive current of described first bias-voltage generating circuit 1 maintains required value scope for making the size of the described common signal or each described block signal that are input to described liquid crystal panel 6 between twice change, the drive current of described first bias-voltage generating circuit 1 also namely in the embodiment of the present invention is mainly used in compensating the electric leakage between each described segmented electrode and described public electrode, the current potential of corresponding each described segmented electrode and described public electrode is made to maintain required value.Be the drive current size regulating described first bias-voltage generating circuit 1 by adjusting each described divider resistance in the embodiment of the present invention, the size of the drive current of described first bias-voltage generating circuit 1 is wanted to compensate the leakage current produced between the public pole of described liquid crystal panel 6 and segmentation pole.
Described first bias-voltage generating circuit 1 also comprises one second mos transistor switch, the source-drain electrode of described second mos transistor switch is connected on the path of each described divider resistance, and the grid of described second mos transistor switch connects a control signal to control the turn-on and turn-off of described first bias-voltage generating circuit 1.Described in Fig. 2, the second mos transistor switch adopts PMOS M0, described PMOS M0 is serially connected between supply voltage VLCD and divider resistance R0, and namely the source electrode of described PMOS M0 meets described supply voltage VLCD, drain electrode connects described divider resistance R0, grid meets control signal LIPS_B; Realized the conducting of divider resistance string and the control of disconnection by control signal LIPS_B.Certainly in other embodiments, described PMOS M0 also can be serially connected on other position of divider resistance string; Or described PMOS M0 also can adopt NMOS tube to replace, just no longer enumeration here.
When the common electrical number of poles of described liquid crystal panel is 4, described common signal is 4, the driving of described liquid crystal panel is that 1/4 dutycycle drives; The number of the described bias voltage output of described bias-voltage generating circuit is 4, and the driving of described liquid crystal panel is that 1/3 bias voltage drives; Now with the mode of operation of liquid crystal drive for 1/3BIAS i.e. 1/3 bias voltage drives, the pattern that 1/4DUTY i.e. 1/4 dutycycle drives is described as follows the change of embodiment of the present invention circuit to exported described common signal or described block signal for example:
As shown in Figure 4, be the output waveform schematic diagram under timing control signal of common signal of the liquid crystal display drive circuit adopting embodiment of the present invention circuit;
When described control signal LIPS_B is low level, described first bias-voltage generating circuit 1 conducting also starts to provide 4 bias voltages, and four bias voltages got in Fig. 4 are respectively VLC0, VLC1, VLC3 and 0, described first clock signal clk is low level, described second clock signal/CLK is the second bias-voltage generating circuit 2 conducting described in during high level, and described second bias-voltage generating circuit 2 provides stronger drive current, a common signal COM0 is listed in Fig. 4, but the curve of other common signal is different with the identical phase place of common signal COM0, the change of block signal is also similar with common signal COM0, so be only described for the curve of common signal COM0 in Fig. 4, can find out, described control signal LIPS_B is after low level, described common signal COM0 when changing as the first clock signal clk as described in when rising or decline can form the low level pulse of one fixed width, and described second clock signal/CLK can form the high level pulse of one fixed width, as the t0 in Fig. 4, t1, corresponding to t2 and t3 shown in position, the rate of change of described common signal COM0 can be made like this to accelerate, and after the change of described common signal COM0 terminates, described first clock signal clk switches back high level, described second clock signal/CLK switches back low level, and described second bias-voltage generating circuit 2 is closed.Described common signal COM0 powers by means of only described first bias-voltage generating circuit 1, greatly can reduce the power consumption of circuit.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (9)
1. a bias-voltage generating circuit, is characterized in that, comprising:
First bias-voltage generating circuit, comprise the multiple divider resistances be series between supply voltage and ground, the cascaded structure of described divider resistance carries out dividing potential drop to described supply voltage and forms multiple bias voltage, and the output terminal of each described bias voltage of described first bias-voltage generating circuit is respectively as a bias voltage output of whole bias-voltage generating circuit;
Drive current is greater than the second bias-voltage generating circuit of described first bias-voltage generating circuit, comprise the source follower circuit identical with the number of described bias voltage output, the output terminal of each described source follower circuit connects a described bias voltage output;
Each described source follower circuit comprises more than one MOS transistor source follower and more than one first mos transistor switch; The break-make being controlled described first mos transistor switch by clock signal controls being turned on or off of described source follower circuit;
The source voltage of each described MOS transistor source follower is as the output end voltage of the described source follower circuit of correspondence, and the voltage that output terminal during each described source follower circuit conducting exports is identical with the voltage that described first bias-voltage generating circuit exports at the described bias voltage output of correspondence; Add grid voltage at the grid of each described MOS transistor source follower, the gate source voltage of each described MOS transistor source follower is a threshold voltage and is determined the On current of corresponding described source follower circuit by this gate source voltage;
The drive current of bias voltage output corresponding during described source follower circuit conducting is formed by the drive current superposition of described first bias-voltage generating circuit and described second bias-voltage generating circuit; The drive current of bias voltage output corresponding when described source follower circuit disconnects is determined by the drive current of described first bias-voltage generating circuit.
2. bias-voltage generating circuit as claimed in claim 1, it is characterized in that: each described source follower circuit comprises two described MOS transistor source followers and two described first mos transistor switches, two described first mos transistor switches are respectively the first PMOS and the 4th NMOS tube, and two described MOS transistor source followers are respectively the 2nd NOMS pipe, the 3rd PMOS; Described first PMOS, described 2nd NOMS pipe, described 3rd PMOS and described 4th NMOS tube series connection are between the supply voltage and ground, the source electrode of described first PMOS connects described supply voltage, the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, the source electrode of described second NMOS tube be connected with the source electrode of described 3rd PMOS and this link position as the output terminal of the described source follower circuit of correspondence; The drain electrode of described 3rd PMOS is connected with the drain electrode of described 4th NMOS tube, the source ground of described 4th NMOS tube;
The second clock signal that first clock signal of the grid connection of described first PMOS is connected with the grid of described 4th NMOS tube is anti-phase each other, the grid of described second NMOS tube connects primary grid voltage, the grid of described 3rd PMOS connects second grid voltage, arranges the output end voltage of corresponding described source follower circuit by arranging described primary grid voltage and described second grid voltage.
3. bias-voltage generating circuit as claimed in claim 1, it is characterized in that: the output voltage of the bias voltage output of described bias-voltage generating circuit is input to bias control circuit, the output terminal of described bias control circuit exports multiple common signal and multiple block signal, each described common signal and each described block signal are input to liquid crystal panel and drive described liquid crystal panel work, and each described common signal or each described block signal can change respectively between the bias voltage of each bias voltage output of described bias-voltage generating circuit; When each described common signal or each described block signal change, with the described source follower circuit conducting corresponding to the described bias voltage output corresponding to the bias voltage after each described common signal or each described block signal change, described source follower circuit corresponding after postponing certain hour disconnects.
4. bias-voltage generating circuit as claimed in claim 3, is characterized in that: the size of the drive current of described second bias-voltage generating circuit meets makes transformation period when each described common signal or each described block signal change narrow down to required value; The drive current of described first bias-voltage generating circuit maintains required value scope for making the size of the described common signal or each described block signal that are input to described liquid crystal panel between twice change.
5. bias-voltage generating circuit as claimed in claim 3, it is characterized in that: the drive current size regulating described first bias-voltage generating circuit by adjusting each described divider resistance, the size of the drive current of described first bias-voltage generating circuit is wanted to compensate the leakage current produced between the public pole of described liquid crystal panel and segmentation pole.
6. bias-voltage generating circuit as claimed in claim 1, it is characterized in that: described first bias-voltage generating circuit also comprises one second mos transistor switch, the source-drain electrode of described second mos transistor switch is connected on the path of each described divider resistance, and the grid of described second mos transistor switch connects a control signal to control the turn-on and turn-off of described first bias-voltage generating circuit.
7. bias-voltage generating circuit as claimed in claim 1 or 2, it is characterized in that: described second bias-voltage generating circuit also comprises one source pole follower control circuit, for providing described clock signal to control the break-make of described first mos transistor switch and to provide the grid voltage of described MOS transistor source follower to control the output end voltage of described source follower circuit.
8. a liquid crystal display drive circuit, is characterized in that, the bias-voltage generating circuit of liquid crystal display drive circuit comprises:
First bias-voltage generating circuit, comprise the multiple divider resistances be series between supply voltage and ground, the cascaded structure of described divider resistance carries out dividing potential drop to described supply voltage and forms multiple bias voltage, and the output terminal of each described bias voltage of described first bias-voltage generating circuit is respectively as a bias voltage output of whole bias-voltage generating circuit;
Drive current is greater than the second bias-voltage generating circuit of described first bias-voltage generating circuit, comprise the source follower circuit identical with the number of described bias voltage output, the output terminal of each described source follower circuit connects a described bias voltage output;
Each described source follower circuit comprises more than one MOS transistor source follower and more than one first mos transistor switch; The break-make being controlled described first mos transistor switch by clock signal controls being turned on or off of described source follower circuit;
The source voltage of each described MOS transistor source follower is as the output end voltage of the described source follower circuit of correspondence, and the voltage that output terminal during each described source follower circuit conducting exports is identical with the voltage that described first bias-voltage generating circuit exports at the described bias voltage output of correspondence; Add grid voltage at the grid of each described MOS transistor source follower, the gate source voltage of each described MOS transistor source follower is a threshold voltage and is determined the On current of corresponding described source follower circuit by this gate source voltage;
The drive current of bias voltage output corresponding during described source follower circuit conducting is formed by the drive current superposition of described first bias-voltage generating circuit and described second bias-voltage generating circuit; The drive current of bias voltage output corresponding when described source follower circuit disconnects is determined by the drive current of described first bias-voltage generating circuit.
9. liquid crystal display drive circuit as claimed in claim 8, it is characterized in that: the output voltage of the bias voltage output of described bias-voltage generating circuit is input to bias control circuit, the output terminal of described bias control circuit exports multiple common signal and multiple block signal, each described common signal and each described block signal are input to liquid crystal panel and drive described liquid crystal panel work, and each described common signal or each described block signal can change respectively between the bias voltage of each bias voltage output of described bias-voltage generating circuit; When each described common signal or each described block signal change, with the described source follower circuit conducting corresponding to the described bias voltage output corresponding to the bias voltage after each described common signal or each described block signal change, described source follower circuit corresponding after postponing certain hour disconnects.
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| CN107170420A (en) * | 2017-07-12 | 2017-09-15 | 深圳市航顺芯片技术研发有限公司 | A kind of circuit structure for LCD driving bias voltages |
| CN107610667A (en) * | 2017-10-19 | 2018-01-19 | 深圳市博巨兴实业发展有限公司 | A kind of New type LCD drive circuit |
| CN108242221A (en) * | 2016-12-27 | 2018-07-03 | 无锡中微爱芯电子有限公司 | A kind of low-power consumption height driving LCD bias driving circuits being integrated in MCU |
| CN109192127A (en) * | 2018-10-29 | 2019-01-11 | 合肥鑫晟光电科技有限公司 | Sequence controller and its driving method, display device |
| CN111052211A (en) * | 2017-09-05 | 2020-04-21 | 株式会社电装 | Drive circuit of liquid crystal panel and liquid crystal display device |
| CN113568460A (en) * | 2020-04-29 | 2021-10-29 | 无锡华润上华科技有限公司 | Bias current generating circuit and flash memory |
| CN116774101A (en) * | 2023-08-21 | 2023-09-19 | 保定传能电子科技有限公司 | Low-voltage line leakage current detection device |
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| CN116774101B (en) * | 2023-08-21 | 2023-10-27 | 保定传能电子科技有限公司 | Low-voltage line leakage current detection device |
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