CN104516997A - Timing analysis method and machine-readable medium - Google Patents

Abstract

A timing analysis method applied to a circuit of a non-standard component, comprising: finding out at least one first buffer and one second buffer in the circuit; calculating at least one path time delay required for passing through at least one path between the first buffer and the second buffer; calculating a first buffer clock pulse time delay from a first clock pulse source to a first buffer clock pulse input end of the first buffer, and calculating a second clock pulse source to a second buffer clock pulse input end of the second buffer and a second buffer clock pulse time delay; determining whether the second buffer has a timing error according to the at least one path time delay, the first buffer clock time delay, the second buffer clock time delay, and a first buffer time delay of the first buffer.

Description

Timing analysis method and machine-readable medium

technical field

The disclosed embodiments of the present invention are related to verification of circuit design, especially to a timing analysis method and machine-readable medium applied in a circuit using non-standard cells.

Background technique

In practice, for analog circuits using non-standard components, in the verification stage, functional simulation verification is generally carried out for the entire analog circuit, and the limited test pattern (test pattern) is used to verify the simulation as much as possible. Whether the main function of the circuit is correct. However, the limited test mode not only takes a long time to simulate, but also makes it difficult to achieve leak-free timing analysis. Designers often give up complete timing verification in pursuit of efficiency. Therefore, there is an urgent need in the art for a timing analysis method that can take both efficiency and test coverage into consideration.

Contents of the invention

One of the objectives of the present invention is to provide a timing analysis method and a machine-readable medium applied to circuits using non-standard cells, so as to solve the above-mentioned problems.

An embodiment of the present invention discloses a timing analysis method applied in a circuit using non-standard components, including: finding at least a first register and a second register in the circuit, wherein The first register and the second register have at least one path between each other, from a first register data output end of the first register to a second register data input end of the second register; calculating at least one path time delay required to traverse the at least one path; calculating a first buffer clock time delay from a first clock source to a first buffer clock input of the first buffer, and calculating a second clock source to a second buffer clock input of the second buffer and a second buffer clock time delay; and according to the at least one path time delay, the first buffer clock time delay, the clock pulse time delay of the second register, and a first register time delay of the first register to determine whether there is a timing error in the second register.

Another embodiment of the present invention discloses a machine-readable medium storing a program code. When the program code is executed by a processor, the program code will cause the processor to perform the following steps to control the application using non- Timing analysis of a circuit of a standard component: finding at least one first register and a second register in the circuit, wherein the first register and the second register have at least one path between each other, from the A first buffer data output end of the first buffer to a second buffer data input end of the second buffer; calculating at least one path time delay required by the at least one path; calculating a first clock pulse time delaying a first register clock sourced to a first register clock input of the first register, and calculating a second clock sourced to a second register clock input of the second register end and a second buffer clock pulse time delay; and according to the at least one path time delay, the first buffer clock pulse time delay, the second buffer clock pulse time delay, and a first buffer clock delay of the first buffer A buffer time delay is used to determine whether the second register has a timing error.

The invention can improve the coverage of timing analysis of non-standard component circuits, while taking into account the time efficiency.

Description of drawings

Figure 1 is a schematic diagram of a circuit using non-standard components.

FIG. 2 is a flow chart of an exemplary embodiment of the timing analysis method applied in a circuit using non-standard components according to the present invention.

FIG. 3 is a schematic diagram of an embodiment of the present invention directed to a computer system implementing a timing analysis method using circuits with non-standard components.

Wherein, the reference signs are explained as follows:

100 circuits

102, 104 buffer

103 path

106～110 combination circuit

200 process

202～208 steps

300 computer systems

302 processor

304 Machine-readable media

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a circuit 100 using non-standard components. Please note that in order to illustrate the technical features of the present invention, FIG. 1 only shows a part of circuit components, including a plurality of registers 102 , 104 and a plurality of combinational circuits 106 , 108 , 110 . Please note that the circuit 100 may contain analog circuits or any other circuits that cannot only use standard components in the standard cell library (standard cell library), that is, the circuit 100 contains non-standard components; and the combined circuits 106, 108, and 110 may Contains any transistors, basic logic gates (logical gates) (such as AND gates, OR gates, etc.) or logic circuits composed of basic logic gates, and the combination circuits 106, 108, 110 may be different; the registers 102, 104 can be any kind of register, such as a D-latch or a D-flip flop, as long as it is based on a clock pulse and has a data temporary storage function. Belong to the category of the present invention.

Please refer to Figure 1 and Figure 2 together. FIG. 2 is a flow chart of an exemplary embodiment of the timing analysis method applied in a circuit using non-standard components according to the present invention. If substantially the same result can be achieved, it is not necessary to follow the sequence of steps in the process 200 shown in FIG. 2 , and the steps shown in FIG. 2 do not have to be performed continuously, that is, other steps can also be inserted, In addition, some steps in FIG. 2 can also be omitted according to different embodiments or design requirements. The method mainly includes the following steps:

Step 202: Find at least a first register and a second register in a circuit using non-standard components, wherein the first register and the second register have at least one path between each other, from the first register a first register data output terminal of a buffer to a second register data input terminal of the second register;

Step 204: Calculate at least one path time delay required to pass through the at least one path;

Step 206: Calculate a first register clock time delay from a first clock source to a first register clock input of the first register, and calculate a second clock source to the second register of a second buffer clock input and a second buffer clock time delay; and,

Step 208: Determine the second buffer according to the at least one path time delay, the clock time delay of the first register, the clock time delay of the second register, and a first register time delay of the first register Whether there is a timing violation in the device.

For step 202 of the process 200, it should be noted that all or part of the registers in the circuit using non-standard components can be found according to the required test coverage or the scope of analysis, and It is not limited to the method used to find all registers or some registers. For example, the present invention preferably can use a specific register identification method, which can be identified according to the default register transistor connection or composition Registers in circuit 100. Therefore, for FIG. 1 , it is assumed that the scope to be analyzed here is part of the registers of the circuit 100 , namely, the register 102 and the register 104 . First, the register 102 and the register 104 can be identified on the transistor level netlist of the circuit 100 according to the connection or composition of the transistors, and then the register 102 and the register 104 need to be analyzed. Next, it is necessary to confirm whether there is at least one path between the buffer 102 and the buffer 104, that is, to find out a path from a data output terminal Q of the buffer 102 to a data input D of the buffer 102 through the combinational circuit 110 ( For example, path 103 in this embodiment).

Step 204 calculates a path time delay of at least one path between the register 102 and the register 102, that is, finds out that in FIG. 1, a signal passes through the combinational circuit 110 to the The path time delay of the path 103 of the data input D of the buffer 102 . For example, general analog circuit simulation software can be used to simulate only the path 103 and calculate the corresponding path time delay, which can greatly reduce the time required for simulation.

Next, in step 206, a first clock pulse time delay from a clock pulse source P to a clock pulse input terminal ck_in of the buffer 102 in FIG. 1 and a time delay from the clock pulse source P to the buffer 104 are calculated respectively. A second clock pulse time delay of a clock pulse input terminal ck_in. Please note that in another embodiment, the clock source P mentioned in step 206 may also refer to a different clock source.

Finally, according to the data setup time (data setup time) specification and the data hold time (data hold time) specification of the buffer 104, from the data output terminal Q of the buffer 102 to the data input terminal D of the buffer 102 through the combination circuit 110 The path time delay, the first clock time delay, the second clock time delay and a buffer time delay of the register 102 are used to determine whether the register 104 has a set time error or a hold time error (step 208 ). Since those skilled in the art should easily understand the way of determining whether the setting time is wrong or the keeping time is wrong, further details will not be repeated here.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of an embodiment of the present invention directed to a computer system for implementing a timing analysis method in a circuit using non-standard components. The computer system 300 includes a processor 302 and a machine-readable medium 304. For example, the computer system 300 can be a personal computer, and the machine-readable medium 304 can be any storage device with a data storage function in the personal computer, such as Volatile memory, non-volatile memory, hard disk, CD, etc. In this embodiment, a program code PROG is stored in the machine-readable medium 304. Therefore, when the program code PROG is loaded and executed by the processor 302, the program code PROG will cause the processor 302 to execute the circuit design file File_IN of the integrated circuit. The timing analysis method disclosed in the present invention (that is, steps 202-208 shown in FIG. 2). Since those skilled in the art can easily understand the timing analysis operation performed by the processor 302 executing the program code PROG after reading the above content on the timing analysis method, further description is omitted here for brevity.

To sum up, with the timing analysis method applied in circuits using non-standard components proposed by the present invention, timing analysis can be performed only based on the identified registers and the paths between the registers, so that It will significantly reduce the time required for simulation and take into account the test coverage.

Claims (8)

1. be applied in the Time Series Analysis Method in the circuit using non-standard features, it is characterized in that, include:

Find out at least one first buffer in this circuit and one second buffer, wherein this first buffer and this second buffer have at least one path, the one second buffer data input end from one first buffer data output terminal of this first buffer to this second buffer each other;

Calculate and postpone through at least one path time needed for this at least one path;

Calculate the one first buffer clock pulse time delay of one first clock source to one first buffer clock pulse input terminal of this first buffer, and calculate the one second buffer clock pulse time delay of a second clock impulse source to one second buffer clock pulse input terminal of this second buffer; And,

Postpone according to this at least one path time, this first buffer clock pulse time postpones, this second buffer clock pulse time postpones and one first buffer time delay of this first buffer judges whether this second buffer exists timing error.

2. method according to claim 1, wherein, calculates the step postponed through this at least one path time needed for this at least one path and includes:

The component hour obtaining the assembly in this at least one path postpones; And,

Postpone according to this component hour this at least one path time calculated through needed for this at least one path to postpone.

3. method according to claim 1, wherein, postpone according to this at least one path time, this first buffer clock pulse time postpone, this second buffer clock pulse time postpones and this first buffer time delay of this first buffer judges that the step whether this second buffer exists timing error includes:

According to the data setup times specification of this second buffer and data hold time specification, this at least one path time postpones, this first buffer clock pulse time postpones, this second buffer clock pulse time postpones and this first buffer time delay of this first buffer judges whether this second buffer exists setup times mistake or retention time mistake.

4. method according to claim 1, wherein, the step finding out at least one first buffer in this circuit and one second buffer includes:

Transistor connected mode according to this circuit picks out this first buffer and this second buffer.

5. a machine-readable medium, it is characterized in that, store a program code, when this program code is performed by a processor, this program code can cause this processor to perform following step to use a circuit of non-standard features to carry out time series analysis to being applied in:

Find out at least one first buffer in this circuit and one second buffer, wherein this first buffer and this second buffer have at least one path, the one second buffer data input end from one first buffer data output terminal of this first buffer to this second buffer each other;

Calculate and postpone through at least one path time needed for this at least one path;

Calculate one first clock source to this first buffer one first buffer clock pulse input terminal one first buffer clock pulse time postpone, and calculate a second clock impulse source to this second buffer one second buffer clock pulse input terminal and one second buffer clock pulse time postpone; And,

Postpone according to this at least one path time, this first buffer clock pulse time postpones, this second buffer clock pulse time postpones and one first buffer time delay of this first buffer judges whether this second buffer exists timing error.

6. machine-readable medium according to claim 5, wherein, calculates the step postponed through this at least one path time needed for this at least one path and includes:

The component hour obtaining the assembly in this at least one path postpones; And

Postpone according to this component hour this at least one path time calculated through needed for this at least one path to postpone.

7. machine-readable medium according to claim 5, wherein, postpone according to this at least one path time, this first buffer clock pulse time postpone, this second buffer clock pulse time postpones and this first buffer time delay of this first buffer judges that the step whether this second buffer exists timing error includes:

According to the data setup times specification of this second buffer and data hold time specification, this at least one path time postpones, this first buffer clock pulse time postpones, this second buffer clock pulse time postpones and this first buffer time delay of this first buffer judges whether this second buffer exists setup times mistake or retention time mistake.

8. machine-readable medium according to claim 5, wherein, the step finding out at least one first buffer in this circuit and one second buffer includes:

Transistor connected mode according to this circuit picks out this first buffer and this second buffer.