CN104505351A - Preparation method of laterally interconnected stacked packaging structure - Google Patents

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a method for preparing a laterally interconnected stacked packaging structure. The structure includes an upper-layer package and a lower-layer package. The method includes: making an upper layer with a plurality of interlayer solder balls at the bottom Package; making a lower package with a redistribution layer and a lateral interconnection structure, wherein the redistribution layer is formed on top of the lower plastic package of the lower package, and the lateral interconnection structure is formed on the lower plastic package of the lower package Align and weld the upper package body and the lower package body, so that multiple layer solder balls, redistribution layers and lateral interconnection structures form interconnection channels, and then form a stacked package structure of lateral interconnection. The invention increases the number of interconnection channels between the upper package and the lower package by utilizing the lateral interconnection and the redistribution layer on the plastic-encapsulated top. The invention also combines the lateral interconnection structure with the through-molding via hole technology to further increase the number of interconnection channels between the upper package body and the lower package body.

Description

A method for preparing a stacked packaging structure with lateral interconnection

technical field

The invention relates to the technical field of semiconductor packaging, in particular to a method for preparing a laterally interconnected stacked packaging structure.

Background technique

Stacked (Package on Package, PoP) packaging is a typical 3D packaging technology, mainly used in the integration of processors and memory systems, and its typical product is Apple's A7 processor. As the demand for memory bandwidth continues to increase, the main bottleneck restricting the application of PoP packaging is the limited number of interconnection solder balls between the upper and lower layers of the traditional PoP structure, that is, the limited number of effective memory channels.

Companies represented by Amkor and Samsung have two types of mass-produced PoP packages: flip-chip size package-stacked package (fcCSP-PoP) as shown in Figure 1 and such as Figure 2 shows the Through Molded Via - Flip Chip Stacked Package (TMV-fcPoP). Among them, the chips in the upper and lower packages can be wire bonded (Wire Bond, WB), flip chip soldered (Flip Chip, FC) or a combination of the two, and can be stacked or tiled. Through molding vias (TMV) are filled with solder balls to realize the interconnection of the upper and lower layers. In order to improve memory bandwidth, various companies are committed to reducing the size and spacing of interlayer solder balls (Solder ball)/TMV, but they are all limited by process and yield.

Some patents and articles have also evolved many packaging structures or integrated more functions based on the concept of PoP upper and lower packaging 3D interconnection. for example:

In the patent System and method for shielding of Package on Package (PoP) assemblies, US7851834B1, Amkor company forms a PoP structure with a shielding structure on the basis of TMV-fcPoP for radio frequency (RF), as shown in Figure 3.

In FIG. 4, the conductive coating 32 is connected to the metal line 16a (ground) to form a shielding structure for RF shielding. The conductive coating 32 can be realized by processes such as electroplating, vacuum printing, vacuum deposition, insert molding, and spraying. Similarly, this patent is also suitable for solder ball filling to realize the interconnection between the upper and lower layers of the TMV.

Taiwan's semiconductor manufacturing company adopts a fan-in stacked package (Fan-in PoP) structure. The lower package is mainly composed of a polymer layer and a Si-based substrate and the active chips contained therein, and various dielectrics are filled in the via holes. The material forms a resistive/capacitive passive device [Package-on-Package (PoP) Device with Integrated Passive Device, US7692311B2], as shown in Figure 5. The upper and lower packages in this patent mainly adopt the front-end process and material system, which is significantly different from the traditional PoP package proposed by Amkor and Samsung.

Scholars from the Singapore Agency for Science, Technology and Research (A*STAR) stacked the upper and lower layers of embedded wafer level packaging (EWLP), using the TMV on the plastic packaging material and the redistribution layer on the top of the plastic packaging ( Redistribution layer (RDL) technology, and a substrate integrated waveguide (SIW) resonator composed of TMV, integrated in the package structure, as shown in Figure 6. EWLP stack packaging mainly adopts wafer-level packaging, which is obviously different from traditional PoP packaging with organic substrate structure [Rui Li, Boo Yang Jung, et al., Novel HighPerformance Millimeter-Wave Resonator and Filter Structures using Embedded Wafer Level Packaging( EWLP) Technology, Electronics Packaging Technology Conference (EPTC 2013), pp: 844-847].

The latter two packaging forms, namely fan-in stack package (Fan-in PoP) structure and embedded wafer level packaging (embedded wafer level packaging, EWLP) stack structure, compared with fcCSP-PoP and TMV-fcPoP two mainstream The packaging form is still in the research stage, and its application is relatively narrow.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to propose a method for preparing a stacked packaging structure with lateral interconnection for the mainstream PoP packaging forms represented by Amkor and Samsung, and the number of interlayer channels is limited, so as to improve the interlayer The number of interconnect channel counts.

(2) Technical solutions

In order to achieve the above object, the present invention provides a method for preparing a laterally interconnected stacked package structure, the stacked package structure includes an upper package and a lower package, the method includes: making a package with a plurality of interlayer solder balls at the bottom An upper package; making a lower package with a redistribution layer and a lateral interconnect structure, wherein the redistribution layer is formed on top of the lower plastic package of the lower package, and the lateral interconnect structure is formed on the lower layer of the lower package Around the plastic package: Align and solder the upper package body and the lower package body, so that multiple interlayer solder balls, redistribution layers and lateral interconnection structures form interconnection channels, and then form a stacked package structure of lateral interconnection.

In the above solution, the fabrication of the upper package with a plurality of interlayer solder balls at the bottom includes:

Step 1: Manufacture the upper substrate by lamination process or stacking process, and then slice the upper substrate to form long substrates for subsequent packaging processes, each long substrate contains several packaging units;

Step 2: Use the eutectic bonding method, welding bonding method, conductive adhesive bonding method or glass bonding method to combine the upper bare chip and the long substrate through conductive adhesive or patch adhesive;

Step 3: Electrically interconnect the upper die and the strip substrate by ultrasonic bonding, thermocompression bonding or thermosonic bonding;

Step 4: Form an upper plastic seal around the upper die using transfer molding technology, injection molding technology or pre-molding technology to protect the upper die;

Step 5: Plant balls on the bottom of the strip substrate to form multiple interlayer solder balls;

Step 6: Cutting the long substrate into several upper package units to obtain an upper package with multiple interlayer solder balls at the bottom.

In the above solution, the material used for the plurality of interlayer solder balls in step 5 is solder, and a full disk arrangement or an outer ring arrangement is adopted between the upper package and the lower package.

In the above solution, the manufacturing of the lower package with the redistribution layer and the lateral interconnection structure includes:

Step 11: Manufacture the lower substrate by lamination process or lamination process, and then slice the lower substrate to form strip substrates for subsequent packaging process, each strip substrate contains several packaging units;

Step 12: Directly bond the lower die face-down die soldering area to the long substrate soldering area; and through the underfill process, inject epoxy resin material between the lower die and the long substrate to protect the soldering point, the epoxy resin is cured through the curing oven, in order to reduce the stress and strain caused by the difference in thermal expansion coefficient between the bare chip and the long substrate;

Step 13: Using transfer molding technology, injection molding technology or pre-molding technology to form a lower plastic seal around the lower die to protect the lower die;

Step 14: using laser etching to ablate the lower plastic package to form via holes for forming lateral interconnection structures;

Step 15: Apply electroless plating and copper electroplating to the lower plastic package with vias in sequence, and plate the vias with copper to form metallized vias with a lateral interconnection structure, and at the same time form a redistribution layer on the lower plastic package;

Step 16: cutting each strip of substrate into several lower packaging substrate units with redistribution layers and lateral interconnection structures;

Step 17: Coating the metal copper with electroless gold tweezers or palladium gold tweezers on the outside of the metal copper in the lateral interconnection structure to prevent oxidation of the metal copper;

Step 18: Plant balls on the bottom of the package substrate unit by means of a full disk arrangement or an outer ring arrangement, and clean the residual solder on the bottom pad to obtain a lower package with a redistribution layer and a lateral interconnection structure.

In the above solution, the underfill process described in step 12 and the plastic encapsulation process described in step 13 are replaced by a molding underfill process.

In the above scheme, when the via hole formed in step 14 is a quadrilateral via hole, the lower plastic package is ablated by a continuous laser etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

In the above solution, the redistribution layer adopts a multi-layer structure, and the formation of the redistribution layer on the lower plastic package in step 15 includes: sequentially adopting electroless plating and electroplating copper processes to form the second layer of the redistribution layer on the lower plastic package. One layer of metal layer; followed by exposure and etching to complete the patterning of the first metal layer of the redistribution layer, followed by lamination of dielectric layers, laser drilling blind holes to form interlayer blind holes in the redistribution layer, and then sequentially using chemical Plating and electroplating metal copper processes to form the second metal layer in the hole and the redistribution layer; then sequentially adopt exposure and etching to complete the patterning of the second metal layer of the redistribution layer, and then sequentially use a laminated dielectric layer, laser drilling blind The hole forms the interlayer blind hole of the redistribution layer, and then uses the electroless plating and electroplating metal copper processes to form the third layer of metal layer in the hole and the redistribution layer; and so on, repeat the above to form the second layer of metal layer or the third layer The multi-layer metal layer process forms the multi-layer metal layer of the redistribution layer; after forming the outermost metal layer, a patterned pad is formed to interconnect with the upper package.

In the above solution, the manufacturing of the lower package with the redistribution layer and the lateral interconnection structure includes:

Step 21: Manufacture the lower substrate by lamination process or lamination process, and then slice the lower substrate to form strip substrates for subsequent packaging process, each strip substrate contains several packaging units;

Step 22: mounting discrete devices on the surface of the strip substrate;

Step 23: Directly bond the lower die face-down die soldering area to the long substrate soldering area; and through the underfill process, inject epoxy resin material between the lower die and the long substrate to protect the soldering point, the epoxy resin is cured through the curing oven, in order to reduce the stress and strain caused by the difference in thermal expansion coefficient between the bare chip and the long substrate;

Step 24: Using transfer molding technology, injection molding technology or pre-molding technology to form a lower plastic seal around the lower die to protect the upper and lower die;

Step 25: using laser etching to ablate the lower plastic package to form via holes for forming lateral interconnection structures and through-molding vias;

Step 26: Use electroless plating and electroplating to form a copper ring in turn on the lower plastic package with vias to form a lateral interconnection structure and through-molded metallized vias; use the resin plugging process to test the interconnection structure and penetration The molded metallized vias are filled to support the redistribution layer and prevent the copper metal oxidation of the lateral interconnection structure; at the same time, a redistribution layer is formed on the lower plastic package;

Step 27: Plant balls on the bottom of the long substrate by means of full disk arrangement or outer ring arrangement, and clean the residual solder on the bottom pad;

Step 28: Cutting each strip of substrate into several lower package units with redistribution layer and lateral interconnection structure to obtain lower package body with redistribution layer and lateral interconnection structure.

In the above solution, the underfill process described in step 23 and the plastic encapsulation process described in step 24 are replaced by a molding underfill process.

In the above solution, when the via hole formed in step 25 is a quadrilateral via hole, the lower plastic package is ablated by a continuous laser etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

In the above solution, the redistribution layer adopts a multi-layer structure, and the formation of the redistribution layer on the lower plastic package as described in step 26 includes: sequentially adopting electroless plating and electroplating copper plating processes to form the second layer of the redistribution layer on the lower plastic package. One layer of metal layer; followed by exposure and etching to complete the patterning of the first metal layer of the redistribution layer, followed by lamination of dielectric layers, laser drilling blind holes to form interlayer blind holes in the redistribution layer, and then sequentially using chemical Plating and electroplating metal copper processes to form the second metal layer in the hole and the redistribution layer; then sequentially adopt exposure and etching to complete the patterning of the second metal layer of the redistribution layer, and then sequentially use a laminated dielectric layer, laser drilling blind The hole forms the interlayer blind hole of the redistribution layer, and then uses the electroless plating and electroplating metal copper processes to form the third layer of metal layer in the hole and the redistribution layer; and so on, repeat the above to form the second layer of metal layer or the third layer The multi-layer metal layer process forms the multi-layer metal layer of the redistribution layer; after forming the outermost metal layer, a patterned pad is formed to interconnect with the upper package.

In the above solution, the manufacturing of the lower package with the redistribution layer and the lateral interconnection structure includes:

Step 31: Manufacture the lower substrate by lamination process or lamination process, and then slice the lower substrate to form strip substrates for subsequent packaging process, each strip substrate contains several packaging units;

Step 32: Directly bond the lower die face-down die soldering area to the long substrate soldering area; and through the underfill process, inject epoxy resin material between the lower die and the long substrate to protect the soldering point, the epoxy resin is cured through the curing oven, in order to reduce the stress and strain caused by the difference in thermal expansion coefficient between the bare chip and the long substrate;

Step 33: Use eutectic bonding method, soldering bonding method, conductive adhesive bonding method or glass glue bonding method to attach the lower bare die on the long substrate, and use ultrasonic bonding and thermocompression bonding or thermosonic bonding to electrically interconnect the underlying die with the elongated substrate;

Step 34: Using transfer molding technology, injection molding technology or pre-molding technology to form a lower plastic seal around the lower die to protect the upper and lower die;

Step 35: using laser etching to ablate the lower plastic package to form via holes for forming lateral interconnection structures and through-molding vias;

Step 36: Apply electroless plating and copper electroplating to the lower plastic package with vias in sequence, and plate the vias with copper to form lateral interconnection structures and copper-plated through-molded vias, and form them on the lower plastic package at the same time redistribution layer;

Step 37: cutting each strip of substrate into several lower packaging substrate units with redistribution layers and lateral interconnection structures;

Step 38: Coating the metal copper with electroless gold tweezers or palladium gold tweezers on the outside of the metal copper in the lateral interconnection structure to prevent oxidation of the metal copper;

Step 39: Plant balls on the bottom of the package substrate unit by means of a full disk arrangement or an outer ring arrangement, and clean the residual solder on the bottom pad to obtain a lower package with a redistribution layer and a lateral interconnection structure.

In the above solution, when the via hole formed in step 34 is a quadrilateral via hole, the lower plastic package is ablated by a continuous laser etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

In the above solution, the redistribution layer adopts a multi-layer structure, and the formation of the redistribution layer on the lower plastic package as described in step 36 includes: sequentially adopting electroless plating and electroplating copper plating processes to form the second layer of the redistribution layer on the lower plastic package. One layer of metal layer; followed by exposure and etching to complete the patterning of the first metal layer of the redistribution layer, followed by lamination of dielectric layers, laser drilling blind holes to form interlayer blind holes in the redistribution layer, and then sequentially using chemical Plating and electroplating metal copper processes to form the second metal layer in the hole and the redistribution layer; then sequentially adopt exposure and etching to complete the patterning of the second metal layer of the redistribution layer, and then sequentially use a laminated dielectric layer, laser drilling blind The hole forms the interlayer blind hole of the redistribution layer, and then uses the electroless plating and electroplating metal copper processes to form the third layer of metal layer in the hole and the redistribution layer; and so on, repeat the above to form the second layer of metal layer or the third layer The multi-layer metal layer process forms the multi-layer metal layer of the redistribution layer; after forming the outermost metal layer, a patterned pad is formed to interconnect with the upper package.

In the above solution, the lateral interconnection structure is connected to the metal layer in the redistribution layer on the top, and connected to the lower substrate of the lower package body below, and is formed by circular via holes or a row of circular via holes. The quadrilateral vias are sequentially filled with copper by electroless plating and electroplating, and sliced to form discrete half-via, multi-half-via structures or cubic structures.

In the above solution, the metal material in the lateral interconnection structure is fully or mostly covered by resin, tweezer gold or tweezer palladium gold, so as to prevent the metal material from being oxidized.

In the above solution, the redistribution layer is composed of a metal layer and a dielectric layer, the metal layer is used to realize electrical interconnection, and the dielectric layer is used to realize isolation between interconnection lines or layers. The redistribution layer includes a single layer of metal or multiple layers of metal.

In the above solution, the upper-layer package includes an upper-layer substrate, an upper-layer die, and an upper-layer plastic package, wherein: the upper-layer die is formed on the upper-layer substrate, and the upper-layer die and the upper-layer substrate are bonded by conductive glue or patch glue, Or use wire bonding or flip-chip bonding; the upper layer plastic package surrounds the upper layer die to protect the upper layer die; the lower layer package includes a lower layer substrate, a lower layer die, a lower layer plastic package, a redistribution layer, The lateral interconnection structure and the bottom ball grid array solder balls, wherein: the lower die is formed on the lower substrate, and the lower die and the lower substrate are combined by conductive glue or patch glue, or by wire bonding or inverted Combination of soldering method; the lower plastic package surrounds the lower die to protect the lower die and support the lateral interconnection structure; the lower ball grid array solder balls are formed under the lower substrate to realize the lower die The electrical interconnection between the package and the PCB substrate.

In the above solution, the upper substrate contains a plurality of upper-layer thermal holes, and the lower substrate contains a plurality of lower-layer thermal holes, and the upper-layer thermal holes are sequentially connected with the interlayer solder balls and the single-layer metal or multi-layer metal contained in the redistribution layer. The metal, the lateral interconnection structure and the lower layer heat conduction hole form the 3D heat dissipation channel of the stacked package structure.

In the above solution, when the redistribution layer is connected to the lateral interconnection structure and the ground layer in the lower substrate, it can form an electromagnetic shield for electromagnetic isolation of the lower die.

In the above solution, the lower package body further includes a plurality of through-molding vias, which are formed under part or all of the interlayer solder balls and penetrate the redistribution layer and the lower-layer plastic package.

In the above scheme, electroless plating, electroplated copper full holes or electroplated copper rings are sequentially used in the through-molding vias, so that interlayer solder balls, redistribution layers and through-molding vias form interconnection channels to realize the through-molding vias. An electrical interconnection between the upper package and the lower package.

In the above solution, when the metal copper in the through-molding via hole is an electroplated copper ring, plug hole technology is used to support the redistribution layer.

In the above solution, the plugging technology adopts soldering or filling resin in the through-molding via hole.

In the above solution, there is at least one of the upper die or the lower die, and when there are multiple, the upper die is arranged on the upper substrate in a manner of stacking, tiling, embedding or embedding. The lower-layer bare chips are arranged on the lower-layer substrate in a manner of stacking, tiling, embedding or embedding.

In the above solution, the upper die uses gold wires, copper wires or silver wires to realize electrical interconnection with interconnection lines and vias in the upper substrate, and the lower die uses controllable collapse chip connection bumps or copper pillars The bumps are electrically interconnected with interconnect lines and vias in the underlying substrate.

In the above solution, the upper die or the lower die are replaced by discrete devices.

(3) Beneficial effects

Compared with the fcCSP-PoP shown in Figure 1 and the TMV-fcPoP package shown in Figure 2, the method for preparing a laterally interconnected stacked package structure provided by the present invention mainly has the following advantages:

1. The preparation method of the lateral interconnection stacked packaging structure provided by the present invention, the processing size of the lateral interconnection structure process can be smaller than the diameter of the solder ball, and the number of channels between the upper and lower layers can be compared with the traditional packaging form.

2. According to the preparation method of the stacked packaging structure with lateral interconnection provided by the present invention, TMV can use Amkor’s traditional solder ball filling method to realize upper and lower packaging, and can also use electroless plating and electroplating hole filling methods to realize upper and lower interconnection and hole filling. It can be realized by filling or electroplating copper and other metals and then filling resin and other materials.

3. The preparation method of the stacked packaging structure with lateral interconnection provided by the present invention opens up another form of interconnection between the upper and lower layers through the lateral interconnection technology and the RDL technology. After combining with TMV technology, the increase is far greater than 1/3 of the traditional PoP structure, significantly increasing the application bandwidth. It is still possible to further increase channel count by reducing interlayer ball/TMV size and spacing.

4. The preparation method of the stacked package structure with lateral interconnection provided by the present invention, the single-layer/multi-layer RDL technology on the plastic packaging material makes the design more flexible, and can combine the thermal via in the upper substrate and the interlayer Solder balls and lateral interconnection structures form a 3D heat dissipation channel for PoP.

5. The preparation method of the stacked package structure with lateral interconnection provided by the present invention, when the RDL layer on the top of the plastic package in the lower package is connected to the lateral interconnection structure and the ground layer in the lower substrate, an electromagnetic shielding effect can be formed, which can be used for Electromagnetic isolation of the underlying RF chip. Different from the shielding structure in the patent US7851834B1: the conductive layer on the top of the lower package in the patent US7851834B1 is a large-area continuous ground plane, which is only used for shielding, while the RDL layer in the present invention can be used as a part of the shielding structure , mainly as an interconnection channel, which can be multi-layered, and the preparation scheme is also different; in the patent US7851834B1, the conductive layer located on the side of the lower package is a continuous plane, while the lateral interconnection structure in the present invention is a discrete semi- The preparation schemes are also different for via holes, mostly via structures or cube structures.

Description of drawings

1 is a schematic diagram of flip-chip size package-package-on-package (fcCSP-PoP) in the prior art;

2 is a schematic diagram of a through molded via-flip-chip stacked package (TMV-fcPoP) in the prior art;

3 is a cross-sectional view of a PoP structure with a shielding structure in the prior art;

Fig. 4 is a cross-sectional view of a PoP bottom package with a shielding structure in the prior art;

5 is a cross-sectional view of a fan-in stack package (Fan-in PoP) structure in the prior art;

FIG. 6 is a cross-sectional view of a stacked package structure of an embedded wafer level packaging (EWLP) with two upper and lower layers in the prior art;

Fig. 7 is a cross-sectional view of a PoP package structure of lateral interconnection provided by the present invention;

Fig. 8 is a cross-sectional view of the upper package body in Fig. 7;

Fig. 9 is a cross-sectional view of the lower package in Fig. 7;

10 is a top view of the position of the lateral interconnect structure in the lower package;

11 is a cross-sectional view of a PoP package structure when an electroplated copper ring is used in a TMV hole according to an embodiment of the present invention;

12 is a cross-sectional view of the PoP package structure when the TMV hole is filled with electroplated copper according to an embodiment of the present invention;

FIG. 13 is a flow chart of a method for preparing a laterally interconnected stacked package structure provided by the present invention;

Fig. 14 is a process flow chart for preparing an upper package according to Embodiment 1 of the present invention;

Fig. 15 is a process flow chart for preparing a lower package according to Embodiment 1 of the present invention;

FIG. 16 is a process flow chart for preparing a laterally interconnected stacked package structure according to Embodiment 2 of the present invention;

FIG. 17 is a flow chart of a process for preparing a laterally interconnected package-on-package structure according to Embodiment 3 of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In order to further increase the number of interlayer interconnection channels, the present invention utilizes lateral interconnection and a redistribution layer (Redistribution layer, RDL) on the top of the plastic package to form a novel lateral interconnection PoP packaging structure. Moreover, after combining the lateral interconnection structure with TMV technology, the number of channels in the upper and lower packages will be further increased. Wherein, the TMVs in the laterally interconnected PoP packaging structure are electrically interconnected sequentially by metal filling methods such as electroless plating and copper electroplating.

As shown in FIG. 7 , FIG. 7 is a cross-sectional view of a laterally interconnected PoP package structure provided by the present invention. The PoP package structure includes an upper package 100 and a lower package 200, wherein the upper package 100 and the lower package 200 are connected by a plurality of interlayer solder balls 107, a redistribution layer 208 and a lateral interconnection structure. 206 to realize electrical interconnection, a plurality of interlayer solder balls 107 are formed between the upper package 100 and the lower package 200, the redistribution layer 208 is formed on the top of the lower plastic package 201 of the lower package 200, and the side The interconnection structure 206 is formed around the lower plastic package 201 of the lower package body 200 .

The lateral interconnection structure 206 is a circular via hole or a quadrilateral via hole formed by a row of circular via holes. The via hole is sequentially filled with metal materials such as metal copper by electroless plating and electroplating, and formed into discrete semi-conductive vias after slicing. Via, Mostly Via or Cube structures. The metal material in the lateral interconnection structure 206 is fully covered or mostly covered by materials such as resin, gold tweezers or palladium gold tweezers, so as to prevent the metal materials from being oxidized. The lateral interconnection structure 206 is connected to the metal layer in the redistribution layer 208 and connected to the lower substrate 205 of the lower package body 200 . The redistribution layer 208 is composed of a metal layer and a dielectric layer. The metal layer is used to realize electrical interconnection, and the dielectric layer is used to realize isolation between interconnection lines or layers. The redistribution layer 208 may comprise a single layer of metal or multiple layers of metal. The material used for the plurality of interlayer solder balls 107 is solder, and the arrangement between the upper package body 100 and the lower package body 200 is arranged on a full disk or on an outer ring. Due to the existence of the redistribution layer 208 , the number of interlayer solder balls 107 is not limited, and can be arranged all over the disk or in the outer circle.

FIG. 8 is a cross-sectional view of the upper package 100 in FIG. 7 . The upper package 100 includes an upper substrate 105 , an upper die 103 , and an upper plastic package 101 . The upper bare chip 103 is formed on the upper substrate 105, and the upper bare chip 103 and the upper substrate 105 are bonded by conductive adhesive or patch glue, or by wire bonding or flip-chip bonding; the upper layer plastic package 101 surrounds the upper bare chip 103 around, used to protect the upper die 103 .

There is at least one upper-layer die 103 , and when there are multiple upper-layer die 103 , they are arranged on the upper-layer substrate 105 in a manner of stacking, tiling, embedding or embedding. The upper bare chip 103 is combined with the upper substrate 105 through conductive adhesive or chip adhesive 102 , and may also be combined by wire bonding or flip-chip welding. In FIG. 8 , the upper die 103 is electrically interconnected with the interconnection wires 111 in the upper substrate 105 and the upper via holes 112 by using bonding wires 104 such as gold wires, copper wires or silver wires. The upper die 103 can also be replaced by discrete devices. The via hole 112 on the upper layer is also called a thermal via when used for heat dissipation, and the electrical property of the thermal via is usually grounded.

FIG. 9 is a cross-sectional view of the lower package body 200 in FIG. 7 . The lower package 200 includes a lower die 203, a lower substrate 205, a lower plastic package 201, a redistribution layer (RDL) 208 on the top of the plastic package (the redistribution layer 208 includes a metal layer and a dielectric layer), a lateral interconnect structure 206, and a bottom layer Ball Grid Array (BGA) solder balls 207 . The lower bare chip 203 is formed on the lower substrate 205, and the lower bare chip 203 and the lower substrate 205 are bonded by conductive adhesive or patch glue, or by wire bonding or flip-chip bonding; the lower plastic package 201 surrounds the lower bare chip 203 surrounding, used to protect the lower die 203, and support the lateral interconnection structure 206; the bottom ball grid array solder balls 207 are formed under the lower substrate 205, and are used to realize the electrical interconnection between the lower package body 200 and the PCB substrate .

There is at least one lower-layer die 203 , and when there are multiple lower-layer die 203 , they are arranged on the lower-layer substrate 205 in a manner of stacking, tiling, embedding or embedding. The lower bare chip 203 is combined with the lower substrate 205 through conductive adhesive or chip adhesive 202 , and may also be combined by wire bonding or flip-chip welding. In Fig. 9, the lower bare chip 203 adopts bumps 210 such as controllable collapse chip connection bumps (Controlled Collapse ChipConnection, C4) or copper pillar bumps, and realizes electrical interconnection with the interconnection lines 211 and the lower layer via holes 212 in the lower layer substrate 205. even. The underlying die 203 can also be replaced with discrete devices. The via hole 112 on the upper layer is also called a thermal via when used for heat dissipation, and the electrical property of the thermal via is usually grounded. The lower plastic package 201 surrounds the lower die 203 to protect the lower die 203 and support the vertical interconnect structure 206 .

The underfill 209 is filled between the bumps 210 for protecting the bumps 210 . Alternatively, a molding underfill (MUF) process may also be used to replace the underfill and molding processes, so as to eliminate the underfill 209 .

A plurality of interlayer solder balls 107, a redistribution layer 208 and a lateral interconnection structure 206 form an interconnection channel, the interconnection channel is connected to the upper substrate 105 of the upper package 100, and connected to the lower substrate 205 of the lower package 200, The electrical interconnection between the upper package 100 and the lower package 200 is completed. Finally, the laterally interconnected PoP package structure provided by the present invention realizes electrical interconnection between the bottom solder balls 207 of the lower package body 200 and the PCB substrate.

In FIG. 9, the lateral interconnection structure 206 can adopt metal processes such as electroless plating and electroplating copper in turn, and the metal material in the lateral interconnection structure 206 is coated with materials such as electroless gold tweezers or palladium gold tweezers to prevent oxidation of the metal materials. . The top view of the lateral interconnection structure 206 can be various structures such as semicircle, multi-semicircle or rectangle, that is, slice along the center of the outermost circle or rectangle of the packaging unit, or eccentrically, as shown in FIG. 10 . The purpose of off-center slicing is to enhance the bonding force between the metal/resin in the lateral interconnection structure 206 and the underlying molding compound 201 . FIG. 10 only shows the relative position information of the lateral interconnection structure 206, where the dotted line represents the schematic diagram of the original shape of the vertical interconnection structure before slicing, and the actual manufacturing is not limited to the figure shown in FIG. 10 .

When the top redistribution layer 208 of the lower plastic package 201 of the lower package 200 , the lateral interconnection structure 206 and the interconnection line/layer 211 (ground) in the lower substrate 205 are connected, an electromagnetic shielding effect can be formed. The redistribution layer 208 is not only a part of the shielding structure, but also an interconnection channel, which can be multi-layered; the lateral interconnection structure 206 is a discrete half-via, multi-half-via structure or cubic structure.

The upper substrate 105 contains a plurality of upper thermal vias 112, and the lower substrate 205 contains a plurality of lower thermal vias 212. The upper thermal vias 112 are sequentially connected to the interlayer solder balls 107 and the single-layer metal or multi-layer metal contained in the redistribution layer 208. , the lateral interconnection structure 206 and the lower layer thermal vias 212 to form a 3D heat dissipation channel of the stacked package structure.

The PoP packaging structure with lateral interconnection provided by the present invention can also be combined with through molded via (TMV) technology, as shown in Figure 11 and Figure 12, except that the lateral interconnection structure 206 is used in the lower package body 200 In addition to increasing the number of channels between the upper package and the lower package of the PoP package structure, the number of interconnection channels can also be increased by reducing the TMV size/pitch. In the through-molding via hole 215, the metal copper is sequentially used in the manner of electroless plating, electroplated copper full hole or electroplated copper ring. When the electroplated copper ring is used, the plug hole technology is used, as shown in FIG. 11, to play a supporting role. In the role of the distribution layer (RDL) 208 , the plugging technique employs soldering or resin filling in the TM via 215 . The lateral interconnection structure 206 is obtained by slicing along the outermost circular or rectangular center, or eccentrically, of the packaging unit. The purpose of off-center slicing is to enhance the bonding force between the metal/resin in the lateral interconnection structure 206 and the underlying molding compound 201 . Most of the resin in the lateral interconnection structure 206 in FIG. 11 covers the metal copper ring to prevent the metal copper from epoxidation. The metal in the lateral interconnection structure 206 in FIG. 12 is coated with electroless gold tweezers or palladium gold tweezers to prevent metal oxidation.

It should be noted that since the process steps of the lateral interconnection structure 206 and the TMV hole 215 are synchronized, solder cannot be used for plugging the lateral interconnection structure 206 due to the characteristic that solder tends to form balls in the reflow process. In FIG. 11 and FIG. 12 , 213 represents surface mount components, such as resistors, capacitors, and inductors. 214 represents solder, which is used for electrical interconnection between components and the lower substrate 205 .

As shown in FIG. 11 and FIG. 12 , in addition to including the lower die 203, the lower substrate 205, the lower plastic package 201, and the redistribution layer (RDL) 208 on the top of the plastic package in the lower package body 200 (the redistribution layer 208 includes a metal layer and a dielectric layer ), lateral interconnect structure 206, and underlying ball grid array (BGA) solder balls 207, and also includes a plurality of through molded vias (TMVs) 215 formed in some or all of the Below the interlayer solder balls 107, and through the redistribution layer 208 and the lower plastic package 201. In practical applications, one TMV 215 does not need to be arranged under each interlayer solder ball 107, and the number of interlayer solder balls 107 can be greater than the number of TMV 215.

The through-molding vias 215 are sequentially filled with electroless plating, electroplated copper, or solder balls, so that the interlayer solder balls 107, the redistribution layer 208 and the through-molding vias 215 form an interconnection channel to realize the upper package. The electrical interconnection between the body 100 and the lower package body 200 .

In the through-molding via hole 215, the metal copper is sequentially used in the manner of electroless plating, electroplated copper full hole or electroplated copper ring. When the electroplated copper ring is used, the plug hole technology is used to support the redistribution layer (RDL) 208. The plug hole technology uses solder or resin filling in the through-molded via hole 215 .

Based on the above-mentioned laterally interconnected package-on-package structure provided by the present invention, the method for preparing the laterally interconnected package-on-package structure will be described in detail below.

As shown in FIG. 13 , FIG. 13 is a flowchart of a method for preparing a laterally interconnected stacked package structure provided by the present invention. The stacked package structure includes an upper package and a lower package. The method includes the following steps:

Step A: making an upper package with a plurality of interlayer solder balls at the bottom;

Step B: making a lower package with a redistribution layer and a lateral interconnection structure, wherein the redistribution layer is formed on the top of the lower plastic package of the lower package, and the lateral interconnection structure is formed on the lower plastic package of the lower package around;

Step C: Align and solder the upper package body and the lower package body, so that multiple interlayer solder balls, redistribution layers and lateral interconnection structures form interconnection channels, and then form a stacked package structure of lateral interconnection.

Wherein, the manufacture of the upper package body having a plurality of interlayer solder balls at the bottom as described in step A specifically includes the following steps:

Step 1: Manufacture the upper substrate by lamination process or stacking process, and then slice the upper substrate to form long substrates for subsequent packaging processes, each long substrate contains several packaging units;

Step 2: Use the eutectic bonding method, welding bonding method, conductive adhesive bonding method or glass bonding method to combine the upper bare chip and the long substrate through conductive adhesive or patch adhesive;

Step 3: Electrically interconnect the upper die and the strip substrate by ultrasonic bonding, thermocompression bonding or thermosonic bonding;

Step 4: Form an upper plastic seal around the upper die using transfer molding technology, injection molding technology or pre-molding technology to protect the upper die;

Step 5: Plant balls on the bottom of the strip substrate to form multiple interlayer solder balls; among them, the material used for multiple interlayer solder balls is solder, and a full disk arrangement is adopted between the upper package and the lower package or outer ring arrangement;

Step 6: Cutting the long substrate into several upper package units to obtain an upper package with multiple interlayer solder balls at the bottom.

Wherein, the manufacture of the lower package body having a redistribution layer and a lateral interconnection structure as described in step B specifically includes the following steps:

Step 11: Manufacture the lower substrate by lamination process or lamination process, and then slice the lower substrate to form long substrates for subsequent packaging process, each long substrate contains several packaging units.

Step 12: Directly bond the lower die face-down die soldering area to the long substrate soldering area; and through the underfill process, inject epoxy resin material between the lower die and the long substrate to protect the soldering In order to reduce the stress and strain caused by the difference in coefficient of thermal expansion between the bare chip and the strip substrate, the epoxy resin is cured by a curing oven.

Step 13: Using transfer molding technology, injection molding technology or pre-molding technology to form a lower plastic seal around the lower die to protect the lower die;

In addition, a molding underfill process can be used to replace the underfill described in step 12 and the plastic encapsulation process in step 13.

Step 14: Use laser etching to ablate the lower layer of plastic packaging to form vias for forming lateral interconnection structures; wherein, when the formed vias are quadrilateral vias, use continuous laser etching to ablate the lower layer of plastic packaging, that is, quadrilateral The four sides of the via are not ideal straight lines.

Step 15: Apply electroless plating and copper electroplating to the lower plastic package with vias in sequence, and plate the vias with copper to form metallized vias with a lateral interconnection structure, and at the same time form a redistribution layer on the lower plastic package;

Wherein, if the redistribution layer adopts a multi-layer structure, the formation of the redistribution layer on the lower plastic package includes: sequentially adopting electroless plating and copper electroplating processes to form the first metal layer of the redistribution layer on the lower plastic package; Then exposure and etching are used to complete the patterning of the first metal layer of the redistribution layer, followed by lamination of dielectric layers, laser drilling blind holes to form interlayer blind holes in the redistribution layer, and then chemical plating and electroplating metal copper Process to form the second metal layer in the hole and the redistribution layer; then sequentially adopt exposure and etching to complete the patterning of the second metal layer of the redistribution layer, and then sequentially use a laminated dielectric layer, and laser drill blind holes to form a redistribution layer Blind holes between layers, and then use electroless plating and electroplating metal copper processes to form the third metal layer in the hole and the redistribution layer; and so on, repeat the above process to form the second or third metal layer, A multi-layer metal layer that forms a redistribution layer; after forming the outermost metal layer, a patterned pad is formed to interconnect with the upper package.

Step 16: cutting each strip of substrate into several lower packaging substrate units with redistribution layers and lateral interconnection structures;

Step 17: Coating the metal copper with electroless gold tweezers or palladium gold tweezers on the outside of the metal copper in the lateral interconnection structure to prevent oxidation of the metal copper;

Step 18: Plant balls on the bottom of the package substrate unit by means of a full disk arrangement or an outer ring arrangement, and clean the residual solder on the bottom pad to obtain a lower package with a redistribution layer and a lateral interconnection structure.

Wherein, the manufacture of the lower package body having a redistribution layer and a lateral interconnection structure as described in step B specifically includes the following steps:

Step 21: Manufacture the lower substrate by lamination process or lamination process, and then slice the lower substrate to form long substrates for subsequent packaging process, each long substrate contains several packaging units.

Step 22: Mount discrete devices on the surface of the strip substrate.

Step 23: Directly bond the lower die face-down die soldering area to the long substrate soldering area; and through the underfill process, inject epoxy resin material between the lower die and the long substrate to protect the soldering In order to reduce the stress and strain caused by the difference in coefficient of thermal expansion between the bare chip and the strip substrate, the epoxy resin is cured by a curing oven.

Step 24: Using transfer molding technology, injection molding technology or pre-molding technology to form a lower plastic seal around the lower die to protect the upper and lower die;

In addition, a molding underfill process can also be used to replace the underfill described in step 23 and the plastic encapsulation process in step 24.

Step 25: Use laser etching to ablate the lower plastic package to form vias for forming lateral interconnection structures and through-molding vias; where the formed vias are quadrilateral vias, use continuous laser etching process Ablation of the lower layer of plastic packaging means that the four sides of the quadrilateral vias are not ideal straight lines.

Step 26: Use electroless plating and copper electroplating to form a copper ring in sequence for the lower layer plastic package with via holes to form a lateral interconnection structure and through-molded metallized via holes; The through-molded metallized vias are filled to support the redistribution layer and prevent the copper metal oxidation of the lateral interconnection structure; at the same time, a redistribution layer is formed on the lower plastic package;

Among them, if the redistribution layer adopts a multi-layer structure, the redistribution layer is formed on the lower plastic package, including: sequentially adopting electroless plating and electroplating copper to form the first metal layer of the redistribution layer on the lower plastic package; Exposure and etching complete the patterning of the first metal layer of the redistribution layer, followed by lamination of dielectric layers, laser drilling of blind holes to form interlayer blind holes in the redistribution layer, and then sequential use of electroless plating and electroplating of metal copper to form holes The second metal layer of the internal and redistribution layer; followed by exposure and etching to complete the patterning of the second metal layer of the redistribution layer, followed by lamination of the dielectric layer, laser drilling blind holes to form the interlayer of the redistribution layer Blind holes, and then use electroless plating and electroplating metal copper processes to form the third metal layer in the hole and the redistribution layer; and so on, repeat the above process to form the second or third metal layer to form a redistribution The multi-layer metal layer of the first layer; after forming the outermost metal layer, a patterned pad is formed to interconnect with the upper package;

Step 27: Plant balls on the bottom of the long substrate by means of full disk arrangement or outer ring arrangement, and clean the residual solder on the bottom pad;

Step 28: Cutting each strip of substrate into several lower package units with redistribution layer and lateral interconnection structure to obtain lower package body with redistribution layer and lateral interconnection structure.

Wherein, the manufacture of the lower package body having a redistribution layer and a lateral interconnection structure as described in step B specifically includes the following steps:

Step 31: Manufacture the lower substrate by lamination process or lamination process, and then slice the lower substrate to form long substrates for subsequent packaging process, each long substrate contains several packaging units.

Step 32: Directly bond the lower die face-down die soldering area to the long substrate soldering area; and through the underfill process, inject epoxy resin material between the lower die and the long substrate to protect the soldering In order to reduce the stress and strain caused by the difference in coefficient of thermal expansion between the bare chip and the strip substrate, the epoxy resin is cured by a curing oven.

Step 33: Use eutectic bonding method, soldering bonding method, conductive adhesive bonding method or glass glue bonding method to attach the lower bare die on the long substrate, and use ultrasonic bonding and thermocompression bonding Or thermosonic bonding electrically interconnects the underlying die to the elongated substrate.

Step 34: Form a lower plastic seal around the lower die by using transfer molding technology, injection molding technology or pre-molding technology to protect the upper and lower die.

Step 35: using laser etching to ablate the lower plastic package to form via holes for forming lateral interconnection structures and through-molding vias;

Wherein, when the formed via hole is a quadrilateral via hole, the lower plastic package is ablated by a continuous laser etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

Step 36: Apply electroless plating and copper electroplating to the lower plastic package with vias in sequence, and plate the vias with copper to form lateral interconnection structures and copper-plated through-molded vias, and form them on the lower plastic package at the same time redistribution layer;

Wherein, if the redistribution layer adopts a multi-layer structure, the redistribution layer is formed on the lower plastic package, including: sequentially adopting electroless plating and electroplating copper processes to form the first metal layer of the redistribution layer on the lower plastic package; and then sequentially Use exposure and etching to complete the patterning of the first metal layer of the redistribution layer, followed by lamination of dielectric layers, laser drilling blind holes to form interlayer blind holes in the redistribution layer, and then sequentially adopt electroless plating and electroplating metal copper processes to form The hole and the second metal layer of the redistribution layer; then sequentially use exposure and etching to complete the patterning of the second metal layer of the redistribution layer, and then use the laminated dielectric layer sequentially, and laser drill blind holes to form the layer of the redistribution layer Blind holes between holes, and then use electroless plating and electroplating metal copper processes to form the third metal layer in the hole and the redistribution layer; and so on, repeat the above process to form the second or third metal layer to form the redistribution layer. The multi-layer metal layer of the distribution layer; after the outermost metal layer is formed, a patterned pad is formed to interconnect with the upper package.

Step 37: cutting each strip of substrate into several lower packaging substrate units with redistribution layers and lateral interconnection structures;

Step 38: Coating the metal copper with electroless gold tweezers or palladium gold tweezers on the outside of the metal copper in the lateral interconnection structure to prevent oxidation of the metal copper;

Step 39: Plant balls on the bottom of the package substrate unit by means of a full disk arrangement or an outer ring arrangement, and clean the residual solder on the bottom pad to obtain a lower package with a redistribution layer and a lateral interconnection structure.

Example 1

In this embodiment, both the upper-layer package and the lower-layer package contain only the upper-layer die, and do not contain discrete devices, and there is no TMV in the lower-layer molding of the lower-layer package.

1.1. As shown in Figure 14, the preparation process of the upper package is as follows:

Step 1: Manufacture of the upper substrate; the upper substrate is manufactured using conventional substrate/PCB processes such as lamination or bulid-up, and then the upper substrate is sliced into strips for subsequent packaging processes. The strip substrate contains several packaging units.

Step 2: SMT: fix the upper bare chip on the upper substrate, using a SMT method such as eutectic bonding method, welding bonding method, conductive adhesive bonding method or glass glue bonding method.

Step 3: wire bonding; electrical interconnection of the upper die and the upper substrate; wire bonding technology is a conventional method for circuit interconnection between the die and the package structure, through burning balls -> pressure welding -> wire drawing -> Broken wire -> Welding -> Broken wire -> Complete several key process steps. The main wire bonding techniques are; kind.

Step 4: Plastic encapsulation; form an upper plastic encapsulation around the upper die to protect the upper die; there are various molding techniques for plastic encapsulation, including Transfer Molding, Inject Molding, Pre- Molding technology (Premolding), etc., but the most important molding technology is transfer molding technology.

Step 5: Ball planting: Plant balls at the bottom of the upper substrate to form multiple interlayer solder balls; interlayer solder balls can be arranged in a full disk or outer circle as required; residual solder on the bottom pad should be cleaned -> Several key process steps such as printing flux (or solder paste) on the bottom pad -> planting balls with a ball planter -> reflow soldering -> inspection.

Step 6: Slicing: Cut each strip of substrate into several upper packaging units along the outer frame of the upper packaging unit.

1.2. As shown in Figure 15, the preparation process of the lower package is as follows:

Step 7: Manufacture of the lower substrate; use conventional substrate/PCB processes such as lamination or stacking (bulid-up) to manufacture the lower substrate, and then slice the lower substrate to form strip substrates for subsequent packaging processes, each strip The strip substrate contains several package units.

Step 8: flip-chip soldering: place the lower die face down on the lower substrate, place the lower die face down, and directly bond the solder pads of the lower die die to the solder pads of the substrate. Flip-chip welding mainly includes several key steps of picking up bare chips -> printing solder paste or conductive adhesive -> flip chip welding (chip placement) -> reflow soldering or thermal curing (or UV curing).

Step 9: Underfill: After the lower die is flip-chip soldered, epoxy resin material is injected between the lower die and the substrate to protect the solder joints, and the epoxy resin is cured by a curing oven to form the lower die and substrate. The solder balls between the chips provide structural support.

Step 10: Plastic encapsulation: form the lower layer plastic seal around the lower die to protect the upper and lower die; there are many molding techniques for plastic encapsulation, including transfer molding technology (Transfer Molding), injection molding technology (Inject Molding), pre- Molding technology (Premolding), etc., but the most important molding technology is transfer molding technology.

A molded underfill (MUF) process may also be used to replace the underfill and plastic encapsulation processes, thereby eliminating the underfill 209 and the underfill process in step 9 .

Step 11: Laser etching holes to form via holes for forming lateral interconnection structures: after the molding process of the lower layer package, laser ablation of the molding compound is used at the positions where the lateral interconnection structures 206 are required. When the lateral interconnection structure is a quadrilateral via hole, it can be formed by a continuous etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

Step 12: Form lateral interconnection metallization and form redistribution layer (RDL): firstly use electroless plating, electroplating Cu and other metals to form a lateral interconnection structure metal layer (full plating), and at the same time form the first metal layer of RDL (M1 layer)->exposure and etching complete the M1 layer patterning of RDL->laminate dielectric layer->laser drilling blind holes to form blind holes between RDL layers->electroless plating, electroplating Cu and other metals to form holes and M2 of RDL Metal layer->exposure and etching complete the patterning of the M2 metal layer of the RDL (when M2 is the outermost metal layer, a patterned pad is formed to interconnect with the upper package 107), and the lower layer plastic package 201 is formed on the top multi-layer RDL208 Repeat the above process to get final product.

Step 13: Slicing: Cut each strip of substrate into several lower packaging substrate units along the outer frame of the lower packaging body unit, and form the lower packaging lateral interconnection structure 206 at the same time. The position of the outer frame of the lower package coincides with or deviates from the center of the lateral interconnection structure. The purpose of off-center slicing is to enhance the bonding force between the metal in the lateral interconnection structure 206 and the underlying molding compound 201 .

Step 14: Anti-oxidation protection: the metal in the lateral interconnection structure 206 is coated with electroless gold tweezers or palladium gold tweezers to prevent metal oxidation.

Step 15: Ball planting: Plant balls at the bottom of the lower substrate, which can be arranged in a full disk or outer ring according to needs; the residual solder on the bottom pad should be cleaned -> print flux (or solder paste) on the bottom pad -> Several key process steps such as ball planting with ball planter -> reflow soldering -> inspection.

1.3. Align and reflow solder the pads of the redistribution layer in the upper package and the lower package to form a stacked package structure with lateral interconnection.

Example 2

In this embodiment, the upper package contains only the upper die and does not contain discrete devices; the lower package contains the upper die and discrete devices, and the lower package of the lower package also contains TMV.

2.1. As shown in FIG. 16 , the preparation process of the upper package is the same as that of the upper package in FIG. 13 , and will not be repeated here.

2.2. As shown in Figure 16, the preparation process of the lower package is as follows:

Step 16: Manufacture of the lower substrate: the lower substrate is manufactured by conventional substrate/PCB processes such as lamination or build-up (bulid-up), and then the lower substrate is sliced to form strips of substrates for subsequent packaging processes. Each strip The substrate contains several packaged units.

Step 17: Surface Mount Discrete Devices: Solder the discrete devices on the lower substrate using a surface mount (SMT) process. The surface mount process mainly consists of silk screen printing (or dispensing)->mounting (curing)->reflow soldering->cleaning->testing and other parts.

Step 18: flip-chip soldering: place the lower die face down on the lower substrate, place the lower die face down, and directly bond the solder pads of the lower die to the solder pads of the substrate. Flip-chip welding mainly includes several key steps of picking up bare chips -> printing solder paste or conductive adhesive -> flip chip welding (chip placement) -> reflow soldering or thermal curing (or UV curing).

Step 19: Underfill: After the lower die is flip-chip soldered, the underfill process is used, that is, epoxy resin material is injected between the lower die and the lower substrate to protect the solder joints, and the epoxy resin is cured by a curing oven to Solder balls between the underlying die and the underlying substrate provide structural support.

Step 20: Plastic encapsulation; form a lower plastic encapsulation around the underlying bare die or discrete devices to protect the underlying die or discrete devices; there are various molding techniques for plastic encapsulation, including Transfer Molding and injection molding (Inject Molding), premolding technology (Premolding), etc., but the most important molding technology is transfer molding technology.

It is also possible to use a molded underfill (MUF) process instead of the underfill and plastic encapsulation processes, thereby eliminating the underfill 209 and omitting the underfill process in step 20 .

Step 21: Laser etching holes to form vias for forming lateral interconnection structures and TMVs: After the plastic encapsulation process, the lower layer package uses laser ablation molding compound where lateral interconnection structures 206 and TMV 215 are required . When the lateral interconnection structure is a quadrilateral via hole, it can be formed by a continuous etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

Step 22: Form lateral interconnection metallization, plug holes and form redistribution layer (RDL): firstly use electroless plating, electroplating Cu and other metals to form lateral interconnection structure 206 metal layer (copper ring), TMV215 metal layer, and at the same time Form the first metal layer (M1 layer) of RDL -> solder ball/resin plug hole -> exposure and etching to complete the patterning of M1 layer of RDL -> lamination dielectric layer -> laser drilling blind holes to form blind holes between RDL layers -> Electroless plating, electroplating Cu and other metals form the M2 metal layer in the hole and the RDL -> Exposure and etching complete the patterning of the M2 metal layer of the RDL (when M2 is the outermost metal layer, a patterned pad is formed, and upper package body 107 interconnect). The lower layer plastic seal 201 and the top multi-layer RDL208 are formed by repeating the above process.

It should be noted that: due to the synchronization of the process steps of the lateral interconnection structure 206 and TMV 215, due to the easy ball formation of solder in the reflow process, solder cannot be used in the plug holes of the lateral interconnection structure, while TMV uses solder balls/resin plug holes can be.

Step 23: Ball planting: Plant balls at the bottom of the lower substrate, which can be arranged in a full disk or outer ring according to needs; the residual solder on the bottom pad should be cleaned -> print flux (or solder paste) on the bottom pad -> Several key process steps such as ball planting with ball planter -> reflow soldering -> inspection.

Step 24: Slicing: Cut each strip of substrate into several lower packaging units along the outer frame of the lower packaging unit, and form the lower packaging lateral interconnection structure 206 at the same time. The position of the outer frame of the lower package coincides with or deviates from the center of the lateral interconnection structure. The purpose of off-center slicing is to enhance the bonding force between the metal in the lateral interconnection structure 206 and the underlying molding compound 201 . After slicing, the resin in the lateral interconnection structure 206 is mostly covered with metal, which can prevent the metal in the lateral interconnection structure 206 from being oxidized.

It should be noted that, in the above 1.2, the slicing is performed first, and then the ball is planted. Then the solder balls will be coated with nickel-palladium-gold or gold-tweezers. However, when using resin to partially protect the lateral interconnection structure, it is sufficient to first plant the ball and then slice it. In fact, it is more efficient to plant the ball first and then slice it.

2.3. Align the pads of the redistribution layer in the upper package body and the lower package body for reflow soldering to form a stacked package structure with lateral interconnection.

Example 3

In this embodiment, the upper package only contains the upper die and does not contain discrete devices; the lower package only contains the upper die and does not contain discrete devices, and the lower packaging of the lower package also contains TMV.

3.1. As shown in FIG. 17 , the preparation process of the upper package is the same as that of the upper package in FIG. 13 , and will not be repeated here.

3.2. As shown in Figure 17, the preparation process of the lower package is as follows:

Step 25: Manufacture of the lower substrate; the lower substrate is fabricated by conventional substrate/PCB processes such as lamination or bulid-up, and then the lower substrate is sliced into strips for subsequent packaging processes. Each strip The substrate contains several packaged units.

Step 26: Flip Chip Soldering and Underfill:

Flip-chip welding: place the lower die face down on the lower substrate, place the lower die face down, and directly bond the lower die pads to the substrate pads. Flip-chip welding mainly includes several key steps of picking up bare chips -> printing solder paste or conductive adhesive -> flip chip welding (chip placement) -> reflow soldering or thermal curing (or UV curing).

Underfill: After the lower die is flip-chip soldered, the underfill process is used, that is, epoxy resin material is injected between the lower die and the lower substrate to protect the solder joints, and the epoxy resin is cured by a curing oven to form the lower die and the lower substrate. Solder balls between provide structural support.

Step 27: SMT and wire bonding; fix the lower-layer die on the lower-layer substrate by using a bonding method such as eutectic bonding method, welding bonding method, conductive adhesive bonding method or glass glue bonding method.

Electrically interconnect the underlying bare chip with the underlying substrate; wire bonding technology is a conventional method for circuit interconnection between the bare chip and the package structure. Line -> complete several key process steps. The main wire bonding techniques are; Ultrasonic Bonding (U/S Bonding), Thermocompression Bonding (Thermocompression Bonding, T/C Bonding), and Thermosonic Bonding (Thermosonic Bonding, T/S Bonding).

It should be noted that in step 26, flip-chip soldering the lower-layer die on the lower-layer substrate and in step 27, fixing the lower-layer die on the lower-layer substrate by patching is because there are two lower-layer dies. After completing the FC+bottom filling of a lower die, do the placement+WB of another lower die.

Step 28: Plastic encapsulation; form a lower plastic encapsulation around the lower die to protect the lower die; there are various molding techniques for plastic encapsulation, including Transfer Molding, Inject Molding, Pre- Molding technology (Premolding), etc., but the most important molding technology is transfer molding technology.

It is also possible to use a molded underfill (MUF) process to replace the underfill and molding processes, so as to eliminate the underfill 209 and the underfill process in step 26 .

Step 29: Laser etching holes to form via holes for forming lateral interconnection structures and TMVs: After the plastic encapsulation process, the lower layer package uses laser ablation molding compound where lateral interconnection structures 206 and TMV 215 are required . When the lateral interconnection structure is a quadrilateral via hole, it can be formed by a continuous etching process, that is, the four sides of the quadrilateral via hole are not ideal straight lines.

Step 30: Forming lateral interconnection metallization and forming redistribution layer (RDL): first, metal layer 206 of lateral interconnection structure, TMV215 metal layer (full plating) is formed by electroless plating, electroplating Cu and other metals, and the RDL is formed at the same time The first metal layer (M1 layer)->exposure and etching complete the M1 layer patterning of RDL->laminate dielectric layer->laser drilling blind holes to form blind holes between RDL layers->electroless plating, electroplating Cu and other metals to form holes The M2 metal layer of the inner and RDL -> exposure and etching complete the patterning of the M2 metal layer of the RDL (when M2 is the outermost metal layer, a patterned pad is formed and interconnected with the upper package 107. The top of the lower plastic package 201 The formation of multi-layer RDL208 can be done by repeating the above process.

Step 31: Slicing: cutting each strip substrate into several lower packaging substrate units along the outer frame of the lower packaging body unit, and forming the lower packaging lateral interconnection structure 206 at the same time. The position of the outer frame of the lower package coincides with or deviates from the center of the lateral interconnection structure. The purpose of off-center slicing is to enhance the bonding force between the metal in the lateral interconnection structure 206 and the underlying molding compound 201 .

Step 32: Anti-oxidation protection: the metal in the lateral interconnection structure 206 is coated with electroless gold tweezers or palladium gold tweezers to prevent metal oxidation.

Step: 33: Ball planting: Plant balls at the bottom of the lower substrate, which can be arranged in full disk or outer ring according to needs; the residual solder on the bottom pad should be cleaned -> print flux (or solder paste) on the bottom pad )->Using the ball planter to plant the ball->reflow soldering->testing and other key process steps.

3.3. Align and reflow solder the bonding pads of the redistribution layer in the upper package body and the lower package body to form a stacked package structure with lateral interconnection.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (28)

1. a preparation method for the stack package structure of side direction interconnection, this stack package structure comprises upper strata packaging body and lower floor's packaging body, and it is characterized in that, the method comprises:

Make the upper strata packaging body that bottom has multiple interlayer soldered ball;

Make lower floor's packaging body with redistributing layer and side direction interconnection structure, wherein, redistributing layer is formed at the top of lower floor's plastic packaging of this lower floor's packaging body, and side direction interconnection structure is formed at the surrounding of lower floor's plastic packaging of this lower floor's packaging body;

Upper strata packaging body and lower floor packaging body are aimed at and welds, make multiple interlayer soldered ball, redistributing layer and side direction interconnection structure form interconnecting channel, and then form the stack package structure of side direction interconnection.

2. preparation method according to claim 1, is characterized in that, described making bottom has the upper strata packaging body of multiple interlayer soldered ball, comprising:

Step 1: adopt laminating technology or laminated process to manufacture top substrate layer, then top substrate layer section is formed rectangular substrate and be used for subsequent encapsulating process, the rectangular substrate of every bar contains several encapsulation unit;

Step 2: adopt that eutectic pastes method, method is pasted in welding, method pasted by conducting resinl or glass cement is pasted method and is combined by conducting resinl or Heraeus with rectangular substrate by upper strata nude film;

Step 3: adopt supersonic bonding, thermocompression bonding or thermosonication bonding that upper strata nude film and rectangular substrate are carried out electric interconnection;

Step 4: adopt transfer formation technology, injection molding technology or preform technique to form upper strata plastic packaging around the nude film of upper strata, to protect upper strata nude film;

Step 5: plant ball at rectangular substrate bottom, forms multiple interlayer soldered ball;

Step 6: rectangular substrate is cut into some upper stratas encapsulation unit, obtains the upper strata packaging body that bottom has multiple interlayer soldered ball.

3. preparation method according to claim 2, is characterized in that, the material that multiple interlayer soldered ball described in step 5 adopts is scolding tin, and between upper strata packaging body and lower floor's packaging body, adopts dishful to arrange or arrange in outer ring.

4. preparation method according to claim 1, is characterized in that, described making has lower floor's packaging body of redistributing layer and side direction interconnection structure, comprising:

Step 11: adopt laminating technology or laminated process to manufacture underlying substrate, then underlying substrate section is formed rectangular substrate and be used for subsequent encapsulating process, the rectangular substrate of every bar contains several encapsulation unit;

Step 12: face down lower floor's nude film nude film welding zone and rectangular substrate welding zone Direct Bonding; And through underfill process, epoxide resin material is injected into protect pad between lower floor's nude film and rectangular substrate, by curing oven cured epoxy resin, for reducing the stress and strain that nude film causes because thermal coefficient of expansion is different from rectangular substrate;

Step 13: adopt transfer formation technology, injection molding technology or preform technique to form lower floor's plastic packaging around lower floor's nude film, to protect lower floor's nude film;

Step 14: adopt laser pit ablation lower floor plastic packaging, form the via hole for the formation of side direction interconnection structure;

Step 15: adopt chemical plating, copper plating process successively to lower floor's plastic packaging with via hole, forms the metallization via hole of side direction interconnection structure, forms redistributing layer simultaneously on lower floor's plastic packaging by full for via hole plating copper;

Step 16: rectangular for every bar substrate is cut into some lower layer package substrate unit with redistributing layer and side direction interconnection structure;

Step 17: the outside of metallic copper adopts chemical plating tweezer gold or tweezer porpezite clad copper in side direction interconnection structure, prevents metallic copper;

Step 18: adopt dishful arrangement or outer ring arrangement mode to plant ball in base plate for packaging unit bottom, and clean the residue solder in bottom land, obtain lower floor's packaging body with redistributing layer and side direction interconnection structure.

5. preparation method according to claim 4, is characterized in that, adopts the underfill described in molded underfill technique step of replacing 12 and the plastic package process described in step 13.

6. preparation method according to claim 4, is characterized in that, when the via hole formed described in step 14 is quadrangle via hole, adopt continuous laser pit technique ablation lower floor plastic packaging, namely quadrangle via hole four limit is not desirable straight line.

7. preparation method according to claim 4, is characterized in that, described redistributing layer adopts sandwich construction, forms redistributing layer, comprising described in step 15 on lower floor's plastic packaging:

Adopt chemical plating, copper plating process on lower floor's plastic packaging, form the first layer metal layer of redistributing layer successively; Then adopt exposure successively, etch the first layer metal layer pattern of redistributing layer, then laminating media layer is adopted successively, laser drilling blind hole forms the interlayer blind hole of redistributing layer, then adopts chemical plating, plated metal process for copper to be formed in hole and the second layer metal layer of redistributing layer successively; Then adopt exposure successively, etch the second layer metal layer pattern of redistributing layer, then laminating media layer is adopted successively, laser drilling blind hole forms the interlayer blind hole of redistributing layer, then adopts chemical plating, plated metal process for copper to be formed in hole and the third layer metal level of redistributing layer successively; By that analogy, repeat above formation second layer metal layer or third layer metal layer process, form the more metal layers of redistributing layer; After formation outermost metal layer, form patterned pad, interconnect with upper strata packaging body.

8. preparation method according to claim 1, is characterized in that, described making has lower floor's packaging body of redistributing layer and side direction interconnection structure, comprising:

Step 21: adopt laminating technology or laminated process to manufacture underlying substrate, then underlying substrate section is formed rectangular substrate and be used for subsequent encapsulating process, the rectangular substrate of every bar contains several encapsulation unit;

Step 22: at rectangular substrate surface attachment discrete device;

Step 23: face down lower floor's nude film nude film welding zone and rectangular substrate welding zone Direct Bonding; And through underfill process, epoxide resin material is injected into protect pad between lower floor's nude film and rectangular substrate, be the stress and strain that minimizing nude film causes because thermal coefficient of expansion is different from rectangular substrate by curing oven cured epoxy resin;

Step 24: adopt transfer formation technology, injection molding technology or preform technique to form lower floor's plastic packaging around lower floor's nude film, to protect levels nude film;

Step 25: adopt laser pit ablation lower floor plastic packaging, formed for the formation of side direction interconnection structure and the via hole penetrating molding via hole;

Step 26: lower floor's plastic packaging with via hole is adopted to chemical plating successively, electroplates into copper ring, forms side direction interconnection structure and the metallization via hole penetrating molding; Adopt filling holes with resin technique to be filled up with the metallization via hole penetrating molding by test interconnection structure, play the effect supporting redistributing layer and prevent the burning of side direction interconnection structure copper; On lower floor's plastic packaging, form redistributing layer simultaneously;

Step 27: adopt dishful arrangement or outer ring arrangement mode to plant ball at rectangular substrate bottom, and clean the residue solder in bottom land;

Step 28: rectangular for every bar substrate is cut into some lower floor's encapsulation units with redistributing layer and side direction interconnection structure, obtains lower floor's packaging body with redistributing layer and side direction interconnection structure.

9. preparation method according to claim 8, is characterized in that, adopts the underfill described in molded underfill technique step of replacing 23 and the plastic package process described in step 24.

10. preparation method according to claim 8, is characterized in that, when the via hole formed described in step 25 is quadrangle via hole, adopt continuous laser pit technique ablation lower floor plastic packaging, namely quadrangle via hole four limit is not desirable straight line.

11. preparation methods according to claim 8, is characterized in that, described redistributing layer adopts sandwich construction, forms redistributing layer, comprising described in step 26 on lower floor's plastic packaging:

Adopt chemical plating, copper plating process on lower floor's plastic packaging, form the first layer metal layer of redistributing layer successively; Then adopt exposure successively, etch the first layer metal layer pattern of redistributing layer, then laminating media layer is adopted successively, laser drilling blind hole forms the interlayer blind hole of redistributing layer, then adopts chemical plating, plated metal process for copper to be formed in hole and the second layer metal layer of redistributing layer successively; Then adopt exposure successively, etch the second layer metal layer pattern of redistributing layer, then laminating media layer is adopted successively, laser drilling blind hole forms the interlayer blind hole of redistributing layer, then adopts chemical plating, plated metal process for copper to be formed in hole and the third layer metal level of redistributing layer successively; By that analogy, repeat above formation second layer metal layer or third layer metal layer process, form the more metal layers of redistributing layer; After formation outermost metal layer, form patterned pad, interconnect with upper strata packaging body.

12. preparation methods according to claim 1, is characterized in that, described making has lower floor's packaging body of redistributing layer and side direction interconnection structure, comprising:

Step 31: adopt laminating technology or laminated process to manufacture underlying substrate, then underlying substrate section is formed rectangular substrate and be used for subsequent encapsulating process, the rectangular substrate of every bar contains several encapsulation unit;

Step 32: face down lower floor's nude film nude film welding zone and rectangular substrate welding zone Direct Bonding; And through underfill process, epoxide resin material is injected into protect pad between lower floor's nude film and rectangular substrate, by curing oven cured epoxy resin, for reducing the stress and strain that nude film causes because thermal coefficient of expansion is different from rectangular substrate;

Step 33: eutectic pastes method, method is pasted in welding, method pasted by conducting resinl or glass cement pastes method by lower floor's nude film paster on rectangular substrate in employing, and adopts supersonic bonding, thermocompression bonding or thermosonication bonding that lower floor's nude film and rectangular substrate are carried out electric interconnection;

Step 34: adopt transfer formation technology, injection molding technology or preform technique to form lower floor's plastic packaging around lower floor's nude film, to protect levels nude film;

Step 35: adopt laser pit ablation lower floor plastic packaging, formed for the formation of side direction interconnection structure and the via hole penetrating molding via hole;

Step 36: chemical plating, copper plating process are adopted successively to lower floor's plastic packaging with via hole, what the full copper of via hole plating is formed side direction interconnection structure and the full copper of plating penetrates molding via hole, forms redistributing layer on lower floor's plastic packaging simultaneously;

Step 37: rectangular for every bar substrate is cut into some lower layer package substrate unit with redistributing layer and side direction interconnection structure;

Step 38: the outside of metallic copper adopts chemical plating tweezer gold or tweezer porpezite clad copper in side direction interconnection structure, prevents metallic copper;

Step 39: adopt dishful arrangement or outer ring arrangement mode to plant ball in base plate for packaging unit bottom, and clean the residue solder in bottom land, obtain lower floor's packaging body with redistributing layer and side direction interconnection structure.

13. preparation methods according to claim 12, is characterized in that, when the via hole formed described in step 34 is quadrangle via hole, adopt continuous laser pit technique ablation lower floor plastic packaging, namely quadrangle via hole four limit is not desirable straight line.

14. preparation methods according to claim 12, is characterized in that, described redistributing layer adopts sandwich construction, forms redistributing layer, comprising described in step 36 on lower floor's plastic packaging:

Adopt chemical plating, copper plating process on lower floor's plastic packaging, form the first layer metal layer of redistributing layer successively; Then adopt exposure successively, etch the first layer metal layer pattern of redistributing layer, then laminating media layer is adopted successively, laser drilling blind hole forms the interlayer blind hole of redistributing layer, then adopts chemical plating, plated metal process for copper to be formed in hole and the second layer metal layer of redistributing layer successively; Then adopt exposure successively, etch the second layer metal layer pattern of redistributing layer, followed by lamination dielectric layer, laser drilling blind hole forms the interlayer blind hole of redistributing layer, then adopts chemical plating, plated metal process for copper to be formed in hole and the third layer metal level of redistributing layer successively; By that analogy, repeat above formation second layer metal layer or third layer metal layer process, form the more metal layers of redistributing layer; After formation outermost metal layer, form patterned pad, interconnect with upper strata packaging body.

15. preparation methods according to claim 1, it is characterized in that, described side direction interconnection structure connects the metal level in described redistributing layer, under connect the underlying substrate of described lower floor packaging body, be circular vias or the quadrangle via hole formed by circular vias platoon, adopt chemical plating in the vias successively, plating is filled with metallic copper, section forms discrete half via hole, mostly via structure or cube structure.

16. preparation methods according to claim 15, is characterized in that, the metal material in described side direction interconnection structure is all coated or most of coated by resin, tweezer gold or tweezer porpezite, to prevent metal material oxidized.

17. preparation methods according to claim 15, it is characterized in that, described redistributing layer is made up of metal level and dielectric layer, metal level is used for realizing electric interconnection, and dielectric layer is used for realizing isolation or zone isolation between interconnection line.

18. preparation methods according to claim 17, is characterized in that, described redistributing layer comprises single-layer metal or multiple layer metal.

19. preparation methods according to claim 1, is characterized in that,

Described upper strata packaging body comprises top substrate layer, upper strata nude film and upper strata plastic packaging, wherein: described upper strata nude film is formed on top substrate layer, upper strata nude film is combined by conducting resinl or Heraeus with top substrate layer, or adopts wire bonding or flip chip bonding mode to combine; Described upper strata plastic packaging is centered around around the nude film of upper strata, for the protection of upper strata nude film;

Described lower floor packaging body comprises underlying substrate, lower floor's nude film, lower floor's plastic packaging, redistributing layer, side direction interconnection structure and bottom ball grid array soldered ball, wherein: described lower floor nude film is formed on underlying substrate, lower floor's nude film is combined by conducting resinl or Heraeus with underlying substrate, or adopts wire bonding or flip chip bonding mode to combine; Described lower floor plastic packaging is centered around around lower floor's nude film, and for the protection of lower floor's nude film, and support-side is to interconnection structure; Described bottom ball grid array soldered ball is formed under underlying substrate, for realizing the electric interconnection between lower floor's packaging body and PCB substrate.

20. preparation methods according to claim 19, it is characterized in that, containing multiple upper stratas thermal hole in described top substrate layer, containing multiple lower floors thermal hole in described underlying substrate, the single-layer metal that this upper strata thermal hole comprises with interlayer soldered ball, redistributing layer successively or multiple layer metal, side direction interconnection structure and lower floor's thermal hole, form the 3D heat dissipation channel of this stack package structure.

21. preparation methods according to claim 19, is characterized in that, during stratum conducting in described redistributing layer and described side direction interconnection structure and described underlying substrate, can form electromagnetic shielding, for the electromagnetic isolation of lower floor's nude film.

22. preparation methods according to claim 19, is characterized in that, described lower floor packaging body also comprises and multiplely penetrates molding via hole, and this penetrates molding via hole and is formed under part or all of described interlayer soldered ball, runs through redistributing layer and lower floor's plastic packaging.

23. preparation methods according to claim 22, it is characterized in that, penetrate in molding via hole adopt chemical plating, the full hole of electro-coppering or plating copper ring successively at this, make interlayer soldered ball, redistributing layer and penetrate molding via hole to form interconnecting channel, realize the electric interconnection between this upper strata packaging body and this lower floor's packaging body.

24. preparation methods according to claim 23, is characterized in that, describedly to penetrate in molding via hole metallic copper and adopt consent technology at this for during plating copper ring, play the effect supporting redistributing layer.

25. preparation methods according to claim 24, is characterized in that, described consent technology adopts carries out scolding tin or potting resin penetrating in molding via hole.

26. preparation methods according to claim 19, it is characterized in that, described upper strata nude film or described lower floor nude film at least one, when for time multiple, described upper strata nude film adopt stacking, tiling, embedded or in the mode of burying be arranged on top substrate layer, described lower floor nude film adopt stacking, tiling, embedded or in the mode of burying be arranged on underlying substrate.

27. preparation methods according to claim 26, it is characterized in that, described upper strata nude film adopts gold thread, copper cash or silver-colored line to realize electric interconnection with the interconnection line in top substrate layer and via hole, and the interconnection line in described lower floor nude film employing controlled collapse chip connection salient point or copper pillar bump and underlying substrate and via hole realize electric interconnection.

28. preparation methods according to claim 26, is characterized in that, described upper strata nude film or described lower floor nude film adopt discrete device to substitute.