CN104485289A - Wafer packaging method - Google Patents
Wafer packaging method Download PDFInfo
- Publication number
- CN104485289A CN104485289A CN201410784667.5A CN201410784667A CN104485289A CN 104485289 A CN104485289 A CN 104485289A CN 201410784667 A CN201410784667 A CN 201410784667A CN 104485289 A CN104485289 A CN 104485289A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- mask
- wafer packaging
- packaging method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a wafer packaging method. The method comprises the steps of providing a substrate, wherein the substrate comprises a central area in which a conductive metal cushion is formed, and an edge area opposite to the central area; forming an under bump metalization layer on the conductive metal cushion; forming a metal radiating layer in the edge area of the substrate; forming a bump structure on the under bump metalization layer. The wafer packaging method has the benefits that the metal radiating layer is formed on the front surface of the substrate, and a chip is formed on the front surface of the substrate, that is, both the metal radiating layer and the chip are positioned on the front surface of the substrate, so that the metal radiating layer is closer to the chip, which facilitates the radiating of the chip, and as a result, the radiating performance of a wafer packaging structure can be improved; in addition, the metal radiating layer can be formed and packaged without overturning the substrate, so that the process is simplified to some extent while the radiating purpose is reached.
Description
Technical field
The present invention relates to field of semiconductor package, be specifically related to a kind of wafer packaging method.
Background technology
Along with the development of integrated circuit technique, electronic product is more and more to miniaturized, intellectuality, high-performance and high reliability future development.And integrated antenna package not only directly affects the performance of integrated circuit, electronic module and even complete machine, but also govern the miniaturization of whole electronic system, low cost and reliability.Progressively reduce in integrated circuit (IC) wafer size, when integrated level improves constantly, electronics industry proposes more and more higher requirement to integrated antenna package technology.
The heat dispersion of packaged chip directly affects the service behaviour of packaged chip to a great extent.
To be formed with the packaged chip of MOSFET element, MOSFET element is made up of metal, oxide and semiconductor three kinds of materials, weighing one of key parameter values of MOSFET element is RDS value, RDS value represents MOSFET internal resistance value in the on-state, RDS value is lower, and the service behaviour of MOSFET is better; The main method reducing RDS value is improve the heat radiation of MOSFET element.
Therefore, how to promote the heat dispersion of wafer packaging structure further, become the technical problem that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
The problem that the present invention solves is to provide a kind of wafer packaging method, to improve the heat dispersion of wafer packaging structure.
For solving the problem, the invention provides a kind of wafer packaging method, comprising:
There is provided substrate, described substrate comprises the central area being formed with conducting metal pad, and relative to the fringe region of described central area;
Described conducting metal pad forms ball lower metal layer;
Metallic radiating layer is formed at the fringe region of described substrate;
Described ball lower metal layer forms bump structure.
Optionally, described metallic radiating layer and described ball lower metal layer are synchronously formed.
Optionally, the step of substrate is provided to comprise:
Described substrate surface forms the passivation layer exposing described conducting metal pad and substrate edge area;
After providing the step of substrate, before forming the step of ball lower metal layer, described wafer packaging method also comprises: on described passivation layer, form the protective layer exposing described conducting metal pad and substrate edge area.
Optionally, the material of described protective layer is polyimides.
Optionally, the step forming ball lower metal layer and metallic radiating layer comprises:
Described protective layer is formed the first mask and forms the second mask in substrate edge area, the conducting metal pad that described first mask, protective layer and protective layer expose surrounds the first opening jointly, and described second mask, the first mask and the substrate edge area exposed surround the second opening jointly;
Described ball lower metal layer is formed in described first opening;
Described metallic radiating layer is formed in described second opening.
Optionally, before forming the first mask, the second mask, described substrate and conducting metal pad form inculating crystal layer; Described first mask and the second mask are formed on described inculating crystal layer;
The step forming metallic radiating layer and ball lower metal layer comprises: form described ball lower metal layer by the mode of plating in described first open bottom and form described metallic radiating layer in described second open bottom;
Remove described first mask and the second mask.
Optionally, in described second opening, described passivation layer exposes the substrate of described fringe region, and described protective layer exposes described passivation layer, and described first mask exposes described protective layer, forms a step structure;
Described metallic radiating layer conformal is covered on described step structure.
Optionally, the first mask and second mask of light-sensitive material is formed.
Optionally, described metallic radiating layer is the frame-shaped construction thermosphere around substrate center region, to form surface metalation window structure on substrate.
Optionally, the material of described metallic radiating layer is copper.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form conducting metal pad by the central area in the front at described substrate, then form described metallic radiating layer at the fringe region relative to described central area, to be dispelled the heat to the chip in substrate by described metallic radiating layer.Because described metallic radiating layer is formed at the front of described substrate, because the front of substrate is formed with chip, that is, metallic radiating layer and chip are all positioned at the front of substrate, more close between metallic radiating layer and chip, this is conducive to helping chip cooling, namely improves the heat dispersion of wafer packaging structure.In addition, forming metallic radiating layer and encapsulating does not need the substrate that reverses, and this simplifies technique to a certain extent while reaching heat radiation object.
Accompanying drawing explanation
Fig. 1 to Fig. 7 is the structural representation of each step in wafer packaging method one embodiment of the present invention.
Embodiment
In order to promote the heat dispersion of wafer packaging structure, prior art forms one deck heat dissipation film at the back side of substrate.But because this method needs to form heat dissipation film at the back side of substrate, thus add the complexity of whole technique, complicated technique more easily produces mistake.Meanwhile, be formed at the heat dissipation film of substrate back away from the chip in substrate, thus radiating effect is also good not.
Therefore, the invention provides a kind of wafer packaging method, comprise the following steps:
There is provided substrate, described substrate comprises the central area being formed with conducting metal pad, and relative to the fringe region of described central area; Described conducting metal pad forms ball lower metal layer; Metallic radiating layer is formed at the fringe region of described substrate; Described ball lower metal layer forms bump structure.
Metallic radiating layer and chip are all positioned at the front of substrate, more close between metallic radiating layer and chip, and this is conducive to helping chip cooling, namely improves the heat dispersion of wafer packaging structure.In addition, forming metallic radiating layer and encapsulating does not need the substrate that reverses, and this simplifies technique to a certain extent while reaching heat radiation object.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First with reference to figure 1, substrate 101 is provided.In the present embodiment, described substrate 101 is the supplied materials disk silicon comprising one or more chip.
Described substrate 101 comprises the front 11 that is formed with chip and the back side 12 relative to described front.
The front 11 of described substrate 101 comprises the central area being formed with conducting metal pad 102, and relative to the fringe region of described central area; Described central area is used in subsequent step, form the package parts such as the ball lower metal layer of encapsulating structure and bump structure, and described fringe region is for the formation of metallic radiating layer.
Described conducting metal pad 102 for the chip circuit characteristic of substrate 101 inside being connected to substrate 101 surface so that be electrically connected with the package parts such as ball lower metal layer in subsequent step.
In the present embodiment, provide the also step of substrate 101 to be included in described substrate 101 surface and form passivation layer 103.Described passivation layer 103 may be used for the surface protecting described substrate 101.
Concrete, in the present embodiment, the material of described passivation layer 103 can be silicon dioxide or silicon nitride.But the material of the present invention to passivation layer 103 does not limit.
In the present embodiment, make the thickness of described passivation layer 103 in the scope of 1 ~ 2 micron.But this is only an example, the thickness of the present invention to described passivation layer 103 is not construed as limiting, but should determine according to actual conditions.
The conducting metal pad 102 on substrate 101 surface is exposed by described passivation layer 103, passivation layer 103 can be avoided so as far as possible to affect conducting metal pad 102 and be electrically connected with package parts such as ball lower metal layers.
In conjunction with reference to figure 2, after formation passivation layer 103, also form on described passivation layer 103 surface the protective layer 104 exposing described conducting metal pad 102.
Described protective layer 104 can be protected the passivation layer 103 on substrate 101 and substrate 101 further; because under normal circumstances; the quality of passivation layer 103 is more crisp (such as; the passivation layer 103 of silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material in the present embodiment); easy generation is damaged, so form layer protective layer 104 to be again conducive to protection substrate 101 and passivation layer 103 on passivation layer 103.
In addition, described protective layer 104 can also play the effect on planarization passivation layer 103 surface.Because generally, the thickness of passivation layer 103 is less, and the surface of substrate 101 have sometimes more concavo-convex (such as, some semiconductor device that substrate 101 surface is formed), that is, after covering passivation layer 103, substrate 101 surface still may be uneven, and this is unfavorable for the formation of follow-up lead-in wire metal level and pin configuration.Therefore, forming protective layer 104 can the surface of planarized substrate 101, and then facilitates follow-up lead-in wire metal level and the formation of pin configuration.
Described conducting metal pad 102 is exposed from described protective layer 104, affects conducting metal pad 102 to avoid protective layer 104 as far as possible and be electrically connected with the pin configuration of follow-up encapsulation.
In the present embodiment, the protective layer 104 of polyimide material is formed.This material has good elasticity, and quality is comparatively hard, is conducive to protection substrate 101 and passivation layer 103 further.
In the present embodiment, forming thickness is the protective layer 104 of 4 ~ 6 microns, is conducive to filling and leading up substrate 101 surface being coated with passivation layer 103 in this thickness range, is unlikely to again blocked up simultaneously and excessively increases the volume of whole encapsulating structure.
In conjunction with referring to figs. 2 and 3 shown, in the present embodiment, when forming passivation layer 103, make the fringe region of described passivation layer 103 exposed portion substrate 101, further, when forming protective layer 104, described protective layer 104 exposed portion passivation layer 103 is made, like this, the fringe region exposing substrate 101, the passivation layer 103 exposed and protective layer 104 form step structure jointly; Such benefit is, conformal is covered on described step structure by the metallic radiating layer of follow-up formation, and the surface area of the metallic radiating layer formed like this increases, and is conducive to the chip cooling in metallic radiating layer help substrate 101 further.
In the present embodiment, described metallic radiating layer and described ball lower metal layer are synchronously formed.
Concrete, can on described protective layer 104, form the first mask and form the second mask at the fringe region of substrate 101, the conducting metal pad 102 that described first mask, protective layer 104 and protective layer 104 expose surrounds the first opening 77 jointly, and described second mask, the first mask and the fringe region of substrate 101 exposed surround the second opening 78 jointly;
In described first opening 77, form described ball lower metal layer, in described second opening 78, form described metallic radiating layer simultaneously.
Further, the present invention can form described ball lower metal layer and metallic radiating layer by the mode of plating:
Described substrate 101 and conducting metal pad 102 form inculating crystal layer (not shown); Described inculating crystal layer is used for the Seed Layer forming metallic radiating layer as follow-up plating.
After this, described inculating crystal layer is formed the mask layer 201 comprising the first mask and the second mask.Described mask layer 201 is for sheltering from the part not needing to form metallic radiating layer and ball lower metal layer;
In the present embodiment, described mask layer 201 can be light-sensitive material, facilitates the step of the described mask layer 201 of follow-up removal to carry out like this, and the impact of removal light-sensitive material on peripheral devices is simultaneously less.
With reference to figure 3, remove component masking layer 201, with the inculating crystal layer on the substrate 101 of exposed portion conducting metal pad 102 and fringe region; That is, by removing component masking layer 201, to form the pattern of exposed portion inculating crystal layer in described mask layer 201.Concrete, the conducting metal pad 102 that described first mask, protective layer 104 and protective layer 104 expose surrounds the first opening 77 jointly, and described second mask, the first mask and the fringe region of substrate 101 exposed surround the second opening 78 jointly; As mentioned before, described first opening 77 is for the formation of ball lower metal layer, and described second opening 78 is for the formation of metallic radiating layer.
In the present embodiment, form the metallic radiating layer of shaped as frame, the pattern of the mask layer 201 being positioned at substrate 101 fringe region therefore should be made also to be the shape of corresponding shaped as frame.
With reference to figure 4, after this, electroplating metal material layer on the inculating crystal layer exposed, is wherein positioned at bottom the first opening 77, the metal material layer be namely positioned on described conducting metal pad 102 forms ball lower metal layer 106, and described ball lower metal layer 106 is for defining the bump structure position of follow-up formation.
In addition, be positioned at bottom the second opening 78, the metal material layer being namely positioned at the substrate 101 of fringe region forms described metallic radiating layer 108; While the described metallic radiating layer 108 of formation, also form ball lower metal layer 106 like this, simplify processing step.
But the present invention is to whether must form described metallic radiating layer 108 and ball lower metal layer 106 is not construed as limiting simultaneously, it will be understood by those skilled in the art that described metallic radiating layer 108 and ball lower metal layer 106 can adopt above-mentioned plating mode to be formed respectively.
In the present embodiment, form the metallic radiating layer 108 of copper product, that is, the metal material layer of plating is copper.Copper has higher thermal conductivity, is conducive to heat radiation further.
As mentioned before, it is the shape of shaped as frame that mask layer 201 is positioned at substrate 101 marginal zone with the pattern of part, and the metallic radiating layer 108 therefore formed also is frame-shaped construction accordingly.This structure ring is around in the fringe region of substrate 101, can either reach the object of heat radiation, also can not affect the encapsulation step of the central area of substrate 101 simultaneously.
In conjunction with reference to figure 5 and Fig. 6, wherein Fig. 6 is the vertical view of structure shown in Fig. 5.After formation metallic radiating layer 108 and ball lower metal layer 106, remove remaining mask layer 201.Described in going above, the metallic radiating layer 108 of formation is also frame-shaped construction accordingly, and then forms surface metalation window structure on the substrate 101.
With reference to figure 7, after the described ball lower metal layer 106 of formation, form bump structure 107 on described ball lower metal layer 106 surface.
But it should be noted that, the arrangement of the bump structure 107 shown in Fig. 7 is only an example of the present embodiment.The arrangement of the present invention to bump structure 107 is not construed as limiting.
In addition, with reference to figure 7, the present invention also provides a kind of wafer packaging structure, and in the present embodiment, described wafer packaging structure comprises:
Substrate 101.In the present embodiment, described substrate 101 is the supplied materials disk silicon comprising one or more chip.
Described substrate 101 comprises the front 11 that is formed with chip and the back side 12 relative to described front 11.
The front 11 of described substrate 101 comprises the central area being formed with conducting metal pad 102, and relative to the fringe region of described central area; Described central area is for the formation of the package parts such as ball lower metal layer 106 and bump structure 107 of encapsulating structure, and described fringe region is for the formation of metallic radiating layer 108.
Described conducting metal pad 102 is surperficial for the chip circuit characteristic of substrate 101 inside being connected to substrate 101, so that be electrically connected with package parts such as ball lower metal layer 106 grade.
In the present embodiment, passivation layer 103 is also formed with on described substrate 101 surface.Described passivation layer may be used for the surface protecting described substrate 101.
Concrete, in the present embodiment, the material of described passivation layer 103 can be silicon dioxide or silicon nitride.But the material of the present invention to passivation layer 103 does not limit.
In the present embodiment, the thickness of described passivation layer 103 is in the scope of 1 ~ 2 micron.But this is only an example, the thickness of the present invention to described passivation layer 103 is not construed as limiting, but should determine according to actual conditions.
The conducting metal pad 102 on substrate 101 surface exposes by described passivation layer 103, passivation layer 103 can be avoided so as far as possible to affect conducting metal pad 102 and be electrically connected with package parts such as ball lower metal layer 106 grade.
In the present embodiment, described passivation layer 103 surface is also formed with the protective layer 104 exposing described conducting metal pad 102.
Described protective layer 104 can be protected the passivation layer 103 on substrate 101 and substrate 101 further; because under normal circumstances; the quality of passivation layer 103 is more crisp (such as; the passivation layer 103 of silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material in the present embodiment); easy generation is damaged, so be formed with layer protective layer 104 to be again conducive to protection substrate 101 and passivation layer 103 on passivation layer 103.
In addition, described protective layer 104 can also play the effect on planarization passivation layer 103 surface.Because generally, the thickness of passivation layer 103 is less, and the surface of substrate 101 have sometimes more concavo-convex (such as, some semiconductor device that substrate 101 surface is formed), that is, after covering passivation layer 103, substrate 101 surface still may be uneven, and this is unfavorable for the formation of follow-up lead-in wire metal level and pin configuration.Therefore, protective layer 104 can the surface of planarized substrate 101, and then the formation of convenient lead-in wire metal level and pin configuration in the process forming wafer packaging structure.
Described conducting metal pad 102 exposes from described protective layer 104, affects conducting metal pad 102 be electrically connected with the pin configuration of follow-up encapsulation to avoid protective layer 104 as far as possible.
In the present embodiment, the material of protective layer 104 is polyimides.This material has good elasticity, and quality is comparatively hard, is conducive to protection substrate 101 and passivation layer 103 further.
In the present embodiment, the thickness unit of described protective layer 104 is 4 ~ 6 microns, is conducive to filling and leading up substrate 101 surface being coated with passivation layer 103 in this thickness range, is simultaneously unlikely to again blocked up and excessively increases the volume of whole encapsulating structure.
In the present embodiment, the fringe region of described passivation layer 103 exposed portion substrate 101; Further, described protective layer 104 exposed portion passivation layer 103.Like this, the fringe region exposing substrate 101, the passivation layer 103 exposed and protective layer 104 form step structure jointly.Its benefit will follow-up introduce metallic radiating layer 108 time be described.
Wafer packaging structure of the present invention also comprises the metallic radiating layer 108 of the fringe region being formed at described substrate 101 front 11.Metallic radiating layer 108 and chip are all positioned at the front 11 of substrate 101, more close between metallic radiating layer 108 and chip, and this is conducive to helping chip cooling, namely improves the heat dispersion of wafer packaging structure.In addition, forming metallic radiating layer 108 and encapsulating does not need the substrate 101 that reverses, and this simplifies technique to a certain extent while reaching heat radiation object.
In the present embodiment, the conformal of described metallic radiating layer 108 covers on the fringe region exposing substrate 101, the passivation layer 103 exposed and protective layer 104 common formation step structure.That is, described metallic radiating layer 108 is similarly step structure.
Such benefit is, the surface area of the metallic radiating layer 108 of step structure is larger, and this is conducive to the chip cooling that metallic radiating layer 108 helps in substrate 101 further.
In the present embodiment, form the metallic radiating layer 108 (with reference to figure 7) of shaped as frame, and then form surface metalation window structure on the substrate 101.This structure ring is around in the fringe region of substrate 101, can either reach the object of heat radiation, also can not affect the encapsulating structure such as ball lower metal layer 106 grade of substrate 101 central area simultaneously.
In the present embodiment, the material of described metallic radiating layer 108 is copper.Copper has higher thermal conductivity, and then is conducive to heat radiation further.
In the present embodiment, round encapsulating structure of the present invention also comprises the ball lower metal layer 106 being formed at described conducting metal pad 102 surface, and is formed at the bump structure 107 on described ball lower metal layer 106 surface.
In the present embodiment, described bump structure 107 is spherical.But the shape of the present invention to described bump structure 107 is not limited in any way.
Wafer packaging structure of the present invention can be, but not limited to adopt above-mentioned wafer packaging method to obtain.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a wafer packaging method, is characterized in that, comprising:
There is provided substrate, described substrate comprises the central area being formed with conducting metal pad, and relative to the fringe region of described central area;
Described conducting metal pad forms ball lower metal layer;
Metallic radiating layer is formed at the fringe region of described substrate;
Described ball lower metal layer forms bump structure.
2. wafer packaging method as claimed in claim 1, it is characterized in that, described metallic radiating layer and described ball lower metal layer are synchronously formed.
3. wafer packaging method as claimed in claim 1, is characterized in that, provide the step of substrate to comprise:
Described substrate surface forms the passivation layer exposing described conducting metal pad and substrate edge area;
After providing the step of substrate, before forming the step of ball lower metal layer, described wafer packaging method also comprises: on described passivation layer, form the protective layer exposing described conducting metal pad and substrate edge area.
4. wafer packaging method as claimed in claim 3, it is characterized in that, the material of described protective layer is polyimides.
5. wafer packaging method as claimed in claim 3, is characterized in that, the step forming ball lower metal layer and metallic radiating layer comprises:
Described protective layer is formed the first mask and forms the second mask in substrate edge area, the conducting metal pad that described first mask, protective layer and protective layer expose surrounds the first opening jointly, and described second mask, the first mask and the substrate edge area exposed surround the second opening jointly;
Described ball lower metal layer is formed in described first opening;
Described metallic radiating layer is formed in described second opening.
6. wafer packaging method as claimed in claim 5, is characterized in that, before forming the first mask, the second mask, described substrate and conducting metal pad form inculating crystal layer; Described first mask and the second mask are formed on described inculating crystal layer;
The step forming metallic radiating layer and ball lower metal layer comprises: form described ball lower metal layer by the mode of plating in described first open bottom and form described metallic radiating layer in described second open bottom;
Remove described first mask and the second mask.
7. wafer packaging method as claimed in claim 5, is characterized in that, in described second opening, described passivation layer exposes the substrate of described fringe region, described protective layer exposes described passivation layer, and described first mask exposes described protective layer, forms a step structure;
Described metallic radiating layer conformal is covered on described step structure.
8. wafer packaging method as claimed in claim 5, is characterized in that, forms the first mask and second mask of light-sensitive material.
9. wafer packaging method as claimed in claim 1, it is characterized in that, described metallic radiating layer is the frame-shaped construction thermosphere around substrate center region, to form surface metalation window structure on substrate.
10. wafer packaging method as claimed in claim 1, it is characterized in that, the material of described metallic radiating layer is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410784667.5A CN104485289B (en) | 2014-12-16 | 2014-12-16 | Wafer packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410784667.5A CN104485289B (en) | 2014-12-16 | 2014-12-16 | Wafer packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104485289A true CN104485289A (en) | 2015-04-01 |
| CN104485289B CN104485289B (en) | 2017-09-08 |
Family
ID=52759825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410784667.5A Active CN104485289B (en) | 2014-12-16 | 2014-12-16 | Wafer packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104485289B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449562A (en) * | 2016-11-27 | 2017-02-22 | 南通沃特光电科技有限公司 | Packaging method of wafer provided with heat dissipation structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040092092A1 (en) * | 2002-11-12 | 2004-05-13 | Siliconware Precision Industries, Ltd. | Semiconductor device with under bump metallurgy and method for fabricating the same |
| CN101150110A (en) * | 2006-09-21 | 2008-03-26 | 矽品精密工业股份有限公司 | Semiconductor package and substrate structure thereof |
| CN103035579A (en) * | 2011-10-05 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Wafer level chip scale package and method of manufacturing the same |
| JP2013089853A (en) * | 2011-10-20 | 2013-05-13 | Keihin Corp | Printed wiring board |
-
2014
- 2014-12-16 CN CN201410784667.5A patent/CN104485289B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040092092A1 (en) * | 2002-11-12 | 2004-05-13 | Siliconware Precision Industries, Ltd. | Semiconductor device with under bump metallurgy and method for fabricating the same |
| CN101150110A (en) * | 2006-09-21 | 2008-03-26 | 矽品精密工业股份有限公司 | Semiconductor package and substrate structure thereof |
| CN103035579A (en) * | 2011-10-05 | 2013-04-10 | 台湾积体电路制造股份有限公司 | Wafer level chip scale package and method of manufacturing the same |
| JP2013089853A (en) * | 2011-10-20 | 2013-05-13 | Keihin Corp | Printed wiring board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449562A (en) * | 2016-11-27 | 2017-02-22 | 南通沃特光电科技有限公司 | Packaging method of wafer provided with heat dissipation structure |
| CN106449562B (en) * | 2016-11-27 | 2019-01-04 | 海安浩驰科技有限公司 | A kind of wafer packaging method with radiator structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104485289B (en) | 2017-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12136593B2 (en) | Electronic apparatus including antennas and directors | |
| US11961867B2 (en) | Electronic device package and fabricating method thereof | |
| US11245176B2 (en) | Package structure, electronic device and method of fabricating package structure | |
| US20220013421A1 (en) | Shielded fan-out packaged semiconductor device and method of manufacturing | |
| US10978406B2 (en) | Semiconductor package including EMI shielding structure and method for forming the same | |
| TWI676244B (en) | A semiconductor package and method for fabricating the same | |
| US20180166405A1 (en) | Structure and formation method of chip package with antenna element | |
| US10658333B2 (en) | Package structure and method of fabricating the same | |
| US20240312904A1 (en) | Method of fabricating package structure | |
| KR20150145697A (en) | Semiconductor package and method of manufacturing the same | |
| US20190198434A1 (en) | Semiconductor packaging structure with antenna assembly | |
| US10636757B2 (en) | Integrated circuit component package and method of fabricating the same | |
| US11081435B2 (en) | Package substrate and flip-chip package circuit including the same | |
| CN104465556A (en) | Wafer packaging structure | |
| CN109524365A (en) | Semiconductor structure and manufacturing method thereof | |
| CN104485289A (en) | Wafer packaging method | |
| KR20170086377A (en) | Device for fan-out type track pad semiconductor package and method for manufacturing the same | |
| US8421173B2 (en) | Chip package structure and chip packaging process | |
| CN115101511A (en) | A packaging device and packaging method | |
| KR102240407B1 (en) | Semiconductor package | |
| US11682648B2 (en) | Semiconductor device and method of fabricating the same | |
| CN104465571A (en) | Wafer packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |