CN104485284B - A controllable array nanowire and its field effect transistor preparation method - Google Patents

Abstract

The invention discloses the preparation method and its preparation method of field-effect transistor of a kind of controllable aligned nanowires.Growth material is used as substrate along the anisotropic material of growth rate of different crystal orientations during the present invention is grown by selective epitaxy, so as to realize the growth of nano wire；Arrangement and diameter by design configuration substrate, can cycle of accuracy controlling aligned nanowires, quantity, length and diameter, meet different FET demands；The growth conditions of rich VI races or rich V group atom reaches the effect of surface suppression, reduces isotropism of the metallic atom on surface and migrates, and is conducive to the growth of nano wire；Preparing for controllable aligned nanowires FET can use traditional semiconductor device fabrication processes, and process is simple, Modulatory character is strong, with low cost, can realize batch production.

Description

A controllable array nanowire and its field effect transistor preparation method

technical field

The invention relates to a preparation method of a field effect transistor, in particular to a preparation method of a controllable array nanowire and a preparation method of a controllable array nanowire field effect transistor.

Background technique

One-dimensional semiconductor nanostructures have high crystal quality, excellent electrical and optical properties, making them ideal for nanoscale devices, such as field effect devices, photodetector devices, high-efficiency light-emitting devices, sensor devices, single-electron memory devices, and single-photon devices. etc., have a wide range of application value. Field effect transistor FET is a three-terminal element made of semiconductor material and controlled by voltage. It plays an extremely important role in electronic circuits. Nanowire FET is the cornerstone of the application of nanoelectronic devices.

The development of FET has experienced the evolution from planar FET to fin FET to nanowire FET. Since the fin FET is a nano-scale channel obtained by micro-nano processing technology, some additional defects and damage will inevitably be generated in the process, which will reduce the efficacy of the FET; however, the nanowire is an original growth nanostructure with good Excellent surface morphology and high crystal quality, and the nanowire FET has the advantages of the fin FET. However, the source-drain current of a single nanowire FET is relatively small, making it difficult to obtain practical applications. In addition, the nanowire FET can improve the source-drain current and the control ability of the gate voltage to the source-drain current by controlling the number of nanowires in the channel, so as to improve the transconductance, source-drain current and switch ratio of the FET. Therefore, the array nanometer Line FET came into being.

At present, the methods for preparing arrayed nanowire FETs mainly include the method of controlling the array arrangement of nanowires by an external method and the method of growing nanowires laterally. However, the former is difficult to obtain large-area arrayed nanowires, and the latter is poorly controllable, which makes it difficult to realize controllable arrayed nanowire FETs.

Contents of the invention

Aiming at the above existing problems in the prior art, the present invention proposes a method for preparing controllable array nanowires and field-effect transistors thereof, which can produce controllable array nanowires, such as the period, diameter, length and number of nanowires. It can be adjusted, and on this basis, the controllable array nanowire field effect transistor FET is prepared by using the traditional semiconductor device manufacturing process.

An object of the present invention is to provide a method for preparing a controllable array of nanowires.

The method for preparing controllable array nanowires of the present invention is used to prepare II-VI or III-V array nanowires, comprising the following steps:

1) Select a growth material with anisotropic growth rate along different crystal directions as the substrate;

2) According to the preparation requirements of the field effect transistor FET, the pattern of the patterned substrate is designed, and the patterned substrate is prepared;

3) Pretreating the patterned substrate to make the surface of the patterned substrate clean;

4) According to the growth rate of the most preferential growth crystal direction, determine the atomic beam current of VI group or V group atoms;

5) Determine the atomic beam current of group II or group III atoms according to the period and diameter of the arrayed nanowires;

6) According to the conditions determined above, grow arrayed nanowires on a clean patterned substrate.

Wherein, in step 1), the selection of the material of the substrate needs to consider that the growth rate of the material grown on it along different crystal directions is anisotropic. The direction of the nanowires grown on the substrate is along the most preferential growth crystal direction, and the growth rate anisotropy of the growth material along different crystal directions is stronger, that is, the ratio of the growth rate of the most preferential growth crystal direction to the growth rate of other directions The larger is the more pronounced the single linearity of the nanowire. The most preferred growth direction is in the plane of the substrate.

In step 2), designing the graphics of the patterned substrate means that the preparation of the field effect transistor FET requires determining the period and diameter of the array nanowires, and designing the pattern arrangement of the patterned substrate according to the period and diameter of the array nanowires. cloth and diameter. The pattern of the patterned substrate is a periodic columnar two-dimensional lattice, or a periodic hole-shaped two-dimensional lattice. The arrangement of graphics can be a two-dimensional dot matrix arranged at equal intervals, or a two-dimensional dot matrix arranged in a rectangle. The column direction of the two-dimensional lattice is arranged along the most preferential growth crystal direction, the distance between two adjacent columns (column spacing) is the period of the array nanowire, and the length of the column direction determines the length of the nanowire; the two-dimensional lattice The number of columns is the number of nanowires in the array. The diameter d of the pillar or the hole determines the diameter D of the nanowire, the diameter D of the nanowire is slightly larger than the diameter d of the pillar or the hole, and the ratio D/d between the two is between 1 and 3. The preparation methods of the patterned substrate include: nanoimprint technology, electron beam exposure EBL and focused ion beam FIB, etc.

In step 3), the pretreatment of the patterned substrate includes: chemically cleaning the prepared patterned substrate, and then performing high-temperature baking to remove impurity atoms on the surface, thereby making the surface of the patterned substrate clean.

In step 4), the growth method of the arrayed nanowires determines the growth rate ν of the most preferential growth crystal direction, and the growth rate ν of the most preferential growth crystal direction determines the atomic beam current F ₁ of group VI or group V atoms, satisfying the relationship F ₁ =k ₁ ν, where k ₁ is a coefficient related to the crystal structure of the material of the nanowire array.

In step 5), the growth of arrayed nanowires usually selects growth conditions rich in group VI or rich in group V atoms, which is conducive to inhibiting the isotropic migration of metal atoms on the surface, thereby realizing the growth of controllable arrayed nanowires, specifically The group II or group III atomic beam F ₂ needs to be determined according to the period and diameter of the designed array nanowires, the group II or group III atomic beam F ₂ is related to the diameter D of the nanowire and the pattern of the patterned substrate It is related to the arrangement and satisfies the relational formula: F ₂ =k ₂ D ² /L ₁ ² , or F ₂ =k ₂ D ² /(L ₂ L ₃ ), where k ₂ is a coefficient, which is the same as that used for growing arrayed nanowires The growth method is related, L ₁ is the distance between two adjacent points in the two-dimensional lattice arranged at equal intervals, L ₂ and L ₃ are the row spacing and column spacing in the two-dimensional lattice arranged in a rectangle .

In step 6), the methods for growing controllable array nanowires include: molecular beam epitaxy MBE, metal organic chemical vapor deposition MOCVD, chemical vapor deposition CVD, pulsed laser deposition PLD, and the like. As the growth time increases, nanowire segments with increasing length will grow on the pillars or holes of the patterned substrate until the nanowire segments are connected into a complete straight line, and the growth ends. Before the nanowire segments combine with each other, the length of the nanowire segments can be regulated by the growth time, and the longer the growth time, the longer the length of the nanowire segments.

Another object of the present invention is to provide a method for preparing a controllable array nanowire field effect transistor.

The preparation method of the controllable array nanowire field effect transistor FET of the present invention is used to prepare the array nanowires of the II-VI group or the III-V group, comprising the following steps:

1) Select a growth material with anisotropic growth rate along different crystal directions as the substrate;

2) According to the preparation requirements of the field effect transistor FET, the pattern of the patterned substrate is designed, and the patterned substrate is prepared;

3) Pretreating the patterned substrate to make the surface of the patterned substrate clean;

4) According to the growth rate of the most preferential growth crystal direction, determine the atomic beam current of VI group or V group atoms;

5) Determine the atomic beam current of group II or group III atoms according to the period and diameter of the patterned substrate;

6) growing arrayed nanowires on a clean patterned substrate according to the conditions determined above;

7) The arrayed nanowires grown on the substrate are used as the channel region of the FET, and a source, a drain, a gate insulating layer and a gate are sequentially formed thereon by using a traditional semiconductor device preparation process.

Wherein, in step 7), when preparing the arrayed nanowire FET, the number of nanowires contained in the channel region can be selected according to the preparation requirements of the FET, so as to meet different requirements of the FET.

Arrayed nanowires refer to a group of nanowires arranged in an array in the same direction. Experiments have found that the growth rate of semiconductor materials along different crystal directions presents obvious anisotropy. The present invention uses this characteristic to select a substrate with anisotropic growth rate of growth materials along different crystal directions to prepare nanowires with consistent orientations. , the period, diameter, length and number of arrayed nanowires can be further regulated by patterning the substrate, thereby preparing a controllable arrayed nanowire FET.

Advantages of the present invention:

(1) By designing the arrangement and diameter of the patterned substrate, the period, quantity, length and diameter of the arrayed nanowires can be precisely regulated to meet different FET requirements;

(2) Select a material with anisotropic growth rate of the growth material along different crystal directions during epitaxial growth as the substrate, so as to realize the growth of nanowires;

(3) The growth conditions of rich VI or V atoms achieve the effect of surface inhibition, which reduces the isotropic migration of metal atoms on the surface and is conducive to the growth of nanowires;

(4) The preparation of the controllable array nanowire FET can adopt the traditional semiconductor device preparation process, the process is simple, the controllability is strong, the cost is low, and mass production can be realized.

Description of drawings

Fig. 1 is obtained in Example 1 of the method for preparing controllable array nanowires according to the present invention. A partial schematic diagram of a surface GaN columnar patterned substrate, where (a) is a top view and (b) is a side view;

Fig. 2 is obtained in Example 1 of the method for preparing controllable array nanowires according to the present invention. Partial schematic diagram of a nanowire segment on a GaN columnar patterned substrate, where (a) is a top view and (b) is a side view;

Fig. 3 is obtained in Embodiment 1 of the method for preparing controllable array nanowires according to the present invention. Partial schematic diagram of arrayed nanowires on a GaN columnar patterned substrate, where (a) is a top view and (b) is a side view;

Fig. 4 is obtained in Example 2 of the preparation method of controllable array nanowires according to the present invention. Partial schematic diagram of surface 4H-SiC hole-shaped patterned substrate, where (a) is a top view, and (b) is a cross-sectional view along line AA' in figure (a);

Fig. 5 is the results obtained in Example 2 of the preparation method of controllable array nanowires according to the present invention. Partial schematic diagram of a nanowire segment on a 4H-SiC hole patterned substrate, where (a) is a top view, and (b) is a cross-sectional view along line AA' in figure (a);

Fig. 6 is the results obtained in Example 2 of the preparation method of controllable array nanowires according to the present invention. A partial schematic diagram of arrayed nanowires on a surface 4H-SiC hole patterned substrate, where (a) is a top view, and (b) is a cross-sectional view along line AA' in figure (a);

Figure 7 is a schematic diagram of a controllable array nanowire FET obtained according to the preparation method of a controllable array nanowire field effect transistor of the present invention, wherein (a) is a top view, and (b) is along B-B in figure (a) 'The profile of the line, (c) is a side view.

detailed description

The present invention will be further described through the embodiments below in conjunction with the accompanying drawings.

Embodiment one

In this embodiment, the GaN controllable array nanowires are prepared, and the substrate adopts GaN; the pattern of the patterned substrate is a periodic columnar two-dimensional lattice; the growth material of the array nanowires is GaN; the growth method of the array nanowires adopts Molecular beam epitaxy MBE in The growth process is carried out in an ultra-high vacuum growth chamber, and the high-purity (7N) metal source is generated by a K-Cell source furnace; the nitrogen source uses a radio frequency plasma nitrogen source; the growth process uses a reflective High-energy electron diffractometer RHEED in-situ monitoring.

The preparation method of the controllable array nanowires of this embodiment includes the following steps:

1) Select the growth material with anisotropic growth rate along different crystal directions as the substrate:

The growth rate of wurtzite GaN along the [0001] direction is much faster than that along the with The growth rate in the direction, choose surface GaN as the substrate, so that [0001] and The direction is in the substrate plane, which is conducive to the growth of nanowires.

2) According to the preparation requirements of the field effect transistor FET, design the pattern of the patterned substrate, and prepare the patterned substrate:

The pattern of the patterned substrate is a cylindrical two-dimensional lattice arranged at equal intervals, the distance between two adjacent points is 500nm, the diameter d=350nm, and there is no mask, the column spacing of the two-dimensional lattice is The distance between two points×sin 60°, that is, 500×sin 60°=433nm, a patterned substrate was prepared by nanoimprinting method, as shown in FIG. 1 .

3) Pretreating the patterned substrate to make the surface of the patterned substrate clean:

Firstly, the patterned substrate is cleaned by a chemical method, so that the surface of the patterned substrate is clean; then, the temperature of the patterned substrate is raised to about 600° C., and baked for 10-30 minutes.

4) According to the growth rate of the most preferential growth crystal direction, determine the atomic beam current of group V atoms:

The growth method of molecular beam epitaxy MBE determines the most preferential growth crystal direction - the growth rate of the [0001] direction is 10nm/min, and the beam current of nitrogen atoms is about F _N =7.6×10 ¹⁴ cm ^-2 s ^-2 .

5) Determine the atomic beam current of Group III atoms according to the period and diameter of the patterned substrate:

According to the period and diameter of the pattern, the optimized atomic beam current ratio is F _N /F _Ga =5, and the beam current of Ga atoms is about F _Ga =1.52×10 ¹⁴ cm ^-2 s ^-2 .

6) According to the conditions determined above, grow arrayed nanowires on a clean patterned substrate. As the growth time increases, nanowire segments with gradually increasing lengths will grow on the pillars of the patterned substrate, as shown in Figure 2 As shown, until the nanowire segments are connected into a complete straight line, the growth of the array nanowires is completed, as shown in Figure 3, the period P of the obtained array nanowires is the column spacing of the nanowires 433nm, and the diameter of the nanowires is D =400nm, for a two-dimensional lattice arranged at equal intervals, the length L of the nanowire is the number of points in the column × the distance between two adjacent points, the number of nanowires is the number of columns of the two-dimensional lattice, and a single nanometer The shape of the cross-section of the wire is a regular hexagon. The growth process was monitored in situ with RHEED.

The GaN controllable array nanowires grown by this method have good surface morphology and high crystal quality. The scanning electron microscope SEM test shows that the orientation of the nanowires is consistent along the [0001] direction, and the growth rate of the nanowires along the [0001] direction is obvious. higher than direction.

Embodiment two

In this embodiment, a GaN controllable array nanowire FET is prepared, and the substrate is GaN; the pattern of the patterned substrate is a periodic hole-like two-dimensional lattice; the growth material of the array nanowire is GaN; the growth of the array nanowire The method uses molecular beam epitaxy (MBE) in The growth process is carried out in an ultra-high vacuum chamber, and the high-purity (7N) metal source is generated by a K-Cell source furnace; the nitrogen source is a radio frequency plasma nitrogen source; the growth process uses a reflection RHEED in situ monitoring.

The preparation method of the controllable array nanowire FET of this embodiment includes the following steps:

1) Select the growth material with anisotropic growth rate along different crystal directions as the substrate:

The growth rate of wurtzite GaN along the [0001] direction is much faster than that along the with The growth rate in the direction, choose surface 4H-SiC as the substrate, so that [0001] and The direction is in the substrate plane, which is conducive to the growth of nanowires.

2) According to the preparation requirements of the field effect transistor FET, design the pattern of the patterned substrate, and prepare the patterned substrate:

The pattern of the patterned substrate is a two-dimensional dot matrix with masked circular holes arranged in four directions. On the surface 4H-SiC substrate 1, 20nm thick SiO ₂ is grown by plasma-enhanced chemical vapor deposition PECVD method as a mask 21, and then a patterned substrate is prepared by using focused ion beam FIB. Two-dimensional dot matrix 2, as shown in Figure 4, prepared three graphics with different column spacing, and the specific parameters are shown in the following table:

Column spacing/μm 1.0 2.0 3.0 Line spacing/μm 1.0 2.0 3.0 diameter d/nm 50 50 50

3) Pretreating the patterned substrate to make the surface of the patterned substrate clean:

Firstly, the patterned substrate is cleaned by a chemical method, so that the surface of the patterned substrate is clean; then, the temperature of the patterned substrate is raised to about 600° C., and baked for 10-30 minutes.

4) According to the growth rate of the most preferential growth crystal direction, determine the atomic beam current of group V atoms:

The growth method of molecular beam epitaxy MBE determines the most preferential growth crystal direction - the growth rate of the [0001] direction is 10nm/min, and the beam current of nitrogen atoms is about F _N =7.6×10 ¹⁴ cm ^-2 s ^-2 .

5) Determine the atomic beam current of Group III atoms according to the period and diameter of the patterned substrate:

The corresponding atomic beam currents of the three graphs with different column spacing are shown in the table below:

Column spacing/μm 1.0 2.0 3.0 5 10 15 1.52 0.76 0.51

6) According to the conditions determined above, grow arrayed nanowires on a clean patterned substrate, as the growth time increases, nanowire segments 31 with gradually increasing lengths will grow on the holes of the patterned substrate, as shown in Fig. 5, until the nanowire segments are connected into a complete straight line, the growth of the array nanowire 3 is completed. As shown in FIG. 6, the shape of the cross-section of a single nanowire is a regular hexagon. The length L of the nanowires is the row spacing × the number of rows, and the number of nanowires is the number of columns of the two-dimensional lattice. The relevant parameters of the obtained array nanowires are shown in the following table:

Column spacing/μm 1.0 2.0 3.0 Period P/μm of arrayed nanowires 1.0 2.0 3.0 Nanowire diameter D/nm 150 120 100

The growth process was monitored in situ with RHEED. The GaN controllable array nanowires grown by this method have good surface morphology and high crystal quality. SEM tests show that the orientation of the nanowires is consistent along the [0001] direction, and the growth rate of the nanowires along the [0001] direction is significantly higher than that of direction, and the length of the nanowire segments before they combine with each other can be regulated by the growth time.

7) Use the array nanowires that have been grown on the substrate as the channel region of the FET, and select the number of nanowires contained in the channel region according to the preparation requirements of the FET to meet the requirements of the prepared FET; The manufacturing process of the semiconductor device, on which the source electrode 4, the drain electrode 5, the gate insulating layer 6 and the gate electrode 7 are sequentially formed to obtain a controllable array nanowire FET, as shown in FIG. 7 .

The examples of preparing array nanowires and array nanowire FETs are respectively given above. The preparation method of the present invention can prepare II-VI group or III-V group and other semiconductor controllable array nanowire FETs, as long as the involved semiconductor material has anisotropic growth rate, the method of the present invention can be used to select the substrate, Design graphics according to FET requirements, prepare a patterned substrate, determine the atomic beam current of each growth source according to the parameters such as the period and diameter of the graphics, and realize the growth of controllable array nanowires, thereby preparing controllable array nanowires, and hereby On the basis of combining the traditional semiconductor device manufacturing process, the controllable array nanowire FET is prepared.

Finally, it should be noted that the purpose of publishing the implementation is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications can be made without departing from the spirit and scope of the present invention and the appended claims. It is possible. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

Claims (8)

1. a kind of preparation method of controllable aligned nanowires, the aligned nanowires for preparing II-VI group or iii-v, it is special Levy and be, the preparation method is comprised the following steps：

1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate；

2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate；

3) patterned substrate is pre-processed, makes the clean surface of patterned substrate；

4) growth rate of crystal orientation is grown according to override, the atom line of VI races or V group atom is determined；

5) cycle according to aligned nanowires and diameter, determine the atom line of II races or III atom；

6) according to condition determined above, aligned nanowires are grown in clean patterned substrate；

Wherein, in step 2) in, cycle and diameter according to aligned nanowires, the arrangement of the figure of design configuration substrate and straight Footpath；The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice；The row of figure Cloth is the two-dimensional lattice of equidistant arrangement, or rectanglar arrangement two-dimensional lattice；

In step 6) in, with the increase of growth time, grow length in the post or Kong Shanghui of patterned substrate and gradually increase Nano wire segment, untill nano wire segment connects into a complete straight line, growth terminates；It is mutual in nano wire segment With reference to before, the length of nano wire segment is regulated and controled by growth time, and the length of growth time nano wire segment more long is more It is long.

2. preparation method as claimed in claim 1, it is characterised in that in step 1) in, in the nano wire of Grown Direction grows crystal orientation along override, and growth material is stronger along the growth rate anisotropy of different crystal orientations, i.e. override growth The growth rate of crystal orientation is bigger with the ratio between the growth rate in other directions, and the single linear of nano wire is more notable；Override growth is brilliant To in substrate surface.

3. preparation method as claimed in claim 1, it is characterised in that the row of two-dimensional lattice are arranged to along override growth crystal orientation The distance between row, adjacent two row are the cycle of aligned nanowires；The columns of two-dimensional lattice is the quantity of aligned nanowires.

4. preparation method as claimed in claim 1, it is characterised in that the diameter d in post or hole determines the diameter D of nano wire, two The value of the ratio between person D/d is between 1~3.

5. preparation method as claimed in claim 1, it is characterised in that in step 4) in, the growing method of aligned nanowires is determined The growth rate ν that override grows crystal orientation is determined, the growth rate ν of override growth crystal orientation determines the original of VI races or V group atom Beamlet stream F₁, meet relation F₁=k₁ν, wherein, k₁It is coefficient, the crystal structure with the material of aligned nanowires is relevant.

6. preparation method as claimed in claim 1, it is characterised in that in step 5) in, the growth selection of aligned nanowires is rich VI races or the growth conditions of rich V group atom, II races or III atom line F₂, with the diameter D of nano wire and patterned substrate The arrangement of figure is relevant, meets relational expression：F₂=k₂D²/L₁ ², or F₂=k₂D²/(L₂L₃), wherein, k₂It is coefficient, with growth battle array The growing method for being used of row nano wire is relevant, L₁For in the two-dimensional lattice of equidistant arrangement, the distance between adjacent 2 points, L₂And L₃Line space and column pitch respectively in the two-dimensional lattice of rectanglar arrangement.

7. a kind of preparation method of controllable aligned nanowires field-effect transistor FET, for preparing II-VI group or iii-v Aligned nanowires, it is characterised in that the preparation method is comprised the following steps：

1) growth material is chosen along the anisotropic material of growth rate of different crystal orientations as substrate；

2) the preparation requirement according to field-effect transistor FET, the figure of design configuration substrate prepares patterned substrate；

3) patterned substrate is pre-processed, makes the clean surface of patterned substrate；

4) growth rate of crystal orientation is grown according to override, the atom line of VI races or V group atom is determined；

5) cycle according to patterned substrate and diameter, determine the atom line of II races or III atom；

6) according to condition determined above, aligned nanowires are grown in clean patterned substrate；

7) aligned nanowires that will have been grown on substrate are prepared as the channel region of FET using traditional semiconductor devices Technique, sequentially forms source electrode, drain electrode, gate insulator and grid thereon；

Wherein, in step 2) in, cycle and diameter according to aligned nanowires, the arrangement of the figure of design configuration substrate and straight Footpath；The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice；The row of figure Cloth is the two-dimensional lattice of equidistant arrangement, or rectanglar arrangement two-dimensional lattice；

In step 6) in, with the increase of growth time, grow length in the post or Kong Shanghui of patterned substrate and gradually increase Nano wire segment, untill nano wire segment connects into a complete straight line, growth terminates；It is mutual in nano wire segment With reference to before, the length of nano wire segment is regulated and controled by growth time, and the length of growth time nano wire segment more long is more It is long.

8. preparation method as claimed in claim 7, it is characterised in that in step 7) in, the preparation requirement selection ditch according to FET The quantity of contained nano wire in road area, to meet the demand of FET.