CN104466905B

CN104466905B - Fault arc protection device and method thereof

Info

Publication number: CN104466905B
Application number: CN201410818674.2A
Authority: CN
Inventors: 王新
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2014-12-23
Filing date: 2014-12-23
Publication date: 2017-07-25
Anticipated expiration: 2034-12-23
Also published as: CN104466905A

Abstract

The invention discloses a fault arc protection device and a method thereof. The fault arc protection device includes: the protection circuit comprises a control unit, a pulse detection circuit and a zero-crossing detection circuit, wherein the pulse detection circuit samples a current signal of a protected circuit to obtain a detection circuit pulse signal, and sends the detection circuit pulse signal to the control unit; when the zero-crossing detection circuit detects that the current value of the current signal is zero, a trigger electric signal is sent to the control unit; the control unit periodically analyzes the detection circuit pulse signal based on the trigger electric signal to detect a fault arc. The fault arc protection device can shorten the judgment time, improve the response speed and be more reliable and effective for fault arc protection.

Description

Fault arc protection device and method thereof

Technical Field

The invention relates to the technical field of electrical protection, in particular to a fault arc protection device and a method thereof.

Background

The Arc-fault circuit protection (AFCI) is a new circuit protection technology, and its main function is to prevent some fires caused by fault arcs. These dangerous arcs may occur on household wiring, when plugs and sockets are connected, on wiring harnesses inside household appliances or on power cords of appliances, etc. The main cause of the fault arc is the wear of the wire insulation or poor electrical connection. Some fault arc protection circuits exist in the prior art, but the fault arc protection circuits have the defects of single judgment condition and long judgment cycle time.

Disclosure of Invention

The invention aims to solve the technical problem that the fault arc protection circuit in the prior art has the defect of long judgment period.

According to a first aspect of the present invention, there is provided a fault arc protection device comprising: the pulse detection circuit is used for sampling a current signal of a protected circuit to obtain a detection circuit pulse signal and sending the detection circuit pulse signal to the control unit; the zero-crossing detection circuit is used for sending a trigger electric signal to the control unit when the current value of the current signal is detected to be zero; and the control unit is used for periodically analyzing the detection circuit pulse signal based on the trigger electric signal so as to detect the fault arc.

Further, the control unit starts counting the detection circuit pulse signals after receiving the trigger electric signal, and when the number of the detection circuit pulse signals detected in one period of the current signal is greater than or equal to a first threshold value, the number is recorded as 1 series arc.

Further, the control unit judges whether the number of detected series arcs is greater than or equal to a first set value in a predetermined number of consecutive cycles, and if so, determines that a series fault arc is detected.

Further, if the control unit detects two detection circuit pulse signals which are low and high in a half period of the current signal, the series type electric arc in the protected circuit is determined to occur.

Further, the first threshold value is 4.

Further, the pulse detection circuit includes: the circuit comprises a current transformer, a first resistor, a second resistor, a first full-bridge rectifying circuit and a first capacitor; wherein, the first output pin of current transformer's secondary coil is connected to the first end of first resistance, the second end of first resistance is connected to the first end of first full-bridge rectifier circuit, the second output pin of current transformer's secondary coil is connected to the third end of first full-bridge rectifier circuit, the second end ground connection of first full-bridge rectifier circuit, the fourth end of first full-bridge rectifier circuit is connected to the first end of second resistance, the second end ground connection of second resistance, and the first end of second resistance is connected to the first input of control unit, the one end of first electric capacity is connected to the first end of second resistance, other end ground connection.

Further, the pulse detection circuit further includes: the first end of the second resistor is connected to the first end of the third resistor, the second end of the third resistor is connected with the first end of the fourth resistor, the cathode of the first voltage stabilizing diode and the first input end of the control unit in a common mode, and the second end of the fourth resistor and the anode of the first voltage stabilizing diode are both grounded.

Further, still include: a high-frequency component detection circuit for detecting a high-frequency harmonic component in the current signal of the protected circuit, sampling the high-frequency harmonic component to obtain a high-frequency detection pulse signal, and inputting the high-frequency detection pulse signal to the control unit; the control unit starts to count the high-frequency detection pulse signals after receiving the trigger electric signal, and judges whether the number of the high-frequency detection pulse signals is smaller than a second threshold value and the number of the detection circuit pulse signals is equal to a third threshold value in one period of the current signal, and if yes, the number of the high-frequency detection pulse signals is recorded as 1 parallel arc.

Further, the control unit judges whether the number of detected parallel type arcs is greater than or equal to a second set value in a predetermined number of consecutive cycles, and if so, determines that a parallel type fault arc is detected.

Further, the second threshold is 2, and the third threshold is 2.

Further, the high-frequency component detection circuit includes: second electric capacity, second full-bridge rectifier circuit, third electric capacity and fifth resistance, wherein, the one end of second electric capacity is connected the first output pin of current transformer's secondary coil, the other end is connected to the first end of second full-bridge rectifier circuit, the second output pin of current transformer's secondary coil is connected to the third end of second full-bridge rectifier circuit, the second end ground connection of second full-bridge rectifier circuit, the fourth end of second full-bridge rectifier circuit with third electric capacity one end the first end of fifth resistance with the third input end of control unit links together, the third electric capacity other end with the second end of fifth resistance is all ground connection.

Further, the current transformer is made of a high-permeability magnetic core material.

Further, still include: the leakage detection circuit is used for detecting a current signal of a protected circuit, converting the current value of the current signal into a voltage value and inputting the voltage value into the control unit; the control unit obtains a plurality of voltage values and calculates to obtain a voltage average value, judges whether the voltage average value is larger than a leakage set value or not, and determines that the ground fault arc is detected if the voltage average value is larger than the leakage set value.

Further, still include: the test circuit is used for generating a test current in the protected circuit so as to determine whether the protected circuit is disconnected by the protection circuit when the protected circuit leaks.

Further, still include: and the reset circuit is used for sending a reset signal to the control unit, wherein the control unit carries out reset operation after receiving the reset signal.

Further, still include: the protection circuit is used for disconnecting the protected circuit when receiving the circuit-breaking control signal output by the control unit; wherein the control unit sends a trip control signal to the protection circuit when it is determined that a fault arc is detected; and the power supply circuit is used for supplying power to the control unit and the zero-crossing detection circuit.

According to a second aspect of the present invention, there is provided a fault arc protection method comprising: sampling a current signal of a protected circuit to obtain a pulse signal of a detection circuit; when the current value of the current signal is detected to be zero, generating a trigger electric signal; and periodically analyzing the detection circuit pulse signal to detect the fault arc based on the trigger electric signal.

Further, the method comprises the following steps: and counting the pulse signals of the detection circuit after receiving the trigger electric signal, and recording as 1 series arc when the number of the pulse signals of the detection circuit detected in one period of the current signal is greater than or equal to a first threshold value.

Further, whether the number of the detected series type arcs in the continuous preset number of periods is larger than or equal to a first set value or not is judged, and if yes, the series type fault arcs are determined to be detected.

Further, the method comprises the following steps: if two detection circuit pulse signals which are low and high are detected in a half period of the current signal, the occurrence of the series type arc in the protected circuit is determined.

Further, the first threshold value is 4.

Further, the method comprises the following steps: sampling high-frequency harmonic components in the current signal of the protected circuit to obtain a high-frequency detection pulse signal; and counting the high-frequency detection pulse signals after receiving the trigger electric signal, and judging whether the number of the high-frequency detection pulse signals is smaller than a second threshold value and whether the number of the detection circuit pulse signals is equal to a third threshold value in one period of the current signal, wherein if yes, the number is marked as 1 parallel arc.

Further, whether the number of parallel type arcs detected in a predetermined number of consecutive periods is greater than or equal to a second set value is judged, and if yes, it is determined that a parallel type fault arc is detected.

Further, the second threshold is 2, and the third threshold is 2.

Further, the method comprises the following steps: detecting a current signal of a protected circuit, and converting a current value of the current signal into a voltage value; and obtaining a plurality of voltage values, calculating to obtain a voltage average value, judging whether the voltage average value is larger than a leakage set value, and if so, determining that the ground fault arc is detected.

In the invention, a pulse detection circuit samples a current signal of a protected circuit to obtain a detection circuit pulse signal, and the detection circuit pulse signal is sent to a control unit; when the zero-crossing detection circuit detects that the current value of the current signal is zero, a trigger electric signal is sent to the control unit; the control unit periodically analyzes the detection circuit pulse signal based on the trigger electric signal to detect a fault arc. The fault arc protection device can shorten the judgment time, improve the response speed and be more reliable and effective for fault arc protection.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

fig. 1 is a schematic structural view showing a fault arc protection device according to an embodiment of the present invention.

Fig. 2A is a graph illustrating pulse signals detected by a fault arc protection device according to an embodiment of the present invention when no string-type arc occurs in a protected circuit.

Fig. 2B is a graph illustrating pulse signals detected by the arc fault protection device when a string arc occurs in the protected circuit in accordance with an embodiment of the present invention.

Fig. 3A is a pulse signal diagram illustrating the detection of a good arc in a protected circuit by a fault arc protection device according to an embodiment of the present invention.

Fig. 3B is a pulse signal diagram illustrating the detection of a good arc in the protected circuit by the fault arc protection device in accordance with an embodiment of the present invention.

Fig. 4 is a circuit schematic diagram illustrating a power circuit in a fault arc protection device according to an embodiment of the present invention.

Fig. 5 is a circuit schematic diagram illustrating a control unit in the fault arc protection device according to an embodiment of the present invention.

Fig. 6 is a circuit schematic diagram illustrating a protection circuit in the fault arc protection device according to an embodiment of the present invention.

Fig. 7 is a circuit schematic diagram showing a pulse detection circuit and a high-frequency component detection circuit in the fault arc protection device according to the embodiment of the present invention.

Fig. 8 is a circuit schematic diagram illustrating a zero-crossing detection circuit in a fault arc protection device according to an embodiment of the invention.

Fig. 9 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention.

Fig. 10 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention.

Fig. 11 is a circuit schematic diagram illustrating a leakage detection circuit in a fault arc protection device according to further embodiments of the present invention.

Fig. 12 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention.

Fig. 13 is a circuit schematic illustrating a test circuit in a fault arc protection device according to further embodiments of the present invention.

Fig. 14 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention.

Fig. 15 is a circuit schematic illustrating a reset circuit in a fault arc protection device according to further embodiments of the present invention.

Fig. 16 is a flow chart illustrating a fault arc protection method according to an embodiment of the present invention.

Fig. 17 is a flow chart illustrating a fault arc protection method according to further embodiments of the present invention.

FIG. 18 is a flow chart illustrating a fault arc protection method according to further embodiments of the present invention.

FIG. 19 is a flow chart illustrating a fault arc protection method according to further embodiments of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Fig. 1 is a schematic structural view showing a fault arc protection device according to an embodiment of the present invention. As shown in fig. 1, the fault arc protection device 10 includes: a control unit 200, a pulse detection circuit 400, and a zero-crossing detection circuit 500, and for illustrative purposes, a power supply circuit 100 and a protection circuit 300 are also shown in fig. 1. Wherein,

the output end of the pulse detection circuit 400 is electrically connected to the first input end of the control unit 200, and the pulse detection circuit 400 is configured to sample a current signal of a protected circuit to obtain a detection circuit pulse signal, and send the detection circuit pulse signal to the control unit 200;

the output end of the zero-crossing detection circuit 500 is electrically connected to the second input end of the control unit 200, and the zero-crossing detection circuit 500 is configured to send a trigger electrical signal to the control unit 200 when detecting that the current value of the current signal is zero;

the control unit 200 periodically analyzes the detection circuit pulse signal based on the trigger electric signal to detect a fault arc.

In the embodiment, a pulse detection circuit samples a current signal of a protected circuit to obtain a detection circuit pulse signal, and the detection circuit pulse signal is sent to a control unit; when the zero-crossing detection circuit detects that the current value of the current signal is zero, a trigger electric signal is sent to the control unit; the control unit periodically analyzes the detection circuit pulse signal based on the trigger electric signal to detect a fault arc. The fault arc protection device of the embodiment can shorten the judgment time, improve the response speed and ensure that the fault arc protection is more reliable and effective.

In the embodiment of the present invention, the control unit 200 starts counting the detection circuit pulse signals after receiving the trigger electrical signal, and when the number of the detection circuit pulse signals detected in one period of the current signal is greater than or equal to a first threshold (e.g. 4), it is recorded as 1 serial arc. In another embodiment, the control unit (200) determines whether the number of detected string arcs is greater than or equal to a first set value (e.g., 3) for a predetermined number (e.g., 3) of consecutive cycles, and if so, determines that a string fault arc is detected. Because the control unit judges the time sequence position of the pulse signal of the detection circuit according to the triggering of the zero-crossing detection circuit, the judgment time can be shortened, the response speed is improved, and the fault arc protection is more reliable and effective.

In the embodiment of the present invention, if the control unit 200 detects two detection circuit pulse signals that are one low and one high in a half cycle of the current signal, it is determined that the string arc occurs in the protected circuit.

In an embodiment of the invention, the arc fault protection device further comprises: a protection circuit 300 electrically connected to the control unit 200, for disconnecting the protected circuit when receiving a disconnection control signal outputted from the control unit 200; wherein the control unit 200 transmits a disconnection control signal to the protection circuit 300 when it is determined that a fault arc (e.g., a string-type fault arc) is detected.

In an embodiment of the invention, the arc fault protection device further comprises: and a power circuit 100 electrically connected to the control unit 200 and the zero-crossing detection circuit 500, for supplying power to the control unit 200 and the zero-crossing detection circuit 500.

When a series arc occurs in a protected circuit, transient equal values can occur on a sine wave of a current, if the transient equal value phenomenon occurs, the pulse detection circuit can sample two pulse waveforms (shown in fig. 2B) which respectively have a certain amplitude, are lower than one and higher than one and have intervals therebetween in a half period, and when no series arc exists, only one pulse waveform (shown in fig. 2A) with a certain amplitude can be sampled in a half period. However, the detection of a pulse signal as shown in fig. 2B is not necessarily due to a fault arc, but may be due to a good arc or other noise source. Fig. 3A and 3B show graphs of pulse signals detected when a good arc occurs in a protected circuit. As can be seen from fig. 3A and 3B, although two pulse waveforms each having a certain amplitude, one lower and one higher, and a space therebetween are detected, the arc is not a fault arc. For example, normally actuated relays and ac contactors produce a series arc when activated.

Therefore, in detecting whether a series fault arc occurs in the protected circuit, the control unit needs to further determine, for example, the control unit 200 acquires the detection circuit pulse signal, counts the detection circuit pulse signal when receiving the trigger electrical signal, records as 1 series arc when the number of detection circuit pulse signals detected in one period of the current signal is greater than or equal to a first threshold (e.g., 4), determines whether the number of series arcs detected in a predetermined number of consecutive periods is greater than or equal to a first set value, and if so, determines that a series fault arc is detected, and outputs a disconnection control signal to the protection circuit 300, so that the protection circuit disconnects the protected circuit. For example, 3 consecutive cycles may be selected as the predetermined number of consecutive cycles, and the first set value may be 3. This is due to, for example, the fact that normally-actuated relays and ac contactors produce a series arc when actuated, requiring 2 cycles to avoid the normal arc current waveform characteristics. Of course, it will be understood by those skilled in the art that the number of the above-mentioned predetermined number of cycles and the first setting value can be set according to different needs, and are not limited to the above-mentioned examples.

Circuit connection diagrams of the power supply circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, and the zero-cross detection circuit 500 are illustrated below, respectively. Of course, it should be understood by those skilled in the art that the following examples of the various circuits are merely exemplary, and that other circuits may be employed by those skilled in the art, and thus the scope of the present invention is not limited to the following examples.

Fig. 4 is a circuit schematic diagram illustrating a power circuit in a fault arc protection device according to an embodiment of the present invention. As shown in fig. 4, the circuit connection relationship of the power supply circuit 100 includes: 2 and 1 of the terminal X001 of the power circuit 100 are respectively connected with an L line (live line) and an N line (neutral line) of 220V alternating current, and the L line and the N line are also connected with a piezoresistor Z1 (for example, the piezoresistor specification is 471K, namely the surge operating voltage is 470V), a ceramic chip capacitor C0 (for example, the capacitor specification is 472K/1kV) and a resistor R0 through 2 and 1 of the terminal X001; and the L line is connected with the pin 1 at the input end of the rectifier bridge BG1 through two resistors R1 (for example, 47k omega) and R4 (for example, 47k omega) which are connected in parallel, and the N line is connected with the pin 2 at the input end of the rectifier bridge BG 1. The output end 3 pin of the rectifier bridge BG1 is connected with the anode of an electrolytic capacitor C1 (for example, the capacitance value 47 μ F, the maximum carrying voltage 25V), the first end of a capacitor discharge resistor R5 (for example, the resistance value 1M Ω (mega ohm)), the cathode of a zener diode D1 (for example, the regulated voltage 12V), the first end of a current limiting resistor R6 (for example, 10k Ω), the first end of a current limiting resistor R7 (for example, 3.3k Ω), and the first end of a current limiting resistor R27 (for example, 5.1k Ω); the pin 4 at the output end of the rectifier bridge BG1, the negative electrode of the electrolytic capacitor C1, the second end of the capacitor discharge resistor R5, and the anodes of the zener diode D1, the zener diode D2 and the zener diode D3 are grounded respectively. The output terminal 3 pin of the rectifier bridge BG1 can provide +12V power. In addition, the +12V power supply is connected to the cathode of the zener diode D3 via a current limiting resistor R7, which may provide a positive power supply VCC to a control unit (not shown in fig. 4), for example. The second end of the current limiting resistor R6 may be connected to the anode of the led D7 to provide power to the led D7, the cathode of the led D7 is grounded, and the led D7 may be used as a power indicator. Other units or circuits may be powered by the power supply circuit shown in fig. 4. Of course, it should be understood by those skilled in the art that the power supply circuit shown in FIG. 4 is merely exemplary, and that other power supply circuits may be used with the present invention, and thus the scope of the present invention is not limited in this respect.

Fig. 5 is a circuit schematic diagram illustrating a control unit in the fault arc protection device according to an embodiment of the present invention. As shown in fig. 5, pin 1 of the control unit 200 is connected to VCC (for example, VCC connected to the power supply circuit 100 shown in fig. 4, and powered by the power supply circuit), pin 14 is grounded, and other pins may be used as input terminals or output terminals, for example, pin 5P 1.3 may be used as a first input terminal of the control unit and connected to an output terminal of the pulse detection circuit; the 6-pin P1.4 can be used as a second input end of the control unit and is connected with the output end of the zero-crossing detection circuit; the 2-pin P1.0 can be used as the output end of the control unit and is connected with the input end of the protection circuit. In addition, there are other pins, which will be described later in the relevant description. The control unit may be, for example, a microprocessor of the model MSP430F 2012. Of course, those skilled in the art will appreciate that the present invention may also be used with other types or styles of control units, and the scope of the present invention is not limited in this respect.

Fig. 6 is a circuit schematic diagram illustrating a protection circuit in the fault arc protection device according to an embodiment of the present invention. As shown in fig. 6, the circuit connection relationship of the protection circuit 300 includes: a first terminal of the resistor R19 (e.g. with a resistance value of 1k omega) is connected to pin 2 (P1.0) of the control unit 200 shown in figure 5, a second terminal of which is commonly connected to the gate (g-pole) of thyristor 302 (e.g. thyristor BT168GW) and one terminal of chip capacitor C13 (e.g. capacitor 223pF), the cathode (k pole) of the thyristor 302 and the other end of the chip capacitor C13 are both connected to zero, the anode (a-pole) of the thyristor 302 is connected to one end of the trip coil of the trip unit 301, the other end of the trip coil of the trip unit 301 is connected to the L-line (i.e., live line), in fig. 4 the contact terminals TK _ L and TK _ N are shown (the middle dashed line represents both linkages), which when pressed down, contacting the terminals M and N respectively, that is, the other end of the trip coil of the trip unit 301 is connected to the L line, and the cathode (k pole) of the thyristor 302 and the other end of the chip capacitor C13 are both connected to the zero line. In another embodiment, the other end of the trip coil of the trip unit 301 may be connected to the cathode of a diode (not shown in fig. 6) whose anode is connected to the L line shown in fig. 4.

The working principle of the protection circuit is as follows: the control unit outputs a circuit breaking control signal (such as a trigger spike), the circuit breaking control signal is transmitted to the thyristor element 302 through the resistor R19, the thyristor element 302 is triggered to be conducted, a circuit loop of a tripping coil of the tripper 301 is connected, direct current flows through the tripping coil, and a tripper action mechanism acts to enable the tripper to complete tripping and tripping, and a power supply of a load carried by the tripper is cut off, so that the protected circuit is protected.

Fig. 7 is a circuit schematic diagram showing a pulse detection circuit and a high-frequency component detection circuit in the fault arc protection device according to the embodiment of the present invention. Fig. 7 shows the pulse detection circuit 400 and the high-frequency component detection circuit 600, and description about the high-frequency component detection circuit 600 will be explained later, where the circuit connection relationship of the pulse detection circuit 400 is explained first.

In an embodiment of the present invention, the pulse detection circuit 400 includes: a current transformer 401, a first resistor R22 (e.g., having a resistance value of 1k Ω), a second resistor R17 (e.g., having a resistance value of 470 Ω), a first full-bridge rectifier circuit 402 (e.g., a full-bridge rectifier circuit composed of four diodes D40, D41, D42, D43 as shown in fig. 7), and a first capacitor C10 (e.g., a capacitance value of 104 pF); the first output pin Y1 of the secondary coil of the current transformer 401 is connected to the first end of the first resistor R22, the second end of the first resistor R22 is connected to the first end of the first full-bridge rectifier circuit 402, the second output pin Y2 of the secondary coil of the current transformer 401 is connected to the third end of the first full-bridge rectifier circuit 402, the second end of the first full-bridge rectifier circuit 402 is grounded, the fourth end of the first full-bridge rectifier circuit 402 is connected to the first end of the second resistor R17, the second end of the second resistor R17 is grounded, the first end of the second resistor R17 can be connected to the first input terminal P1.3 of the control unit 200, and one end of the first capacitor C10 is connected to the first end of the second resistor R17 and the other end is grounded.

In this embodiment, for example, the live wire in the protected circuit may pass through a central hole of the current transformer 401, and the current transformer generates an induced current in the secondary coil due to a change in current in the live wire, so that the pulse detection circuit may detect a current signal of the protected circuit, sample the detected circuit pulse signal and input the detected circuit pulse signal to the control unit. In this embodiment, since the full-bridge rectifier circuit is used, the number of times of signal processing time can be increased, which is advantageous for shortening the detection time. Of course, it will be appreciated by those skilled in the art that other rectifier circuits, such as half-wave rectifier circuits, may be used, and the scope of the present invention is not limited in this respect.

In the embodiment of the invention, the current transformer can adopt a current transformer made of a high-permeability magnetic core material. For example, a current transformer having a magnetic core material with an inductance of more than 200mH (millihenry) may be used.

In another embodiment, as shown in fig. 7, the pulse detection circuit 400 further includes: a third resistor R18 (e.g., a resistor value of 1k Ω), a fourth resistor R21 (e.g., a resistor value of 10k Ω), and a first zener diode D8 (e.g., a zener value of 2.7V), wherein a first end of the second resistor R17 is connected to a first end of the third resistor R18, a second end of the third resistor R18 is connected in common with a first end of the fourth resistor R21, a cathode of the first zener diode D8, and a first input end P1.3 of the control unit 200 (not shown in fig. 7), and a second end of the fourth resistor R21 and an anode of the first zener diode D8 are both grounded.

The third resistor R18 and the fourth resistor R21 form a matching resistor of the pulse detection circuit 400, the third resistor R18 performs current limiting and voltage dividing, and the fourth resistor R21 performs voltage dividing and pull-down. By arranging the first voltage regulator tube D8, the damage of the control unit caused by the fact that the sampling voltage exceeds the bearing range of the control unit 200 can be avoided.

Fig. 8 is a circuit schematic diagram illustrating a zero-crossing detection circuit in a fault arc protection device according to an embodiment of the invention. As shown in fig. 8, the circuit connection relationship of the zero-crossing detection circuit 500 includes: the zero-crossing detection circuit 500 obtains an alternating-current signal from the power supply circuit 100, and is connected to a 3 pin of an inverting input end of an integrated operational amplifier U4 (such as model LM 392-N) through resistors R50 (such as a resistor value 1M omega), R51 (such as a resistor value 5.1k omega) and R52 (such as a resistor value 5.1k omega) which are connected IN series, the 3 pin is connected to a +5V power supply of the power supply circuit 100 through a resistor R54 (such as a resistor value 100k omega), a connection end of a resistor R51 and a resistor R52 is connected to a cathode of a diode D51 (such as model IN 4148), and an anode of the diode D51 is grounded; the 1 pin of the non-inverting input terminal of the integrated operational amplifier U4 is connected to one ends of resistors R53 (for example, 100k Ω), R56 (for example, 20k Ω), and R57 (for example, 10k Ω), the other end of the resistor R53 is connected to the +5V power supply of the power supply circuit 100, the other end of the resistor R57 is grounded, the other end of the resistor R56 is connected to one ends of the 4 pins of the output terminal of the integrated operational amplifier U4, the resistor R55 (for example, 5.1k Ω), and R59 (for example, 1k Ω), the other end of the resistor R59 is connected to the cathode of the zener diode D9 (for example, 2.7V) and the 6 pins (i.e., P1.4) of the second input terminal of the control unit 200, the other end of the resistor R55 is connected to the +5V power supply of the power supply circuit 100, and the anode of the zener diode D9 and the 2 pin of the integrated operational amplifier.

In this embodiment, the zero-crossing detection circuit may detect a period of a current signal of the protected circuit, and when detecting that a current value of the current signal is zero, transmit a trigger electrical signal to the control unit so that a detection circuit pulse signal received from the pulse detection circuit starts counting when the trigger electrical signal is received. The zero-crossing detection circuit can be used for triggering interruption, carrying out A/D conversion, determining the time sequence positions of two pulse waveforms which respectively have certain amplitude values, are lower than one and higher than one and have intervals in a half period, and improving the efficiency and the anti-interference capability of detecting the fault arc.

Fig. 9 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention. As shown in fig. 9, the arc fault protection device 20 includes: a power supply circuit 100, a control unit 200, a protection circuit 300, a pulse detection circuit 400, a zero-cross detection circuit 500, and a high-frequency component detection circuit 600. The power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, and the zero-crossing detection circuit 500 are similar to the power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, and the zero-crossing detection circuit 500 shown in fig. 1, respectively, and are not described herein again.

An output end of the high-frequency component detection circuit 600 is electrically connected to a third input end of the control unit 200 (for example, a 4-pin P1.2 of the control unit shown in fig. 5), and the high-frequency component detection circuit 600 is configured to detect a high-frequency harmonic component in a current signal of the circuit to be protected, sample the high-frequency harmonic component to obtain a high-frequency detection pulse signal, and input the high-frequency detection pulse signal to the control unit 200; the control unit 200 starts counting the high frequency detection pulse signals after receiving the trigger electrical signal, and determines whether the number of high frequency detection pulse signals is less than a second threshold (e.g., 2) and the number of detection circuit pulse signals is equal to a third threshold (e.g., 2) in one cycle of the current signal, and if so, the number is recorded as 1 parallel arc. In another embodiment, the control unit 200 determines whether the number of detected parallel type arcs is greater than or equal to a second set value (e.g., 3) for a predetermined number (e.g., 3) of consecutive cycles, and if so, determines that a parallel type fault arc is detected.

In this embodiment, a high-frequency detection pulse signal is transmitted to the control unit through the high-frequency component detection circuit, the control unit compares the high-frequency detection pulse signal received from the high-frequency component detection circuit with the detection circuit pulse signal received from the pulse detection circuit, determines whether the number of high-frequency detection pulse signals is less than a second threshold (e.g., 2) and the number of detection circuit pulse signals is equal to a third threshold (e.g., 2) in one cycle of the current signal, and if so, it is written as 1 parallel arc, and determines that a parallel fault arc is detected when the number of parallel arcs detected in a predetermined number (e.g., 3) of consecutive cycles is greater than or equal to a second set value (e.g., 3). Further, the control unit outputs a disconnection control signal to the protection circuit 300 when it is determined that the parallel type fault arc is detected.

This embodiment can be used to detect a parallel fault arc, and its operating principle is: when parallel type electric arcs appear in a protected circuit, the pulse detection circuit detects current signals and obtains 1 pulse signal in a half cycle (namely, the pulse signal of the detection circuit is distinguished from two pulse waveforms which have certain amplitude, are lower than one and higher than one and have intervals when series type electric arcs appear), so that the pulse detection circuit can detect 2 pulse signals in one cycle; in the high-frequency component detection circuit, since the high-current magnetic field has a suppression effect on the high-frequency pulse signal, the number of pulse signals (i.e., high-frequency detection pulse signals) detected by the high-frequency component detection circuit is reduced, for example, 1 pulse signal or 0 pulse signal is detected in one cycle; the control unit judges whether the number of the high-frequency detection pulse signals is less than 2 in one period of the current signal and whether the number of the detection circuit pulse signals is equal to 2, if yes, the number is recorded as 1 parallel arc, and since the occurrence of the parallel arc is not necessarily just a fault arc, the control unit needs to judge whether the number of the parallel arcs detected in a predetermined number (for example, 3) of continuous periods is greater than or equal to a second set value (for example, 3), and if yes, the parallel fault arc is determined to be detected. Further, the control unit outputs a disconnection control signal to the protection circuit to disconnect the protected circuit.

As for the circuit connection relationship of the high-frequency component detection circuit, reference may be made to the high-frequency component detection circuit 600 shown in fig. 7. As shown in fig. 7, the high-frequency component detection circuit 600 includes: a second capacitor C11 (e.g. a capacitance value of 104pF), a second full-bridge rectifier circuit 603 (e.g. a full-bridge rectifier circuit composed of four diodes D60, D61, D62, D63 as shown in fig. 7), a third capacitor C12 (e.g. a capacitance value of 104pF), and a fifth resistor R20 (e.g. a resistance value of 33k Ω), wherein one end of the second capacitor C11 is connected to a first output pin Y1 of a secondary coil of a current transformer 401 (e.g. a current transformer of a high-permeability core material), the other end is connected to a first end of the second full-bridge rectifier circuit 603, a second output pin Y2 of the secondary coil of the current transformer 401 is connected to a third end of the second full-bridge rectifier circuit 603, a second end of the second full-bridge rectifier circuit 603 is grounded, a fourth end of the second full-bridge rectifier circuit 603 is connected to a first end of the third capacitor C12, a first end of the fifth resistor R20, and a third input end of the control unit 200 (e.g. a 4- The other end of the third capacitor C12 and the second end of the fifth resistor R20 are both grounded.

In this embodiment, since the full-bridge rectifier circuit is used, the number of times of signal processing time can be increased, which is advantageous for shortening the detection time. Of course, it will be appreciated by those skilled in the art that other rectifier circuits, such as half-wave rectifier circuits, may be used, and the scope of the present invention is not limited in this respect.

Fig. 10 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention. As shown in fig. 10, the arc fault protection device 30 includes: the power supply circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, and the leakage detection circuit 700. The power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, and the high-frequency component detection circuit 600 are similar to the power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, and the high-frequency component detection circuit 600 shown in fig. 9, respectively, and are not described herein again.

An output end of the leakage detection circuit 700 is electrically connected to a fourth input end of the control unit 200 (for example, pin 3P 1.1 of the control unit 200 shown in fig. 5), and the leakage detection circuit 700 is configured to detect a current signal of a protected circuit, convert a current value of the current signal into a voltage value, and input the voltage value to the control unit 200, where the control unit 200 obtains a plurality of voltage values and calculates a voltage average value (i.e., an average value of the plurality of voltage values), determines whether the voltage average value is greater than a leakage set value (for example, 1.1V), and if so, determines that a ground fault arc is detected. This embodiment may be used to perform leakage detection (i.e., detect ground fault arcs). Further, the control unit outputs a disconnection control signal to the protection circuit 300 when it is determined that the ground fault arc is detected. In another embodiment, the power circuit 100 is electrically connected to the leakage detecting circuit 700 to supply power to the leakage detecting circuit 700.

In the embodiment of the present invention, a current limit value a (for example, 5mA, 10mA, 30mA, 75mA, etc.) of a ground arc of the leakage detection circuit may be set, when a ground arc occurs in a protected circuit and a current value of the ground arc is greater than or equal to the current limit value a, an output end of the leakage detection circuit provides a voltage value b (for example, 1.1V) of a dc signal sampled and processed by the control unit 200, the control unit 200 obtains a plurality of voltage values and calculates a voltage average value, determines whether the voltage average value is greater than a leakage set value, if so, determines that a ground fault arc is detected, and outputs a disconnection control signal to the protection circuit 300 to disconnect the protected circuit.

In order to make the fault arc protection device respond more quickly in the embodiment of the present invention, two control units may be provided in the fault arc protection device of the embodiment of the present invention, one for detecting the ground fault arc and the other for detecting the series fault arc and the parallel fault arc. Because the two control units are respectively used for detecting different fault arcs, the operation speed is improved, and the response speed of the fault arc protection device can be improved.

A circuit connection relationship of the electrical leakage detection circuit 700 is described below with reference to fig. 11.

Fig. 11 is a circuit schematic diagram illustrating a leakage detection circuit in a fault arc protection device according to further embodiments of the present invention. As shown in fig. 11, the circuit connection relationship of the leakage detecting circuit 700 includes: the X002 terminals 5 and 6 of the leakage detection circuit 700 are respectively connected to two output pins of a zero sequence current transformer (not shown IN fig. 11), the pin of the zero sequence current transformer connected to the X002 terminal 6 is further connected to one end of a capacitor C30 (for example, a capacitance value of 104pF), one end of a resistor R30(10k Ω), a cathode of a diode D30 (for example, IN 4148), an anode of a diode D31 (for example, IN 4148), a pin 1 of an integrated operational amplifier U3, one end of a resistor R33 (for example, a resistance value of 10k Ω), one end of a resistor R35 (for example, a resistance value of 20M Ω), and one end of a resistor R36 (for example, a resistance value of 10k Ω); and a pin of the zero sequence current transformer connected with the X002 terminal 5 is also connected with the other end of the capacitor C30, the other end of the resistor R30, an anode of the diode D30, a cathode of the diode D31 and a pin 3 of the integrated operational amplifier U3 in common. The power circuit 100 provides +12V to the 5 pin of the integrated operational amplifier U3, the 2 pin of the integrated operational amplifier U3 is connected to ground (e.g., to a dc power ground), the 4 pin of the integrated operational amplifier U3 is connected to +5V of the power circuit via a resistor R34 (e.g., having a resistance of 3k Ω), the 4 pins of U3 are also commonly connected to the other end of R35, one end of a chip capacitor C7 (e.g., a capacitance of 104pF), and the anode of an electrolytic capacitor C8 (e.g., a capacitance of 47 μ F, a maximum carrying voltage of 25V), the other end of a resistor R33 is connected to +5V, the cathode of an electrolytic capacitor C8 is commonly connected to one end of a resistor R14 (e.g., a resistance of 33k Ω) and the anode of a diode D5 (e.g., model IN 4148), the cathode of the diode D5 is commonly connected to one end of a chip capacitor C9 (e.g., a capacitance of 105pF), one end of a resistor R15 (a resistance of 1.5M Ω), the cathode of a zener diode D10 (e.g., a zener diode of 2.7V), and the 3 pin (i.e., P1.1) of the control unit 200; the other end of the resistor R36, the other end of the chip capacitor C7, the other end of the resistor R14, the other end of the chip capacitor C9 and the other end of the resistor R15 are commonly connected to the anode of the zener diode D10 and grounded.

After signal processing by the leakage detection circuit 700, a dc voltage signal that can be sampled and processed by the control unit 200 is output to the 3 pins of the control unit, the control unit calculates the voltage average value as described above, and determines whether the voltage average value is greater than a leakage set value, if so, it is determined that leakage occurs in the protected circuit (i.e., there is a ground fault arc), and outputs a disconnection control signal to the protection circuit 300 to disconnect the protected circuit.

Fig. 12 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention. As shown in fig. 10, the arc fault protection device 40 includes: the power supply circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, the leakage detection circuit 700, and the test circuit 800. The power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, and the leakage detection circuit 700 are similar to the power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, and the leakage detection circuit 700 shown in fig. 10, respectively, and are not described herein again.

The test circuit 800 is used for generating a test current in the protected circuit to determine whether the protection circuit 300 disconnects the protected circuit when the protected circuit leaks.

One circuit connection relationship of the test circuit 800 is described below in conjunction with fig. 13.

Fig. 13 is a circuit schematic illustrating a test circuit in a fault arc protection device according to further embodiments of the present invention. As shown in fig. 13, the circuit connection relationship of the test circuit 800 includes: one end of the key switch S1 of the test circuit 800 is connected to an N line (i.e., a zero line), the other end is connected to one end of a resistor R9 (e.g., a resistance value of 11k Ω), and the other end of the resistor R9 is connected to an L line (i.e., a live line) after passing through a zero-sequence current transformer (not shown in fig. 13) of the leakage detection circuit 700 (e.g., after passing through a primary coil of the zero-sequence current transformer for three cycles), where the N line and the L line are respectively connected to 1 and 2 of the terminal X001 of the power circuit 100. Of course, when the wire is threaded around the primary coil of the zero sequence current transformer, the wire may also be threaded around other number of turns, which may be determined according to actual situations.

In this embodiment, when the key switch S1 is pressed, a current with a current value I (for example, a current greater than 15mA, such as 20mA or 30mA) flows through the same one turn of the primary coil of the zero sequence current transformer to verify the action of leakage protection, and if the protection circuit opens the protected circuit, it is determined that the leakage detection circuit can detect leakage (i.e., a ground arc).

Fig. 14 is a schematic diagram illustrating a configuration of a fault arc protection device according to further embodiments of the present invention. As shown in fig. 14, the arc fault protection device 50 includes: the power supply circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, the leakage detection circuit 700, the test circuit 800, and the reset circuit 900. The power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, the leakage detection circuit 700, and the test circuit 800 are similar to the power circuit 100, the control unit 200, the protection circuit 300, the pulse detection circuit 400, the zero-crossing detection circuit 500, the high-frequency component detection circuit 600, the leakage detection circuit 700, and the test circuit 800 shown in fig. 12, respectively, and are not described herein again.

An output end of the reset circuit 900 is electrically connected to a reset end of the control unit 200, and is configured to send a reset signal to the control unit 200, where the control unit 200 performs a reset operation after receiving the reset signal.

One circuit connection relationship of the reset circuit 900 is described below with reference to fig. 15.

Fig. 15 is a circuit schematic illustrating a reset circuit in a fault arc protection device according to further embodiments of the present invention. As shown in fig. 15, the circuit connection relationship of the reset circuit 900 includes: a pin 3 of the reset unit U2 (e.g., TLV803 model) is connected to the dc power VCC of the power circuit 100, a pin 2 of the reset unit U2 is connected to a pin 10 (i.e., reset terminal/RST) of the control unit 200, and a pin 3 and a pin 2 of the reset unit U2 are connected through a resistor R8 (e.g., a resistance value of 100k Ω). Pin 1 of reset unit U2 is connected to ground (e.g., dc ground).

In this embodiment, the reset power supply U2 outputs a reset signal to the control unit via pin 10 (i.e.,/RST) via pin 2, and the control unit performs a reset operation upon receiving the reset signal.

In an embodiment of the present invention, the arc fault protection device may further include: and the fault indicating element is electrically connected with the control unit and is used for indicating whether a fault arc occurs in the protected circuit or not. Specifically, the fault indication element may be connected to the 7-pin (i.e., P1.5), 8-pin (i.e., P1.6), and 9-pin (i.e., P1.7) of the control unit, respectively, and may detect whether the 7-pin, 8-pin, and 9-pin outputs of the control unit are high or low, respectively. For example, when the control unit detects a ground fault arc (i.e., detects a leakage), the P1.5 output terminal outputs a high level to the fault indicating element, and when there is no ground fault arc, the P1.5 output terminal outputs a low level to the fault indicating element; when the control unit detects parallel fault arcs, the output end of the P1.6 outputs high level to the fault indication element, and outputs low level to the fault indication element when no parallel fault arcs exist; when the control unit detects the series fault arc, the output end of the P1.7 outputs high level to the fault indication element, and outputs low level to the fault indication element when no series fault arc exists. As another example, the fault indicating element may include three indicator lights (e.g., the indicator light is illuminated at a high level and not illuminated at a low level), and the three indicator lights may be respectively connected to the pins 7 (i.e., P1.5), 8 (i.e., P1.6) and 9 (i.e., P1.7) of the control unit to respectively indicate whether a corresponding fault arc is detected.

In step S1601, a current signal of the protected circuit is sampled to obtain a detection circuit pulse signal.

In step S1602, when it is detected that the current value of the current signal is zero, a trigger electrical signal is generated.

In step S1603, the detection circuit pulse signal is periodically analyzed based on the trigger electrical signal to detect a fault arc.

In the embodiment, a current signal of a protected circuit is sampled to obtain a pulse signal of a detection circuit; when the current value of the current signal is detected to be zero, generating a trigger electric signal; based on the trigger electric signal, the detection circuit pulse signal is periodically analyzed to detect the fault arc, so that the judgment time can be shortened, the response speed is improved, and the fault arc protection is more reliable and effective.

In another embodiment, when it is determined that a fault arc is detected, a trip control signal is sent to the protection circuit, which upon receiving the trip control signal, trips the protected circuit.

In an embodiment of the invention, the fault arc protection method comprises: counting the detection circuit pulse signals after receiving the trigger electric signal, and recording as 1 series arc when the number of the detection circuit pulse signals detected in one period of the current signal is larger than or equal to a first threshold (for example, 4). In another embodiment, it is determined whether the number of detected string arcs is greater than or equal to a first set value (e.g., 3) for a predetermined number (e.g., 3) of consecutive cycles, and if so, it is determined that a string fault arc is detected. The time sequence position of the pulse signal of the detection circuit can be judged according to the triggering of the triggering electric signal, so that the judgment time can be shortened, the response speed can be improved, and the fault arc protection is more reliable and effective.

In an embodiment of the invention, the fault arc protection method comprises: if two detection circuit pulse signals which are low and high are detected in a half period of the current signal, the occurrence of the series type arc in the protected circuit is determined.

In an embodiment of the invention, the fault arc protection method comprises: sampling high-frequency harmonic components in a current signal of a protected circuit to obtain a high-frequency detection pulse signal; and counting the high-frequency detection pulse signals after receiving the trigger electric signal, and judging whether the number of the high-frequency detection pulse signals is smaller than a second threshold (for example, 2) and whether the number of the detection circuit pulse signals is equal to a third threshold (for example, 2) in one period of the current signal, and if so, recording as 1 parallel arc. In another embodiment, it is determined whether the number of detected parallel type arcs is greater than or equal to a second set value (e.g., 3) for a predetermined number (e.g., 3) of consecutive cycles, and if so, it is determined that a parallel type fault arc is detected.

In an embodiment of the invention, the fault arc protection method comprises: detecting a current signal of a protected circuit, and converting a current value of the current signal into a voltage value; obtaining a plurality of voltage values, calculating to obtain a voltage average value (namely the average value of the voltage values), judging whether the voltage average value is larger than a leakage set value, and if so, determining that the ground fault arc is detected.

In step S1701, the control unit initializes.

In step S1702, the trip pulls in.

In step S1703, it is determined whether a fault arc has occurred. If so, the process proceeds to step S1704, otherwise, the process proceeds to step S1705. In another embodiment, a delay time (e.g., 1 second) may also be set for the control unit before determining whether a fault arc is occurring, which may facilitate more stable operation of the control unit.

In step S1704, the trip unit trips. I.e. opens the protected circuit.

In step S1705, it is determined whether the time counter is equal to 0. Determining whether a time counter (e.g., a 3ms counter) is equal to 0 may serve as a determination condition for detecting a series-type fault arc or a parallel-type fault arc. If so, the process proceeds to step S1706, i.e., a parallel fault arc is detected, otherwise the process proceeds to step S1707, i.e., a series fault arc is detected.

In step S1706, parallel fault arc detection. The parallel fault arc is detected by the number of pulses detected by the P1.3 input and the P1.2 input of the control unit. For example, the voltage at the P1.3 input terminal of the control unit is greater than 200mV, and 1 is added to the counter CNT1, that is, 1 detection circuit pulse signal is detected; p1.2 detecting that the port voltage is greater than 200mV, the counter CNT2 increments by 1, that is, 1 high frequency detection pulse signal is detected, the control unit determines whether the number of high frequency detection pulse signals is less than a second threshold (e.g., 2) and the number of detection circuit pulse signals is equal to a third threshold (e.g., 2) within one cycle of the current signal, and if so, it is recorded as 1 parallel arc, and if the number of parallel arcs detected in a predetermined number of consecutive cycles is greater than or equal to a second set value, it is determined that a parallel fault arc is detected.

In step S1707, a string fault arc is detected. The number of pulse signals of the detection circuit is detected through the P1.3 input end of the control unit to detect the series fault arc. For example, the voltage at the P1.3 input terminal of the control unit is greater than 200mV, the counter CNT1 adds 1, 1 detection circuit pulse signal is detected, when a string-type arc occurs, the obtained pulse signal has two pulse waveforms with a certain amplitude, one lower and one higher, and an interval therebetween in a half cycle, so the control unit judges that the number of detected string-type arcs in one cycle of the current signal is greater than or equal to a first threshold (for example, 4), if so, it is recorded as 1 string-type arc, and if the number of detected string-type arcs in a predetermined number of consecutive cycles is greater than or equal to a first set value, it is determined that a string-type fault arc is detected.

In step S1708, whether the average value of the voltages of the leakage detection is greater than the leakage set value is determined. If so, the procedure proceeds to step S1709, otherwise, the procedure proceeds to step S1710.

In step S1709, it is determined that a leakage fault occurs, and the trip unit trips.

In step S1710, a failure is indicated. For example, for a ground fault arc: when the ground fault electric arc occurs, the P1.5 output end of the control unit outputs a high level, and when the ground fault electric arc does not exist, the low level is output; for parallel fault arcs: when parallel fault arcs occur, the P1.6 output end of the control unit outputs high level, and when no parallel fault arcs exist, low level is output; for a string fault arc: when the series type fault electric arc occurs, the P1.7 output end of the control unit outputs high level, and when no series type fault electric arc exists, the low level is output.

In the embodiment, three fault arcs are respectively detected, so that the protected circuit is safer, and the detection effect is better.

In step S1801, a zero-crossing detection interrupt enters. Namely, the trigger electric signal of the zero-crossing detection circuit is input to the control unit.

In step S1802, the voltage half-cycle count V _ CNT is incremented by 1. Wherein the voltage half-cycle count V _ CNT is incremented by 1 every half-cycle count.

In step S1803, a time counter is set. For example, a 3ms counter is provided, which may be provided since the arc pulse typically occurs in the first quarter of a cycle (about 5 ms).

In step S1804, it is determined whether the voltage half-cycle count V _ CNT is equal to 2. I.e. whether a cycle has elapsed. If so, the process proceeds to step S1805, otherwise returns until the voltage half-cycle count V _ CNT equals 2.

In step S1805, it is determined whether the P1.2 pulse counter CNT2 is less than 2 and the P1.3 pulse counter CNT1 is equal to 2. Here, the P1.2 pulse counter CNT2 is a pulse counter that counts a high frequency detection pulse signal received from a P1.2 input terminal of the control unit, and the P1.3 pulse counter CNT1 is a pulse counter that counts a detection circuit pulse signal received from a P1.3 input terminal of the control unit. If so, the process advances to step S1807, otherwise, the process advances to step S1806.

In step S1806, the parallel fault counter is cleared.

In step S1807, the parallel fault counter is incremented by 1.

In step S1808, it is determined whether the P1.3 pulse counter is greater than or equal to 4. If so, the process proceeds to step S1810, otherwise, the process proceeds to step S1809.

In step S1809, the string fault counter is cleared.

In step S1810, the string fault counter is incremented by 1.

In step S1811, it is determined whether the parallel fault counter is greater than or equal to a second set value. If so, the process proceeds to step S1812, otherwise, the process proceeds to step S1813.

In step S1812, a parallel fault arc is determined and the trip unit trips.

In step S1813, it is determined whether the string fault counter is greater than or equal to a first set value. If so, the process proceeds to step S1814, otherwise, the process proceeds to step 1815.

In step S1814, a string fault arc is determined and the trip unit trips.

In step S1815, the P1.2 pulse counter CNT2 is equal to 0, the P1.3 pulse counter CNT1 is equal to 0, and the voltage half-cycle count V _ CNT is equal to 0. Namely, the P1.2 pulse counter CNT2, the P1.3 pulse counter CNT1 and the voltage half-cycle count V _ CNT are cleared to cyclically detect the next fault arc.

In step S1901, the leakage sample is a/D converted, and the leakage sample a/D conversion count is incremented by 1.

In step S1902, it is determined whether the number of a/D conversions of the leakage current sample is less than a set number of times (e.g., 50 times). If so, the process proceeds to step S1904, otherwise, the process proceeds to step S1903.

In step S1903, the voltage average value is calculated and the number of times is cleared.

In step S1904, the leakage sample a/D conversion values are accumulated.

In step S1905, it is determined whether the voltage average value is greater than the leakage setting value. If so, the process proceeds to step S1906, otherwise return, i.e., re-detect the leakage fault.

In step S1906, an electrical leakage fault is determined. I.e., it is determined that a ground fault arc is detected.

In another embodiment of the present invention, it may be further determined whether the detectable leakage flag is 1 before step S1901, that is, whether leakage detection is possible, if so, step S1901 is performed, otherwise, processing is performed so that the detectable leakage flag is 1.

Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

The method and system of the present invention may be implemented in a number of ways. For example, the methods and systems of the present invention may be implemented in software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustrative purposes only, and the steps of the method of the present invention are not limited to the order specifically described above unless specifically indicated otherwise. Furthermore, in some embodiments, the present invention may also be embodied as a program recorded in a recording medium, the program including machine-readable instructions for implementing a method according to the present invention. Thus, the present invention also covers a recording medium storing a program for executing the method according to the present invention.

Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A fault arc protection device, comprising:

the pulse detection circuit (400) is used for sampling a current signal of a protected circuit to obtain a detection circuit pulse signal and sending the detection circuit pulse signal to the control unit (200);

the zero-crossing detection circuit (500) is used for sending a trigger electric signal to the control unit (200) when the current value of the current signal is detected to be zero;

a control unit (200) that periodically analyzes the detection circuit pulse signal based on the trigger electrical signal to detect a fault arc;

the control unit (200) starts counting the detection circuit pulse signals after receiving the trigger electric signal, and when the number of the detection circuit pulse signals detected in one period of the current signal is greater than or equal to a first threshold value, the number is marked as 1 serial arc; if the control unit (200) detects two detection circuit pulse signals which are low and high within a half period of the current signal, determining that the series type electric arc occurs in the protected circuit;

the control unit (200) determines whether the number of detected series arcs is greater than or equal to a first set value in a predetermined number of consecutive cycles, and if so, determines that a series fault arc is detected.

2. The arc fault protection device of claim 1, wherein the first threshold is 4.

3. The arc fault protection device of claim 1, wherein the pulse detection circuit (400) comprises: the circuit comprises a current transformer (401), a first resistor (R22), a second resistor (R17), a first full-bridge rectifying circuit (402) and a first capacitor (C10); wherein,

a first output pin of a secondary coil of the current transformer (401) is connected to a first end of the first resistor (R22), a second terminal of the first resistor (R22) is connected to a first terminal of the first full-bridge rectifier circuit (402), a second output pin of the secondary coil of the current transformer (401) is connected to a third end of the first full-bridge rectification circuit (402), a second terminal of the first full-bridge rectification circuit (402) is grounded, a fourth terminal of the first full-bridge rectification circuit (402) is connected to a first terminal of the second resistor (R17), a second terminal of the second resistor (R17) is grounded, and a first terminal of the second resistor (R17) is connected to a first input terminal (P1.3) of the control unit (200), one end of the first capacitor (C10) is connected to the first end of the second resistor (R17), and the other end is grounded.

4. The arc fault protection device of claim 3, wherein the pulse detection circuit (400) further comprises: a third resistor (R18), a fourth resistor (R21), and a first zener diode (D8), wherein,

the first end of the second resistor (R17) is connected to the first end of the third resistor (R18), the second end of the third resistor (R18) is connected to the first end of the fourth resistor (R21), the cathode of the first zener diode (D8) and the first input end (P1.3) of the control unit (200), and the second end of the fourth resistor (R21) and the anode of the first zener diode (D8) are both grounded.

5. The arc fault protection device of claim 3 or 4, further comprising:

a high-frequency component detection circuit (600) for detecting a high-frequency harmonic component in the current signal of the protected circuit, sampling the high-frequency harmonic component to obtain a high-frequency detection pulse signal, and inputting the high-frequency detection pulse signal to the control unit (200);

the control unit (200) starts counting the high-frequency detection pulse signals after receiving the trigger electric signal, judges whether the number of the high-frequency detection pulse signals is smaller than a second threshold value in one period of the current signal, judges whether the number of the detection circuit pulse signals is equal to a third threshold value, and records the number as 1 parallel arc if the number of the high-frequency detection pulse signals is equal to the third threshold value.

6. The arc fault protection device of claim 5,

the control unit (200) judges whether the number of detected parallel type arcs in a predetermined number of consecutive periods is greater than or equal to a second set value, and if so, determines that a parallel type fault arc is detected.

7. The arc fault protection device of claim 5, wherein the second threshold is 2 and the third threshold is 2.

8. The arc fault protection device according to claim 5, wherein the high frequency component detection circuit (600) comprises: a second capacitor (C11), a second full-bridge rectifier circuit (603), a third capacitor (C12) and a fifth resistor (R20), wherein,

one end of the second capacitor (C11) is connected with a first output pin of a secondary coil of the current transformer (401), the other end of the second capacitor is connected with a first end of the second full-bridge rectifying circuit (603), a second output pin of the secondary coil of the current transformer (401) is connected with a third end of the second full-bridge rectifying circuit (603), a second end of the second full-bridge rectifying circuit (603) is grounded, a fourth end of the second full-bridge rectifying circuit (603) is connected with one end of the third capacitor (C12), a first end of the fifth resistor (R20) and a third input end (P1.2) of the control unit (200) in a common mode, and the other end of the third capacitor (C12) and a second end of the fifth resistor (R20) are both grounded.

9. The arc fault protection device according to claim 8, wherein the current transformer (401) is a current transformer of high permeability core material.

10. The arc fault protection device of claim 1, further comprising:

a leakage detection circuit (700) for detecting a current signal of a protected circuit, converting a current value of the current signal into a voltage value, and inputting the voltage value to the control unit (200);

the control unit (200) obtains a plurality of voltage values and calculates to obtain a voltage average value, judges whether the voltage average value is larger than a leakage set value or not, and determines that the ground fault arc is detected if the voltage average value is larger than the leakage set value.

11. The arc fault protection device of claim 10, further comprising:

the protection circuit comprises a test circuit (800) and a control circuit, wherein the test circuit is used for generating a test current in the protected circuit so as to determine whether the protection circuit (300) opens the protected circuit when the protected circuit generates electric leakage.

12. The arc fault protection device of claim 1, further comprising:

a reset circuit (900) for sending a reset signal to the control unit (200),

wherein the control unit (200) performs a reset operation upon receiving the reset signal.

13. The arc fault protection device of claim 1, further comprising:

a protection circuit (300) which, upon receiving a disconnection control signal output by the control unit (200), disconnects the protected circuit; wherein the control unit (200) sends a trip control signal to the protection circuit (300) when it is determined that a fault arc is detected;

a power supply circuit (100) for supplying power to the control unit (200) and the zero-crossing detection circuit (500).

14. A method of fault arc protection, comprising:

sampling a current signal of a protected circuit to obtain a pulse signal of a detection circuit;

when the current value of the current signal is detected to be zero, generating a trigger electric signal;

periodically analyzing the detection circuit pulse signal to detect a fault arc based on the trigger electrical signal;

counting the detection circuit pulse signals after receiving the trigger electric signals, and recording as 1 series arc when the number of the detection circuit pulse signals detected in one period of the current signals is greater than or equal to a first threshold value; if two detection circuit pulse signals which are low and high are detected in a half period of the current signal, determining that the series type electric arc occurs in the protected circuit;

and judging whether the number of the detected series type arcs in the continuous preset number of periods is larger than or equal to a first set value, and if so, determining that the series type fault arcs are detected.

15. The method of fault arc protection according to claim 14, wherein the first threshold is 4.

16. The fault arc protection method of claim 14, comprising:

sampling high-frequency harmonic components in the current signal of the protected circuit to obtain a high-frequency detection pulse signal;

and counting the high-frequency detection pulse signals after receiving the trigger electric signal, and judging whether the number of the high-frequency detection pulse signals is smaller than a second threshold value and whether the number of the detection circuit pulse signals is equal to a third threshold value in one period of the current signal, wherein if yes, the number is marked as 1 parallel arc.

17. The method for fault arc protection according to claim 16,

and judging whether the number of the detected parallel type arcs in a preset number of continuous periods is greater than or equal to a second set value, and if so, determining that the parallel type fault arcs are detected.

18. The method of fault arc protection according to claim 16, wherein the second threshold is 2 and the third threshold is 2.

19. The fault arc protection method of claim 14, comprising:

detecting a current signal of a protected circuit, and converting a current value of the current signal into a voltage value;

and obtaining a plurality of voltage values, calculating to obtain a voltage average value, judging whether the voltage average value is larger than a leakage set value, and if so, determining that the ground fault arc is detected.