CN104465809B - Double-face growing silicon-based four-junction solar cell - Google Patents

Abstract

The invention discloses a double-face growing silicon-based four-junction solar cell which comprises a Si sub cell serving as a substrate, a GaAsxP1-x sub cell, a GaInxP1-x sub cell and a Ge sub cell located on the lower surface of the substrate, wherein the GaAsxP1-x sub cell and the GaInxP1-x sub cell are located on the upper surface of the substrate. The GaAsxP1-x sub cell and the GaInxP1-x sub cell are connected with the Si sub cell through a GaAsxP1-x component gradient buffer layer. The Ge sub cell is connected with the Si sub cell through a SixGel-x component gradient buffer layer. The GaAsxP1-x sub cell is connected with the GaInxP1-x sub cell through a tunnel junction. The GaAsxP1-x sub cell is connected with the Si sub cell through a tunnel junction. The Si sub cell is connected with the Ge sub cell through a tunnel junction. According to the double-face growing silicon-based four-junction solar cell, the cascaded four-junction solar cell is prepared through the Si substrate, band gaps are combined at the voltage about 1.95/1.5/1.12/0.67 eV, and the cost can be reduced while the photoelectric conversion efficiency of the cell is improved.

Description

A silicon-based four-junction solar cell grown on both sides

technical field

The invention relates to the technical field of solar photovoltaics, in particular to a silicon-based four-junction solar cell grown on both sides.

Background technique

Currently, lattice-matched GaAs multi-junction solar cells are widely used in concentrated photovoltaic (CPV) systems and space power systems because their conversion efficiency is significantly higher than that of crystalline silicon cells. The mainstream structure of gallium arsenide multi-junction solar cells is a triple-junction solar cell composed of GaInP, GaInAs and Ge sub-cells. The cell structure maintains lattice matching, and the band gap combination is around 1.85/1.40/0.67eV. In addition, in order to obtain higher efficiency, some multi-junction solar cells are grown with lattice-mismatched materials, such as GaInP/GaInAs/Ge cells with amorphous structure, in order to compensate for the stress and material quality caused by lattice mismatch and other issues, by growing a composition graded GaInAs buffer layer on the Ge substrate, and increasing the In composition in GaInP and GaInAs cells to achieve a bandgap combination of 1.8/1.3/0.67eV. In addition, there are some institutions that grow two GaInAs cells with different compositions on the GaAs substrate, and connect them with two composition graded buffer layers to achieve a bandgap combination of 1.85/1.3/0.9eV.

So far, the above batteries have made some breakthroughs in terms of efficiency, reaching 40% or even higher levels. However, when this type of battery is applied to a cost-sensitive ground concentrating power station, its high cost often increases the cost of the concentrating power station and reduces its competitiveness. One of the main reasons for the high cost of Ge-based and GaAs-based multi-junction cells is that the content of Ge or Ga and As used in the substrate is very small in the earth's crust, and it is difficult to directly extract and process, so the cost is high, making only the substrate. It accounts for 1/3 to 1/2 of the battery cost, which is not conducive to the large-scale promotion and utilization of multi-junction batteries.

The silicon substrate has a very obvious cost advantage due to decades of development and large-scale production in the IC industry and the photovoltaic industry, and has been widely accepted by the consumer goods and energy markets. However, crystalline silicon cells are directly made from Si, since the lattice constant of silicon is with GaAs series of There is a lattice mismatch of 4%, and it has only appeared in the single-junction cell structure. Due to the limitation of the number of cell junctions and absorption spectrum, its theoretical efficiency is only 27%, while the actual product efficiency of crystalline silicon single-junction cells has been 15% The ~20% range is hovering, and it is difficult to further improve.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies and shortcomings of the prior art, to provide a silicon-based quadruple-junction solar cell grown on both sides, and to grow Ge cells and GaAs on both sides of the Si cell as the substrate through a composition gradient buffer layer. The _x P _1-x /Ga _x In _1-x P battery can not only effectively improve the photoelectric conversion efficiency of the battery, but also make full use of the cost advantage of silicon, and has a good industrialization prospect.

In order to achieve the above object, the technical solution provided by the present invention is: a silicon-based four-junction solar cell grown on both sides, including a Si sub-cell as a substrate, and the upper surface of the Si sub-cell is stacked according to a layered structure. GaIn _x P _1-x sub-cells, GaAs _x P _1-x sub-cells, and GaAs _x P _1-x composition gradient buffer layers are arranged in sequence from top to bottom; the lower surface of the Si sub-cells is stacked in layers The structure is provided with a Six Ge _1-x composition graded buffer layer and a Ge sub-cell in sequence from top to bottom; wherein, the GaIn _x P _{1-x sub} -cell and the GaAs _x P _1-x sub-cell are connected by a third Tunnel junction connection, the GaAs _x P _1-x sub-cell and the Si sub-cell are connected through a second tunnel junction located on the GaAs _x P _1-x composition graded buffer layer, the Si sub-cell and the Ge sub-cell are connected The batteries are connected through the first tunnel junction located on the Si _x Ge _1-x composition gradient buffer layer; the GaIn _x P _1-x sub-cells and the GaAs _x P _1-x sub-cells are lattice-matched.

The internal structure of the GaIn _x P _1-x subcell includes, from top to bottom, a lattice-matched n-type AlGaInP or AlInP window layer, an n-type GaIn _x P _1-x emission region, and a p-type GaIn _x P ₁ -x _x base region, p-type AlGaInP or AlInP back field layer; wherein, in the GaIn _x P _1-x sub-cell, the value of x is in the range of 0.5 to 0.65, and the corresponding GaIn _x P _1-x material band gap is 1.85 eV to 2.05eV range.

The internal structure of the GaAs _x P _1-x subcell includes, from top to bottom, a lattice-matched n-type GaInP window layer, an n-type GaInP or GaAs _x P _1-x emitter, and a p-type GaAs _x P ₁ -x _x base region, p-type GaInP back field layer; wherein, in the GaIn _x P _1-x subcell, the value of x is in the range of 0.85 to 1, corresponding to the band gap of the GaAs _x P _1-x material in the range of 1.42eV to 1.6eV within the range.

The GaAs _x P _1-x composition graded buffer layer has an x value that gradually changes from 1 to 0 from top to bottom, and the corresponding lattice constant gradually changes from matching GaAs _x P _1-x to matching Si, that is is in interval gradient.

The Si _x Ge _1-x composition graded buffer layer has an x value that gradually changes from 1 to 0 from top to bottom, and the corresponding lattice constant gradually changes from matching GaAs _x P _1-x to matching Si, that is, is in interval gradient.

The Si sub-cell includes a window layer, an n-type P diffusion layer, a p-type layer, and a back field layer sequentially from top to bottom, and needs to be polished on both sides before being used as a substrate.

The Ge sub-cell includes a window layer, an n-type layer, a p-type layer, and a back field layer sequentially from top to bottom.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

Using Si sub-cells as double-sided substrates, and introducing composition graded buffer layers, GaIn _x P _1-x and GaAs _x P _1-x sub-cells are set on the Si substrate, and strips are set under the Si substrate. A Ge sub-cell with a gap of about 0.67eV can finally be obtained with a GaIn _x P _1-x /GaAs _x P _1-x /Si/Ge four-junction cell with a bandgap structure of about 1.95/1.5/1.12/0.67eV, which can not only meet The optimal bandgap combination of the four-junction cell under the solar spectrum is expected to obtain higher cell efficiency, and can also significantly reduce the manufacturing cost of the cell, creating conditions for the wide application of high-efficiency cells.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a silicon-based four-junction solar cell grown on both sides according to the present invention.

detailed description

The present invention will be further described below in conjunction with specific examples.

As shown in Figure 1, the silicon-based four-junction solar cell grown on both sides described in this embodiment includes a Si sub-cell as a substrate, and the upper surface of the Si sub-cell is stacked from top to bottom according to a layered superposition structure. A GaIn _x P _1-x sub-cell, a GaAs _x P _1-x sub-cell, and a GaAs _x P _1-x composition graded buffer layer are sequentially arranged on the bottom, and the lower surface of the Si sub-cell is layered from the top to the bottom. The six Ge _1-x composition graded buffer layer and the Ge sub-cell are arranged in sequence from the bottom; the GaIn _x P _{1-x sub} -cell and the GaAs _x P _1-x sub-cell are connected through a third tunnel junction, so The GaAs _x P _1-x sub-cell and the Si sub-cell are connected through a second tunnel junction located on the GaAs _x P _1-x composition graded buffer layer, and the Si sub-cell and the Ge sub-cell are connected by a The first tunnel junction connection on the Si _x Ge _1-x composition graded buffer layer; the GaIn _x P _1-x sub-cell and the GaAs _x P _1-x sub-cell are lattice-matched.

The Si sub-cell includes a window layer, an n-type P diffusion layer, a p-type layer, and a back field layer in order from top to bottom, and needs to be polished on both sides before being used as a substrate.

The internal structure of the GaIn _x P _1-x subcell includes, from top to bottom, a lattice-matched n-type AlGaInP or AlInP window layer (in this embodiment, an n-type AlGaInP window layer is specifically selected), and an n-type GaIn _x P _1-x emission region, p-type GaIn _x P _1-x base area, p-type AlGaInP or AlInP back field layer (in this embodiment, specifically select p-type AlGaInP back field layer); wherein, the GaIn _x In the P _1-x sub-cell, the value of x is in the range of 0.5 to 0.65, corresponding to the GaIn _x P _1-x material band gap in the range of 1.85eV to 2.05eV, and in this embodiment, the value of x is 0.59, corresponding to GaIn The band gap of _x P _1-x material is about 1.95eV, and the lattice constant is about 5.62.

The internal structure of the GaAs _x P _1-x sub-cell includes, from top to bottom, a lattice-matched n-type GaInP window layer, an n-type GaInP or GaAs _x P _1-x emission region (in this embodiment, specifically Select n-type GaInP), p-type GaAs _x P _1-x base region, and p-type GaInP back field layer; wherein, in the GaIn _x P _1-x sub-cell, the value of x is in the range of 0.85 to 1, corresponding to GaAs _x The bandgap of the P _1-x material is in the range of 1.42eV to 1.6eV, and in this embodiment, the value of x is 0.85, corresponding to the bandgap of the GaAs _x P _1-x material is about 1.59eV, and the lattice constant is about 5.62. Lattice matched to GaIn _x P _1-x subcells.

The GaAs _x P _1-x composition graded buffer layer has an x value that gradually changes from 1 to 0 from top to bottom, and the corresponding lattice constant gradually changes from matching GaAs _x P _1-x to matching Si, that is is in Gradual change in the interval, keep x=0 to grow 2um GaP after the gradual change is completed, as the window layer of the Si sub-cell, and play the role of nucleation transition.

The Si _x Ge _1-x composition graded buffer layer has an x value that gradually changes from 1 to 0 from top to bottom, and the corresponding lattice constant gradually changes from matching GaAs _x P _1-x to matching Si, that is, is in interval gradient.

The Ge sub-cell includes a window layer, an n-type layer, a p-type layer, and a back field layer sequentially from top to bottom.

The following is the specific preparation process of the above-mentioned double-sided silicon-based four-junction solar cell in this embodiment, and the situation is as follows:

First, a double-sided polished 4-inch p-type Si single wafer is subjected to front-side P diffusion to form an n-type layer and initially form a Si sub-cell; then metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE ) grow GaAs _x P _1-x composition graded buffer layer, second tunnel junction, GaAs _x P _1-x sub-cell, third tunnel junction and GaIn _x P ₁ -x sequentially on the upper surface of Si sub-cell as substrate _x sub-cell; finally, the substrate is turned over 180°, and then the Si _x Ge _1-x composition graded buffer layer and Ge sub-cell are sequentially grown on the lower surface of the Si sub-cell as the substrate, and the double-sided growth of silicon can be completed. Fabrication of base four-junction solar cells.

In summary, the present invention utilizes a Si substrate to prepare a cascaded four-junction cell, and introduces a composition graded buffer layer, and GaIn _x P _1-x and GaAs _x P _1-x sub-cells are arranged on the Si substrate , a Ge subcell with a bandgap of about 0.67eV is set under the Si substrate, and finally GaIn _x P _1-x /GaAs _x P _1-x /Si with a bandgap structure of about 1.95/1.5/1.12/0.67eV can be obtained /Ge four-junction battery, which not only meets the best bandgap combination of four-junction batteries under the solar spectrum, is expected to obtain higher battery efficiency, but also significantly reduces the manufacturing cost of the battery, creating conditions for the wide application of high-efficiency batteries. , is worth promoting.

The implementation examples described above are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all changes made according to the shape and principle of the present invention should be covered within the scope of protection of the present invention.

Claims (3)

1. a kind of silicon substrate four-junction solar battery of two-sided growth, including as substrate si battery it is characterised in that: described The upper surface of si battery is disposed with gain from top to bottom according to stratiform overlaying structure_xp_1-xSub- battery, gaas_xp_1-xSon electricity Pond, gaas_xp_1-xComponent-gradient buffer layer；Described si battery lower surface according to stratiform overlaying structure from top to bottom successively It is provided with si_xge_1-xComponent-gradient buffer layer and ge battery；Wherein, described gain_xp_1-xSub- battery and gaas_xp_1-xSub- battery Between by the 3rd tunnel knot connect, described gaas_xp_1-xBy positioned at gaas between sub- battery and si battery_xp_1-xComponent is gradually Become the second tunnel knot on cushion to connect, by positioned at si between described si battery and ge battery_xge_1-xComponent is gradually Become the first tunnel knot on cushion to connect；Described gain_xp_1-xSub- battery and gaas_xp_1-xSub- battery Lattice Matching；Described gain_xp_1-xThe internal structure of sub- battery includes N-shaped algainp or the alinp Window layer of Lattice Matching, n from top to bottom successively Type gain_xp_1-xLaunch site, p-type gain_xp_1-xBase, p-type algainp or alinp back surface field layer；Wherein, described gain_xp_1-xSon electricity Chi Zhong, x value, in 0.5～0.65 interval, corresponds to gain_xp_1-xMaterial band gap is in 1.85ev～2.05ev interval；Described gaas_xp_1-xThe internal structure of sub- battery includes the N-shaped gainp Window layer of Lattice Matching from top to bottom successively, N-shaped gainp or gaas_xp_1-xLaunch site, p-type gaas_xp_1-xBase, p-type gainp back surface field layer；Wherein, described gain_xp_1-xIn sub- battery, x value exists 0.85～1 is interval interior, corresponding gaas_xp_1-xMaterial band gap is in 1.42ev～1.6ev interval；Described gaas_xp_1-xContent gradually variational delays Rush layer, its x value is in 1～0 interval gradual change from top to bottom, corresponding lattice paprmeter from gaas_xp_1-xCoupling fades to and si Join, be alsoInterval gradual change；Described si_xge_1-xComponent-gradient buffer layer, from top to bottom its x value 1～ 0 interval gradual change, corresponding lattice paprmeter from gaas_xp_1-xCoupling fade to mate with si, be alsoArea Between gradual change.

2. a kind of two-sided growth according to claim 1 silicon substrate four-junction solar battery it is characterised in that: described si electricity Pond includes Window layer, N-shaped p diffusion layer, p-type layer, back surface field layer from top to bottom successively.

3. a kind of two-sided growth according to claim 1 silicon substrate four-junction solar battery it is characterised in that: described ge electricity Pond includes Window layer, n-layer, p-type layer, back surface field layer from top to bottom successively.