CN104465581A - Low-cost and high-reliability chip size CIS packaging structure - Google Patents

Abstract

The invention discloses a low-cost and high-reliability chip size CIS package, which belongs to the field of semiconductor packages. The package structure includes: 1. a cover plate, a cavity structure is made on the front of the cover plate; 2. a wafer, which includes a front side of the wafer and a back side of the wafer; 3. functional areas and pads are distributed on the front side of the wafer , where the pads are distributed around the function and realize conduction; 4. The bonding glue is located between the cover plate and the wafer, and the two are bonded together; 5. A passivation layer is sequentially fabricated on the back of the wafer , the metal layer, and the solder resist layer, through the redistribution circuit layer composed of the above structure, conduction between the pad and the solder ball is realized; 7. The solder ball is located on the redistribution circuit layer. The invention reduces the stress in the structure while reducing the thickness of the packaging structure. Secondly, by using the solder mask to wrap the metal layer at the edge, the yield rate of cutting is improved. Finally, the bonding force and stability of the metal layer and the pad are enhanced, and the structural reliability is improved.

Description

A Low Cost High Reliability Chip Size CIS Package

technical field

The invention relates to a low-cost and high-reliability chip size CIS package, which belongs to the field of semiconductor packages. It can be preferably used in CIS, MEMS devices or integrated chips, etc.

Background technique

With the rapid development of the personal consumer electronics industry, notebook computers, smart phones, etc. are becoming more and more portable and functional. In addition, in order to meet the popularization of products, low-cost, high-density, high-reliability packaging forms of electronic products are also important development directions. As a new generation of chip packaging technology, chip size packaging (CSP) can make the ratio of chip area to package area exceed 1:1.14, which is quite close to the ideal situation of 1:1, which is about the same as that of ordinary ball grid array package (BGA). 1/3, which is only equivalent to 1/6 of the area of a thin small outline package (TSOP) memory chip. Compared with BGA, CSP can increase the storage capacity by three times under the same space. The purpose of CSP is to use high-density chips (chips with more functions, better performance, and more complex chips) to replace previous chips, and the package body occupies the same or smaller area of the printed board. It is precisely because of the small and thin CSP package that it has rapidly gained application in portable mobile electronic devices. CSP not only significantly reduces the size of the package, reduces the cost of packaging, improves the packaging efficiency, but also meets the requirements of high-density packaging; at the same time, due to the short data transmission path and high stability, this package can reduce energy consumption. It also improves the speed and stability of data transmission.

However, in the current CSP packaging products, especially for CIS (CMOS image sensor), MEMS devices and integrated chips and other packaging types, there are still many problems that affect product reliability:

1. In order to form an airtight cavity structure 100c between the cover plate 100 and the wafer 102, a method of covering the front surface 102a of the wafer with a layer of cover plate 100 is usually used, by making a bonding effect between the two, And have supporting walls of a certain thickness to achieve this. The selected support wall materials are generally polymer materials. Since the thermal expansion coefficients of the cover plate 100, the wafer 102, and the support wall are quite different, the mismatch of thermal expansion coefficients will lead to thermal stress. As a result, the packaging structure is prone to delamination and cracks between the support wall and the cover plate 100 and the wafer 102 in the subsequent reliability test and service, which will lead to the degradation or even failure of the device function; in addition, because the support walls have a certain height , thereby increasing the overall thickness of the packaging structure, which affects the final dimensions of the product, especially in the direction of thickness.

2. In the existing packaging process, the redistribution circuit layer containing the metal layer 106 is usually fabricated on the entire surface of the wafer back 102b, and then the wafer 102 is cut to form individual chips. Since the area to be cut contains a variety of materials with different hardness, such as redistribution circuit layer, silicon, polymer, cover plate 100, etc., this poses a great challenge to the cutting process, and it is easy to generate fragments, splits and other phenomena. On the other hand, during the subsequent service of the packaged product, since the metal layer 106 is in direct contact with the outside world around the package structure, once delamination occurs between the interfaces, it is easy to introduce moisture from the external environment into the package structure. , resulting in accelerated failure of the device.

3. Some of the existing CIS packages are based on Through-Silicon Via (TSV) technology. By making TSVs on the wafer 102, the pads 104 on the front side of the wafer 102a are connected to the back side of the wafer 102b. Through-silicon via technology, as a technology that realizes vertical interconnection by making vertical conduction between chips and wafers, is considered to be an important way to realize three-dimensional packaging. It has many advantages at the same time: small size, low power consumption, high packaging density, excellent high-frequency characteristics, shortest interconnection between chips, and so on. However, through-silicon via technology is also facing severe challenges. First, its cost has remained high. Secondly, in terms of manufacturing processes, such as etching, plating and filling of through-silicon vias, there are complex processes and low product yields. Condition. For TSVs with high aspect ratios, the challenges are even more severe.

Therefore, it is very necessary to develop a low-cost and high-reliability chip-size CIS packaging structure and a manufacturing method thereof.

Contents of the invention

The first aspect of the present invention is to provide a low-cost and high-reliability chip-size CIS packaging structure. The encapsulation structure implemented by the present invention: firstly, since no support wall with a certain thickness is used, the thickness of the encapsulation structure is reduced. Second, the stress caused by thermal mismatch between different materials can be reduced. The finite element calculation results show that, compared with the traditional structure using support walls, the packaging structure of the present invention has a higher density at the interface between the cover plate 100 and the wafer 102. The stress has a decrease of about 30%. In this way, failures such as interface delamination and cracks can be improved. Third, by wrapping the metal layer 106 with the solder resist layer 107, the types of materials that need to be removed during the cutting process are reduced, which not only improves the cutting process yield, but also enhances the reliability of the package; fourth, compared with the high cost According to the TSV process, the present invention does not need to make TSVs on the wafer 102 to conduct the pad 104 to the backside 102b of the wafer, thereby realizing high-reliability packaging at a lower cost and process threshold.

In order to achieve the above object, the present invention adopts the following technical solutions:

The low-cost and high-reliability chip-size CIS packaging structure implemented by the present invention includes: a cover plate 100, and a cavity structure 100c is made on the front surface 100a of the cover plate; a wafer 102; a functional area is prefabricated on the front surface 102a of the wafer 103 and pad 104; bonding glue 101, by coating a layer of bonding glue 101 on the front surface 100a of the cover plate, bonding the front surface 100a of the cover plate with the front surface 102a of the wafer; redistribution circuit layer, on the back side of the wafer The passivation layer 105, the metal layer 106, and the solder resist layer 107 are sequentially formed on the 102b. Through the redistribution circuit layer composed of the above structure, the pads 104 on the front side of the wafer 102a are connected to the solder balls 108 on the back side of the wafer 102b.

The metal layer 106 extends from the back side of the wafer 102b to the front side of the cover plate 100a, and at the same time, the edge of the wafer 102 is wrapped by the solder resist layer 107 without direct contact with the outside world.

The connection method between the pads 104 on the front side of the wafer 102a and the solder balls 108 on the back side of the wafer 102b is as follows: first, expose the sides of the pads 104; then connect the metal layer 106 to the sides of the pads 104 ; Finally, the conduction between the pad 104 and the solder ball 108 is realized by forming the solder ball 108 on the metal layer 106 .

Optionally, the chip may be a CIS (CMOS Image Sensor) chip, MEMSIC or integrated chip.

Optionally, the pads 104 are distributed around the edges of the functional area 103 and are pre-conducted with the functional area 103 in the center of the wafer.

Optionally, the material of the cover plate 100 may be transparent materials such as glass, quartz, and plastic.

Optionally, the cavity structure 100c is located in the center of the front surface 100a of the cover plate, just above the functional area 103; and the cross section of the cavity structure 100c may be circular or square.

A second aspect of the present invention provides a method for preparing the low-cost and high-reliability chip-size CIS packaging structure, comprising the following steps:

Step 1, making the cover plate 100: making a cavity structure 100c on the front surface 100a of the cover plate;

Step 2, wafer 102 bonding: use a bonding machine to bond the front surface 100a of the cover plate with the front surface 102a of the wafer, thereby forming a closed cavity between the cover plate 100 and the wafer 102;

Step 3, wafer 102 thinning: the thinning process is carried out in two steps: first, the wafer back 102b is ground by a grinder, and the wafer 102 is thinned to a set thickness; then, the thinned wafer The round back 102b is subjected to stress-relief plasma etching;

Step 4, silicon removal: the silicon removal process is carried out in three steps. First, remove the silicon around the backside 102b of the wafer to expose the pads 104 on the front side 102a of the wafer; secondly, on the backside 102b of the wafer, including the exposed A passivation layer 105 is coated on the surface of the pad 104; finally, the area around the wafer 102, including part of the passivation layer 105, silicon, part of the pad 104 and part of the bonding glue 101 is removed again, and the part of the pad 104 The side and part of the front surface 100a of the cover are exposed;

Step 5, making the metal layer 106 and the solder resist layer 107 on the back side of the wafer 102b in turn, so as to conduct the pad 104 to the preset position of the solder ball 108 on the back side of the wafer 102b;

Step 6, making solder balls 108: form solder balls 108 on the redistribution circuit layer of the wafer backside 102b, and then cut the periphery of the wafer 102 to form a single chip package.

The redistribution layer on the wafer backside 102 b includes a passivation layer 105 , a metal layer 106 and a solder resist layer 107 .

Optionally, the front surface 100a of the cover plate is bonded to the front surface 102a of the wafer using a bonding glue 101, and the bonding glue 101 is a resin adhesive.

Optionally, the silicon removal method may use a dry etching process of plasma etching, including deep reactive ion etching (DRIE).

Optionally, the silicon removal method may use a wet etching process including a silicon etchant.

Optionally, the silicon removal method may be formed by direct cutting with a V-cut knife (V-groove knife).

Optionally, the two removal steps in the silicon removal step can be completed by combining any two of the three methods: dry etching process, wet etching process, and V-cut knife cutting.

Optionally, the thickness of the outermost solder resist layer 107 is no more than 1.5 times the thickness of the passivation layer 105, so as to reduce the stress between different material interfaces.

Compared with the prior art, through the implementation of the patent of the present invention, the beneficial effects are:

1. By making the cavity structure 100c on the cover plate 100, the support wall structure required when the cover plate 100 and the wafer 102 are bonded in the traditional package structure is omitted, and the overall thickness of the package structure is reduced, realizing Miniaturization and ultra-thinning of the packaging structure.

2. The present invention does not adopt the traditional support wall structure, which can reduce the stress caused by thermal mismatch between different materials in the structure. The calculation results of wired elements show that compared with the traditional support wall structure, the cover plate 100 The stress at the interface with the wafer 102 is reduced by about 30%. Therefore, failures such as interface delamination and cracks can be improved, and the reliability of packaging can be improved.

3. By using the solder resist layer 107 to wrap the metal layer 106 around the edge of the wafer 102, so that the metal layer 106 does not directly contact the outside world, this aspect reduces the challenge to the cutting process step, because in In the cutting process, the cutting of the metal layer 106 is reduced, and the types of materials to be cut are reduced, thereby reducing fragments and cracks caused by cutting, and improving the cutting yield. On the other hand, since the metal layer 106 is not in direct contact with the outside world, the peeling stress between different interfaces at the boundary is reduced, and moisture can also be prevented from entering the package along the metal layer 106, improving the reliability of the product during service .

4. By extending the metal layer 106 to the front surface 100a of the cover plate, and at the same time connecting to the side of the pad 104, this structure enhances the bonding force and stability between the metal layer 106 and the pad 104 on the one hand, and improves the structural stability. Reliability; on the other hand, instead of the high-cost through-silicon via technology, the new structure is low-cost and easy to implement compared with the complex process and high-cost through-silicon via technology.

The following specific examples of the present invention, together with the accompanying drawings, describe the above-mentioned features and advantages of the present invention in detail.

Description of drawings

FIG. 1 is a schematic diagram of a low-cost, high-reliability chip-size CIS package structure drawn according to the present invention.

2( a ) to ( e ) are cross-sectional schematic diagrams of a manufacturing process of a low-cost, high-reliability chip-size CIS package drawn according to an embodiment of the present invention.

Reference numerals in the figure: 100. cover plate, 100a. front side of the cover plate, 100b. back side of the cover plate, 100c. cavity structure, 101. bonding glue, 102. wafer, 102a. front side of the wafer, 102b. back side of the wafer, 103. Functional area, 104. Pad, 105. Passivation layer, 106. Metal layer, 107. Solder resist layer, 108. Solder ball.

Detailed ways

The present invention will be described in more detail below with reference to accompanying drawing:

As shown in FIG. 1 , a low-cost, high-reliability chip-size CIS package according to an embodiment of the present invention has a structure comprising: 1. a cover plate 100, and a cavity structure 100c is made on the front surface 100a of the cover plate; 2. a crystal Circle 102, which includes wafer front 102a and wafer back 102b; 3. Functional area 103 and pad 104, described functional area 103 and pad 104 are all distributed on wafer front 102a, wherein pad 104 is distributed in functional area 103, and achieve conduction; 4. Bonding glue 101, located between the cover plate 100 and the wafer 102, to bond the two together; 5. Redistribution circuit layer, the redistribution circuit layer is located on the wafer 102 The round back 102b includes a passivation layer 105, a metal layer 106 and a solder resist layer 107, and conducts the pad 104 of the wafer front 102a to the solder ball 108 position of the wafer back 102b through the redistribution circuit layer; 7. Solder balls 108, located on the redistribution circuit layer on the backside of the wafer 102b.

A low-cost, high-reliability chip-size CIS package manufacturing process of this embodiment will be described in detail below with reference to FIGS. 2( a ) to ( e ). 2( a ) to ( e ) are cross-sectional schematic diagrams of a manufacturing process of a low-cost, high-reliability chip-size CIS package drawn according to an embodiment of the present invention.

Step 1, making the cover plate 100:

Please refer to Fig. 2(a), first provide the cover plate 100, uniformly coat a layer of photoresist on the front surface 100a of the cover plate through a glue equalizer, and open the window for making the cavity structure 100c by using the exposure and development process, and then A cavity structure 100c is formed on the front surface 100a of the cover plate through an etching process, and finally the coated photoresist is removed.

In this embodiment, the material of the cover plate 100 may be transparent materials such as glass, quartz, and plastic. The cross section of the cavity structure 100c may be circular or square.

Step 2, wafer 102 bonding:

Please refer to FIG. 2( b ), first, a layer of bonding glue 101 is coated on the front surface 100a of the cover plate, and then the front surface 100a of the cover plate is bonded to the front surface 102a of the wafer by using a bonding machine.

In this embodiment, the bonding glue 101 can be coated by a rolling brush, and the bonding glue 101 is a resin-based adhesive.

Step 3, wafer 102 thinning:

Please refer to FIG. 2(c), firstly, the wafer back 102b is ground by a grinder to reduce the thickness to a set thickness; then, after grinding, the wafer back 102b is subjected to stress-relief plasma etching.

In this embodiment, the thickness of the wafer 102 is reduced from the initial 600 to 700 microns to about 130 microns; stress relief plasma etching is to remove the internal stress in the wafer 102 due to grinding and improve the warpage of the wafer 102. Qu, to facilitate the follow-up process.

Step 4, silicon removal, the removal step is carried out in three steps:

1. Referring to FIG. 2(c), the silicon around the backside 102b of the wafer is removed by etching or dicing until the pads 104 on the frontside 102a of the wafer are exposed.

In this embodiment, the etching method includes: a. dry etching process of plasma etching, such as deep reactive ion etching (DRIE); b. wet etching process including silicon etching solution. The cutting method includes: directly cutting and forming by using a V-cut knife (V-groove knife).

2. Referring to FIG. 2(c), use a coater or a sprayer to coat a layer of passivation layer 105 on the backside 102b of the wafer (including the surface of the exposed pad 104).

In this embodiment, the passivation layer 105 is an insulating material, which may be oxide (such as silicon dioxide) or nitride (such as silicon nitride).

3. Please refer to FIG. 2(d), and use etching or cutting to remove the surrounding area of the wafer 102, including part of the passivation layer 105, silicon, part of the pad 104 and part of the bonding glue 101. The side of the pad 104 and part of the front surface 102a of the cover are exposed;

In this embodiment, the etching method includes: a. dry etching process of plasma etching, such as deep reactive ion etching (DRIE); b. wet etching process including silicon etching solution. The cutting method includes: directly cutting and forming by using a V-cut knife (V-groove knife).

Step 5, making metal layer 106 and solder resist layer 107:

Please refer to FIG. 2(e), first, a metal layer 106 is integrally fabricated on the wafer back 102b by sputtering or electroplating, and patterned to form a circuit; then a passivation layer is coated on the metal layer 106 107, and form an opening at the position of the preset solder ball 108.

In this embodiment, when the metal layer 106 is patterned, the patterning includes removing the metal layer 106 at the peripheral edge of the wafer 102, so that the solder resist layer 107 removes the metal layer 106 at the peripheral edge. 106 for wrapping, so as to avoid direct contact between the metal layer 106 and the outside world.

Step 6, making solder balls 108:

Referring to FIG. 2( e ), solder balls 108 are formed on the redistribution circuit layer on the backside of the wafer 102b, and then the wafer 102 is diced around to form a single chip package.

In this embodiment, the solder balls 108 can be made by ball planting or stencil printing.

The description of the embodiments of the invention has been made for the purpose of effectively illustrating and describing the invention, but by way of example only and should not be construed as limiting the scope of the invention as defined by the claims. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Protection for the present invention therefore covers modifications within the spirit and scope of the invention as defined by the claims.

Claims (5)

1. a low cost and high reliability chip size CIS encapsulating structure, is characterized in that comprising:

There is provided wafer, be manufactured with multiple chip region comprising at wafer frontside tool, chip region comprises the functional areas and the pad of edge that are positioned at central authorities;

Cover plate, covers one deck cover plate in wafer frontside, is wherein manufactured with cavity structure in the central authorities in cover plate front, thus forms a closed cavity between cover plate and wafer;

The distribution again line layer of wafer rear, distribution again line layer is made up of passivation layer, metal level and welding resisting layer, by making distribution again line layer, the pad of wafer frontside being conducting to wafer rear, and being connected with the soldered ball of wafer rear;

Metal level in described wafer rear distribution again line layer extends to cover plate front, simultaneously at crystal round fringes place wrap up by welding resisting layer and directly do not contact with the external world.

2. encapsulating structure according to claim 1, is characterized in that, wherein said chip is CIS chip, MEMS IC or integrated chip.

3. prepare the method for a kind of low cost and high reliability chip size CIS encapsulating structure according to claim 1, it is characterized in that, comprise the following steps:

Step 1, makes cover plate: make cavity structure in cover plate front;

Step 2, wafer bonding: utilize bonder, by being coated with one deck bonding glue in cover plate front, is bonded together cover plate front with wafer frontside;

Step 3, wafer is thinning, and thinning process carries out in two steps: first, by grinder, grinds wafer rear, wafer is thinned to setting thickness; Then, destressing plasma etching is carried out to the wafer rear after thinning;

Step 4, silicon is removed, and silicon is removed process and divided three steps to carry out: first, removed by the silicon of wafer rear surrounding, expose the pad of wafer frontside; Secondly, at wafer rear, comprise the bond pad surface exposed and be coated with one deck passivation layer; Finally, to the peripheral regions of wafer, comprise partial deactivation layer, silicon, part pad and moiety glue and again remove, by the side of pad and partial cover plate face exposure out;

Step 5, makes metal level and welding resisting layer at wafer rear successively, thus pad is conducting to the default soldered ball position of wafer rear;

Step 6, makes soldered ball: be formed at by soldered ball on the distribution again line layer of wafer rear, then the surrounding cutting of wafer formed to the encapsulation of single chips.

4. method according to claim 3, is characterized in that, it is adopt the dry etch process of plasma etching, the wet-etching technology comprising process silicon etching solution and V-cut cutter directly to cut one of these three kinds of modes to carry out that described silicon removes technique step.

5. method according to claim 3, is characterized in that, the thickness of welding resisting layer is no more than 1.5 times of passivation layer thickness.